47 lines
883 B
VHDL
47 lines
883 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Comparator is
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generic( BITCOUNT : integer := 8 );
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port(
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X_MANT, Y_MANT : in std_logic_vector((BITCOUNT-1) downto 0);
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NEED_SWAP : out std_logic
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);
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end Comparator;
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architecture ComparatorArch of Comparator is
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signal X_GT_Y : std_logic_vector((BITCOUNT-1) downto 0);
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signal Y_GT_X : std_logic_vector((BITCOUNT-1) downto 0);
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begin
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X_GT_Y <= X_MANT and (not Y_MANT);
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Y_GT_X <= (not X_MANT) and Y_MANT;
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NEED_SWAP_COMPUTE: process (X_GT_Y, Y_GT_X)
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variable SWAP : std_logic;
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variable SWAP_CARRY : std_logic;
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begin
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SWAP := '0';
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SWAP_CARRY := '1';
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for i in (BITCOUNT-1) downto 0 loop
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SWAP := SWAP or ((not(X_GT_Y(i)) and Y_GT_X(i)) and SWAP_CARRY);
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SWAP_CARRY := SWAP_CARRY and (not(X_GT_Y(i) and not(Y_GT_X(i))));
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end loop;
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NEED_SWAP <= SWAP;
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end process;
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end ComparatorArch;
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