166 lines
4.9 KiB
VHDL
166 lines
4.9 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY SpecialCasesTest IS
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END SpecialCasesTest;
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ARCHITECTURE behavior OF SpecialCasesTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT SpecialCasesCheck
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PORT(
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X : IN std_logic_vector(31 downto 0);
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Y : IN std_logic_vector(31 downto 0);
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isNaN : OUT std_logic;
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isZero : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal X : std_logic_vector(31 downto 0) := (others => '0');
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signal Y : std_logic_vector(31 downto 0) := (others => '0');
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--Outputs
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signal isNaN : std_logic;
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signal isZero : std_logic;
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-- No clocks detected in port list. Replace clock below with
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-- appropriate port name
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signal clock : std_logic;
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signal expectedNaN : std_logic;
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signal expectedZero : std_logic;
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signal error : std_logic;
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constant clock_period : time := 1 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: SpecialCasesCheck PORT MAP (
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X => X,
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Y => Y,
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isNaN => isNaN,
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isZero => isZero
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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test_process :process
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begin
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X <= "01111111111111111111111111111111"; -- NaN
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Y <= "01111111111111111111111111111111"; -- NaN
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expectedNaN <= '1';
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expectedZero <= '0';
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wait for clock_period;
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X <= "01111111111111111111111111111111"; -- NaN
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Y <= "01000101100101100111100101001100"; -- 4815.162342
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expectedNaN <= '1';
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expectedZero <= '0';
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wait for clock_period;
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X <= "01000101100101100111100101001100"; -- 4815.162342
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Y <= "01111111111111111111111111111111"; -- NaN
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expectedNaN <= '1';
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expectedZero <= '0';
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wait for clock_period;
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X <= "01111111111111111111111111111111"; -- NaN
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Y <= "01111111100000000000000000000000"; -- +Inf
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expectedNaN <= '1';
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expectedZero <= '0';
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wait for clock_period;
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X <= "01111111100000000000000000000000"; -- +Inf
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Y <= "01111111100000000000000000000000"; -- +Inf
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "01111111100000000000000000000000"; -- +Inf
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Y <= "11111111100000000000000000000000"; -- -Inf
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expectedNaN <= '1';
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expectedZero <= '1';
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wait for clock_period;
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X <= "11111111100000000000000000000000"; -- -Inf
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Y <= "01111111100000000000000000000000"; -- +Inf
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expectedNaN <= '1';
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expectedZero <= '1';
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wait for clock_period;
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X <= "01000101100101100111100101001100"; -- 4815.162342
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Y <= "01111111100000000000000000000000"; -- +Inf
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "11111111100000000000000000000000"; -- -Inf
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Y <= "01000101100101100111100101001100"; -- 4815.162342
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "01000101100101100111100101001100"; -- 4815.162342
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Y <= "01000101100101100111100101001100"; -- 4815.162342
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "01000101100101100111100101001100"; -- 4815.162342
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Y <= "01111101001101101011100011111101"; -- 1.518e+37
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "01000101100101100111100101001100"; -- 4815.162342
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Y <= "11000101100101100111100101001100"; -- -4815.162342
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expectedNaN <= '0';
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expectedZero <= '1';
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wait for clock_period;
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X <= "11000101100101100111100101001100"; -- -4815.162342
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Y <= "01000101100101100111100101001100"; -- 4815.162342
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expectedNaN <= '0';
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expectedZero <= '1';
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wait for clock_period;
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X <= "01111101001101101011100011111101"; -- 1.518e+37
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Y <= "11000101100101100111100101001100"; -- -4815.162342
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "11000101100101100111100101001100"; -- -4815.162342
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Y <= "11000101100101100111100101001100"; -- -4815.162342
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "11000101100101100111100101001100"; -- -4815.162342
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Y <= "11111101001101101011100011111101"; -- -1.518e+37
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "01000101100101100111100101001100"; -- 4815.162342
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Y <= "01111101001101101011100011111101"; -- 1.518e+37
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "00000000000000000000000000000000"; -- 0
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Y <= "00000000000000000000000000000000"; -- 0
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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X <= "00000000000000000000000000000000"; -- +0
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Y <= "10000000000000000000000000000000"; -- -0
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expectedNaN <= '0';
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expectedZero <= '1';
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wait for clock_period;
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X <= "00000000000000000000000000000000"; -- 0
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Y <= "01000101100101100111100101001100"; -- 4815.162342
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expectedNaN <= '0';
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expectedZero <= '0';
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wait for clock_period;
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end process;
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error <= (expectedNaN xor isNaN) or (expectedZero xor isZero);
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END;
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