78 lines
1.7 KiB
VHDL
78 lines
1.7 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY ComparatorTest IS
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END ComparatorTest;
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ARCHITECTURE behavior OF ComparatorTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT Comparator
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PORT(
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X_MANT : IN std_logic_vector(7 downto 0);
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Y_MANT : IN std_logic_vector(7 downto 0);
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NEED_SWAP : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal X_MANT : std_logic_vector(7 downto 0) := (others => '0');
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signal Y_MANT : std_logic_vector(7 downto 0) := (others => '0');
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--Outputs
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signal NEED_SWAP : std_logic;
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signal clock: std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: Comparator PORT MAP (
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X_MANT => X_MANT,
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Y_MANT => Y_MANT,
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NEED_SWAP => NEED_SWAP
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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test_proc: process
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begin
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X_MANT <= "00000000";
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Y_MANT <= "00000000";
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wait for clock_period;
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X_MANT <= "01011010";
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Y_MANT <= "01100000";
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wait for clock_period;
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X_MANT <= "00111100";
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Y_MANT <= "10000100";
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wait for clock_period;
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X_MANT <= "10000000";
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Y_MANT <= "01111111";
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wait for clock_period;
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X_MANT <= "01110100";
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Y_MANT <= "01101000";
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wait for clock_period;
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X_MANT <= "01111111";
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Y_MANT <= "10000000";
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wait for clock_period;
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X_MANT <= "10101010";
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Y_MANT <= "01010101";
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wait for clock_period;
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X_MANT <= "01010101";
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Y_MANT <= "10101010";
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wait for clock_period;
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end process;
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END;
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