84 lines
1.6 KiB
VHDL
84 lines
1.6 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity PipelineStageOne is
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port(
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X, Y : in std_logic_vector(31 downto 0);
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DIFF_EXP_ABS : out std_logic_vector(8 downto 0);
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A, B : out std_logic_vector(31 downto 0);
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IS_NAN, IS_ZERO : out std_logic
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);
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end PipelineStageOne;
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architecture StageOneArch of PipelineStageOne is
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component SpecialCasesCheck is
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port(
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X, Y : in std_logic_vector(31 downto 0);
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IS_NAN, IS_ZERO : out std_logic
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);
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end component;
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component PrepareForShift is
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port(
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X, Y : in std_logic_vector(30 downto 0);
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DIFF_EXP : out std_logic_vector(8 downto 0);
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NEED_SWAP : out std_logic
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);
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end component;
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component Swap is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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X_IN, Y_IN : in std_logic_vector((BITCOUNT-1) downto 0);
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SW : in std_logic;
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X_OUT, Y_OUT : out std_logic_vector((BITCOUNT-1) downto 0)
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);
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end component;
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component TwoComplement is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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DIFF_EXP_C2 : in std_logic_vector((BITCOUNT-1) downto 0);
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DIFF_EXP : out std_logic_vector((BITCOUNT-1) downto 0)
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);
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end component;
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signal DIFF_EXP_C2 : std_logic_vector(8 downto 0);
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signal SW : std_logic;
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begin
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SPC : SpecialCasesCheck
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port map (X => X, Y => Y, IS_NAN => IS_NAN, IS_ZERO => IS_ZERO);
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PFS : PrepareForShift
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port map (X => X(30 downto 0), Y => Y(30 downto 0), DIFF_EXP => DIFF_EXP_C2, NEED_SWAP => SW);
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S : Swap
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generic map (BITCOUNT => 32)
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port map (X_IN => X, Y_IN => Y, SW => SW, X_OUT => A, Y_OUT => B);
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C2 : TwoComplement
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generic map (BITCOUNT => 9)
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port map (DIFF_EXP_C2 => DIFF_EXP_C2, DIFF_EXP => DIFF_EXP_ABS);
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end StageOneArch;
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