110 lines
3.0 KiB
VHDL
110 lines
3.0 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY IEEE754AdderTest IS
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END IEEE754AdderTest;
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ARCHITECTURE behavior OF IEEE754AdderTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT IEEE754Adder
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PORT(
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X : IN std_logic_vector(31 downto 0);
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Y : IN std_logic_vector(31 downto 0);
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RESET : IN std_logic;
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CLK : IN std_logic;
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RESULT : OUT std_logic_vector(31 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal X : std_logic_vector(31 downto 0) := (others => '0');
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signal Y : std_logic_vector(31 downto 0) := (others => '0');
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signal RESET : std_logic := '0';
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signal CLK : std_logic := '0';
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--Outputs
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signal RESULT : std_logic_vector(31 downto 0);
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-- Clock period definitions
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constant CLK_period : time := 50 ns; -- MESSA A CASO. VALUTARE IL PERIODO GIUSTO
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: IEEE754Adder PORT MAP (
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X => X,
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Y => Y,
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RESET => RESET,
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CLK => CLK,
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RESULT => RESULT
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);
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-- Clock process definitions
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CLK_process :process
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begin
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CLK <= '0';
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wait for CLK_period/2;
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CLK <= '1';
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wait for CLK_period/2;
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end process;
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-- Stimulus process
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stim_proc: process
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begin
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RESET <= '1';
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wait for 2*CLK_period;
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RESET <= '0';
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-- TODO: FINIRE TEST
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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wait for CLK_period;
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X <= "00001000000000000000111000000000";
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Y <= "00000010000001111000000000000000";
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wait for CLK_period;
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X <= "01000000010110011001100110011010";
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Y <= "01100110010001110000110110000001";
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wait for CLK_period;
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X <= "01111111100000000000000000000000";
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Y <= "11111111100000000000000000000000";
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wait for CLK_period;
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X <= "01000000100000000000000000000000";
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Y <= "01111111100000000000000000000000";
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wait for CLK_period;
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X <= "00000000100100000000000000000000";
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Y <= "10000000011111111111111111111111";
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wait for CLK_period;
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X <= "11001100000111100111101111110100";
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Y <= "11001111111110111111011100110110";
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wait for CLK_period;
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X <= "01111111011111111111111111111111";
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Y <= "01111110011111111111111111111111";
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wait for CLK_period;
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X <= "11111111111111111111111111111111";
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Y <= "00111111100000000000000000000000";
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wait for CLK_period;
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X <= "00110110100111000010111100011010";
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Y <= "11111111111111111111000001111111";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "10000000000000000000000000000000";
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wait for CLK_period;
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X <= "01001100111010110111100110100011";
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Y <= "11001100111010110111100110100011";
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wait for CLK_period;
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X <= "01000010001010000000000000000000";
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Y <= "01000001101110000000000000000000";
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wait for CLK_period;
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X <= "01101000111011011000111011010101";
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Y <= "00011001001011011001100001111101";
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wait;
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end process;
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END;
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