Creato modulo CarryLookAhead

EqualCheck.vhd

@@ -1,42 +1,32 @@
-library IEEE;
+library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
-use IEEE.STD_LOGIC_1164.ALL;
-
-
+
 entity EqualCheck is
 
 	generic(
-
-	generic(
-		BITCOUNT: integer := 8
-	);
-	
-
-	port(
 		BITCOUNT: integer := 8
-		X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
-
-		IS_EQUAL : out std_logic
-
-	);
-	
+	);
+
+	port(
+		X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+		IS_EQUAL : out std_logic
+	);
+	
+end EqualCheck;
+
 architecture EqualCheckArch of EqualCheck is
-end EqualCheck;
-
-
-architecture EqualCheckArch of EqualCheck is
-
+
+	signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
 
-	signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
+begin
 
-
-begin
-
+	COMP_VEC <= X xor Y;
+
+	RES_COMPUTE: process (COMP_VEC)
 
-	COMP_VEC <= X xor Y;
+		variable RES_TMP : std_logic;
 
-	
+	begin
 	
-	RES_COMPUTE: process (COMP_VEC)
 		RES_TMP := '0';