diff --git a/AddSub.vhd b/AddSub.vhd
index 68a8a25..dc22f9c 100644
--- a/AddSub.vhd
+++ b/AddSub.vhd
@@ -2,41 +2,57 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AddSub is
- generic( BITCOUNT: integer := 8 );
- port(
- X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
- isSub: in std_logic := '0';
- result: out std_logic_vector((BITCOUNT-1) downto 0);
- overflow: out std_logic
+
+ generic(
+ BITCOUNT : integer := 8
);
+
+ port(
+ X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+ IS_SUB : in std_logic := '0';
+ RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
+ OVERFLOW : out std_logic
+ );
+
end AddSub;
architecture AddSubArch of AddSub is
+
component Adder is
- generic( BITCOUNT: integer := 8 );
- port(
- X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
- carry_in: in std_logic;
- result: out std_logic_vector((BITCOUNT-1) downto 0);
- carry_out: out std_logic
+
+ generic(
+ BITCOUNT : integer := 8
);
+
+ port(
+ X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+ CARRY_IN : in std_logic;
+ RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
+ CARRY_OUT : out std_logic
+ );
+
end component;
- signal Y2: std_logic_vector((BITCOUNT-1) downto 0);
- signal C_out: std_logic;
+ signal Y2 : std_logic_vector((BITCOUNT-1) downto 0);
+ signal C_OUT : std_logic;
+
begin
- y2proc: process(Y, isSub)
+ Y2_PROCESS : process(Y, IS_SUB)
+
begin
+
for i in Y2'range loop
- Y2(i) <= Y(i) xor isSub;
+ Y2(i) <= Y(i) xor IS_SUB;
end loop;
+
end process;
- ADD: Adder
- generic map ( BITCOUNT => BITCOUNT )
- port map ( X => X, Y => Y2, carry_in => isSub, result => result, carry_out => C_out );
+ ADD : Adder
+ generic map (BITCOUNT => BITCOUNT)
+ port map (X => X, Y => Y2, CARRY_IN => IS_SUB, RESULT => RESULT, CARRY_OUT => C_OUT);
- overflow <= ((not isSub) and C_out) or (isSub and (not C_out));
+ OVERFLOW <= ((not IS_SUB) and C_OUT) or (IS_SUB and (not C_OUT));
+
end AddSubArch;
diff --git a/Adder.vhd b/Adder.vhd
index c7e6616..92413e8 100644
--- a/Adder.vhd
+++ b/Adder.vhd
@@ -3,37 +3,51 @@ use IEEE.STD_LOGIC_1164.ALL;
entity Adder is
- generic( BITCOUNT: integer := 8 );
- port(
- X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
- carry_in: in std_logic;
- result: out std_logic_vector((BITCOUNT-1) downto 0);
- carry_out: out std_logic
+
+ generic(
+ BITCOUNT : integer := 8
);
+
+ port(
+ X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+ CARRY_IN : in std_logic;
+ RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
+ CARRY_OUT : out std_logic
+ );
+
end Adder;
architecture CarryLookAheadArch of Adder is
- signal generation: std_logic_vector((BITCOUNT-1) downto 0);
- signal propagation: std_logic_vector((BITCOUNT-1) downto 0);
- signal carry: std_logic_vector((BITCOUNT-1) downto 0);
- signal sum_no_carry: std_logic_vector((BITCOUNT-1) downto 0);
-begin
- generation <= X and Y;
- propagation <= X or Y;
- sum_no_carry <= X xor Y;
- carry_look_ahead: process (generation, propagation, carry_in)
- variable C: std_logic;
+ signal GENERATION : std_logic_vector((BITCOUNT-1) downto 0);
+ signal PROPAGATION : std_logic_vector((BITCOUNT-1) downto 0);
+ signal CARRY : std_logic_vector((BITCOUNT-1) downto 0);
+ signal SUM_NO_CARRY : std_logic_vector((BITCOUNT-1) downto 0);
+
+begin
+
+ GENERATION <= X and Y;
+ PROPAGATION <= X or Y;
+ SUM_NO_CARRY <= X xor Y;
+
+ CARRY_LOOK_AHEAD_PROCESS : process (GENERATION, PROPAGATION, CARRY_IN)
+
+ variable C : std_logic;
+
begin
- C := carry_in;
- carry(0) <= C;
+
+ C := CARRY_IN;
+ CARRY(0) <= C;
+
for i in 1 to (BITCOUNT-1) loop
- C := generation(i-1) or (propagation(i-1) and C);
- carry(i) <= C;
+ C := GENERATION(i-1) or (PROPAGATION(i-1) and C);
+ CARRY(i) <= C;
end loop;
+
end process;
- result <= sum_no_carry xor carry;
- carry_out <= (X(BITCOUNT-1) and Y(BITCOUNT-1)) or (X(BITCOUNT-1) and carry(BITCOUNT-1)) or (carry(BITCOUNT-1) and Y(BITCOUNT-1));
+ RESULT <= SUM_NO_CARRY xor CARRY;
+ CARRY_OUT <= (X(BITCOUNT-1) and Y(BITCOUNT-1)) or (X(BITCOUNT-1) and CARRY(BITCOUNT-1)) or (CARRY(BITCOUNT-1) and Y(BITCOUNT-1));
+
end CarryLookAheadArch;
diff --git a/CarryLookAhead.vhd b/CarryLookAhead.vhd
new file mode 100644
index 0000000..1d2b652
--- /dev/null
+++ b/CarryLookAhead.vhd
@@ -0,0 +1,43 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity CarryLookAhead is
+
+ port(
+ X, Y : in std_logic_vector(47 downto 0);
+ OP : in std_logic;
+ RESULT : out std_logic_vector(47 downto 0);
+ OVERFLOW : out std_logic
+ );
+
+end CarryLookAhead;
+
+architecture CarryLookAheadArch of CarryLookAhead is
+
+ --signal OVERFLOW_TMP : std_logic;
+
+ component AddSub is
+
+ generic(
+ BITCOUNT : integer := 8
+ );
+
+ port(
+ X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+ IS_SUB : in std_logic := '0';
+ RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
+ OVERFLOW : out std_logic
+ );
+
+ end component;
+
+begin
+
+ CLA : AddSub
+ generic map (BITCOUNT => 48)
+ port map (X => X, Y => Y, IS_SUB => OP, RESULT => RESULT, OVERFLOW => OVERFLOW);
+
+ --OVERFLOW <= OVERFLOW_TMP xor OP;
+
+end CarryLookAheadArch;
+
diff --git a/Comparator.vhd b/Comparator.vhd
index 338fab0..2e534f7 100644
--- a/Comparator.vhd
+++ b/Comparator.vhd
@@ -4,7 +4,9 @@ use IEEE.STD_LOGIC_1164.ALL;
entity Comparator is
- generic( BITCOUNT : integer := 8 );
+ generic(
+ BITCOUNT : integer := 8
+ );
port(
X_MANT, Y_MANT : in std_logic_vector((BITCOUNT-1) downto 0);
@@ -23,7 +25,7 @@ begin
X_GT_Y <= X_MANT and (not Y_MANT);
Y_GT_X <= (not X_MANT) and Y_MANT;
- NEED_SWAP_COMPUTE: process (X_GT_Y, Y_GT_X)
+ NEED_SWAP_PROCESS : process (X_GT_Y, Y_GT_X)
variable SWAP : std_logic;
variable SWAP_CARRY : std_logic;
diff --git a/EqualCheck.vhd b/EqualCheck.vhd
index 7e50fc8..b8be976 100644
--- a/EqualCheck.vhd
+++ b/EqualCheck.vhd
@@ -1,42 +1,32 @@
-library IEEE;
+library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
-
-entity EqualCheck is
-
+entity EqualCheck is
generic(
BITCOUNT: integer := 8
);
-
- port(
- X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
- IS_EQUAL : out std_logic
- );
-
-end EqualCheck;
-architecture EqualCheckArch of EqualCheck is
-
- signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
-
-begin
-
+ port(
+ X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+ IS_EQUAL : out std_logic
+ );
+
+end EqualCheck;
+architecture EqualCheckArch of EqualCheck is
+ signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
+begin
COMP_VEC <= X xor Y;
-
- RES_COMPUTE: process (COMP_VEC)
-
- variable RES_TMP : std_logic;
-
+ RES_COMPUTE: process (COMP_VEC)
+ variable RES_TMP : std_logic;
begin
-
+
RES_TMP := '0';
-
- for i in COMP_VEC'range loop
- RES_TMP := RES_TMP or COMP_VEC(i);
+
+ for i in COMP_VEC'range loop
+ RES_TMP := RES_TMP or COMP_VEC(i);
end loop;
-
+
IS_EQUAL <= not RES_TMP;
-
+
end process;
-
end EqualCheckArch;
diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise
index 84a5638..890df49 100644
--- a/IEEE754Adder.xise
+++ b/IEEE754Adder.xise
@@ -93,6 +93,10 @@
+
+
+
+
@@ -148,8 +152,8 @@
-
-
+
+
@@ -213,9 +217,9 @@
-
-
-
+
+
+
@@ -284,11 +288,11 @@
-
+
-
+
@@ -299,10 +303,10 @@
-
-
-
-
+
+
+
+
@@ -327,7 +331,7 @@
-
+
@@ -351,8 +355,6 @@
-
-
@@ -373,7 +375,6 @@
-
@@ -430,10 +431,9 @@
-
-
+
diff --git a/OperationCheck.vhd b/OperationCheck.vhd
index f002389..0d1c001 100644
--- a/OperationCheck.vhd
+++ b/OperationCheck.vhd
@@ -2,15 +2,18 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OperationCheck is
+
port(
X_SIGN, Y_SIGN : in std_logic;
OP, RES_SIGN : out std_logic
);
+
end OperationCheck;
architecture OperationCheckArch of OperationCheck is
begin
+
OP <= X_SIGN xor Y_SIGN;
RES_SIGN <= X_SIGN;
diff --git a/PrepareForShift.vhd b/PrepareForShift.vhd
index 54a44ba..1ce3603 100644
--- a/PrepareForShift.vhd
+++ b/PrepareForShift.vhd
@@ -2,41 +2,80 @@ library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PrepareForShift is
+
port(
- X, Y: in std_logic_vector(31 downto 0);
- DIFF_EXP: out std_logic_vector(8 downto 0);
- SW: out std_logic
+ X, Y : in std_logic_vector(30 downto 0);
+ DIFF_EXP : out std_logic_vector(8 downto 0);
+ NEED_SWAP : out std_logic
);
+
end PrepareForShift;
architecture PrepareForShiftArch of PrepareForShift is
- signal LT: std_logic;
- signal EQ: std_logic;
+
+ signal LT : std_logic;
+ signal EQ : std_logic;
+ signal RESULT : std_logic_vector(7 downto 0);
+ signal OVERFLOW : std_logic;
component Comparator is
- generic( BITCOUNT: integer := 8 );
- port(
- xT, yT: in std_logic_vector((BITCOUNT-1) downto 0);
- needSwap: out std_logic
- );
+
+ generic(
+ BITCOUNT: integer := 8
+ );
+
+ port(
+ X_MANT, Y_MANT : in std_logic_vector((BITCOUNT-1) downto 0);
+ NEED_SWAP : out std_logic
+ );
+
+ end component;
+
+ component AddSub is
+
+ generic(
+ BITCOUNT : integer := 8
+ );
+
+ port(
+ X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+ IS_SUB : in std_logic := '0';
+ RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
+ OVERFLOW : out std_logic
+ );
+
end component;
begin
- C: Comparator
- port map (xT => X(22 downto 0), yT => Y(22 downto 0), needSwap => LT);
-
- --istaziare sommatore la cui uscita va mappata in X(31 downto 23), Y(31 downto 23), DIFF_EXP
+
+ C : Comparator
+ generic map (BITCOUNT => 23)
+ port map (X_MANT => X(22 downto 0), Y_MANT => Y(22 downto 0), NEED_SWAP => LT);
- EQ <= '0';
+ ADD_SUB : AddSub
+ generic map (BITCOUNT => 8)
+ port map (X => X(30 downto 23), Y => Y(30 downto 23), IS_SUB => '1', RESULT => RESULT, OVERFLOW => OVERFLOW);
+
+ EQUAL_EXP_PROCESS : process (RESULT, OVERFLOW)
+
+ variable EQ_TMP : std_logic;
- O: process (DIFF_EXP)
begin
- for i in 8 downto 0 loop
- EQ <= EQ or DIFF_EXP(i);
+
+ EQ_TMP := '0';
+
+ for i in 7 downto 0 loop
+ EQ_TMP := EQ_TMP or RESULT(i);
end loop;
+
+ EQ_TMP := EQ_TMP or OVERFLOW;
+ EQ_TMP := not EQ_TMP;
+ EQ <= EQ_TMP;
+
end process;
- SW <= DIFF_EXP(8) or (EQ and LT);
+ NEED_SWAP <= OVERFLOW or (EQ and LT);
+ DIFF_EXP <= OVERFLOW & RESULT;
end PrepareForShiftArch;
diff --git a/SpecialCasesCheck.vhd b/SpecialCasesCheck.vhd
index 231ef01..78173f2 100644
--- a/SpecialCasesCheck.vhd
+++ b/SpecialCasesCheck.vhd
@@ -33,10 +33,10 @@ architecture SpecialCasesCheckArch of SpecialCasesCheck is
begin
- NC: NaNCheck
+ NC : NaNCheck
port map (X => X, Y => Y, IS_NAN => IS_NAN);
- ZC: ZeroCheck
+ ZC : ZeroCheck
port map (X => X, Y => Y, IS_ZERO => IS_ZERO);
end SpecialCasesCheckArch;
diff --git a/Swap.vhd b/Swap.vhd
index 35bc370..3743659 100644
--- a/Swap.vhd
+++ b/Swap.vhd
@@ -19,7 +19,7 @@ architecture SwapArch of Swap is
begin
- SWAP_PROCESS: process(X_IN, Y_IN, SW)
+ SWAP_PROCESS : process (X_IN, Y_IN, SW)
begin
diff --git a/TwoComplement.vhd b/TwoComplement.vhd
index 4877bd8..4f74ac3 100644
--- a/TwoComplement.vhd
+++ b/TwoComplement.vhd
@@ -23,7 +23,7 @@ begin
SIGN <= DIFF_EXP_C2(BITCOUNT-1);
- C2_PROCESS : process(DIFF_EXP_C2, SIGN)
+ C2_PROCESS : process (DIFF_EXP_C2, SIGN)
begin
@@ -33,7 +33,7 @@ begin
end process;
- SUM : process(DIFF_EXP_ABS, SIGN)
+ SUM : process (DIFF_EXP_ABS, SIGN)
variable CARRY : std_logic;
diff --git a/TypeCheck.vhd b/TypeCheck.vhd
index 77b4d20..e198f0c 100644
--- a/TypeCheck.vhd
+++ b/TypeCheck.vhd
@@ -22,7 +22,7 @@ begin
G_BUS <= N(30 downto 23);
T_BUS <= N(22 downto 0);
- G_compute: process (G_BUS)
+ G_PROCESS : process (G_BUS)
variable G_TMP : std_logic;
@@ -38,7 +38,7 @@ begin
end process;
- T_compute: process (T_BUS)
+ T_PROCESS : process (T_BUS)
variable T_TMP : std_logic;
diff --git a/ZeroCheck.vhd b/ZeroCheck.vhd
index 78b151c..a0d618d 100644
--- a/ZeroCheck.vhd
+++ b/ZeroCheck.vhd
@@ -42,7 +42,7 @@ begin
IS_SAME_SIGN <= S_SIGN xnor Y_SIGN;
- AbsCheck: EqualCheck
+ ABS_CHECK : EqualCheck
generic map ( BITCOUNT => 31 )
port map (X => X_ABS, Y => Y_ABS, IS_EQUAL => IS_SAME_ABS_VALUE);