Merge branch 'master' of github.com:optimize-fast/IEEE754Adder

Conflicts:
	IEEE754Adder.xise
	TwoComplement.vhd
	fuse.log
	fuseRelaunch.cmd
	isim.log

Comparator.vhd

@@ -3,31 +3,43 @@ use IEEE.STD_LOGIC_1164.ALL;
 
 
 entity Comparator is
-	generic( BITCOUNT: integer := 8 );
+
+	generic( BITCOUNT : integer := 8 );
+	
 	port(
-		xT, yT: in std_logic_vector((BITCOUNT-1) downto 0);
+		X_MANT, Y_MANT : in std_logic_vector((BITCOUNT-1) downto 0);
-		needSwap: out std_logic
+		NEED_SWAP : out std_logic
 	);
+	
 end Comparator;
 
 architecture ComparatorArch of Comparator is
-	signal xGTy: std_logic_vector((BITCOUNT-1) downto 0);
-	signal yGTx: std_logic_vector((BITCOUNT-1) downto 0);
-begin
-	xGTy <= xT and (not yT);
-	yGTx <= (not xT) and yT;
 
-	needSwap_compute: process (xGTy, yGTx)
+	signal X_GT_Y : std_logic_vector((BITCOUNT-1) downto 0);
-		variable SW: std_logic;
+	signal Y_GT_X : std_logic_vector((BITCOUNT-1) downto 0);
-		variable K: std_logic;
+	
+begin
+
+	X_GT_Y <= X_MANT and (not Y_MANT);
+	Y_GT_X <= (not X_MANT) and Y_MANT;
+	
+	NEED_SWAP_COMPUTE: process (X_GT_Y, Y_GT_X)
+	
+		variable SWAP : std_logic;
+		variable SWAP_CARRY : std_logic;
+	
 	begin
-		SW := '0';
+	
-		K := '1';
+		SWAP := '0';
+		SWAP_CARRY := '1';
+		
 		for i in (BITCOUNT-1) downto 0 loop
-			SW := SW or ((not(xGTy(i)) and yGTx(i)) and K);
+			SWAP := SWAP or ((not(X_GT_Y(i)) and Y_GT_X(i)) and SWAP_CARRY);
-			K := K and (not(xGTy(i) and not(yGTx(i))));
+			SWAP_CARRY := SWAP_CARRY and (not(X_GT_Y(i) and not(Y_GT_X(i))));
 		end loop;
-		needSwap <= SW;
+		
+		NEED_SWAP <= SWAP;
+		
 	end process;
 
 end ComparatorArch;

EqualCheck.vhd

@@ -2,26 +2,40 @@ library IEEE;
 
 use IEEE.STD_LOGIC_1164.ALL;
 
-	generic( BITCOUNT: integer := 8 );
+
-	port(
+
-		X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
+entity EqualCheck is
-		isEqual: out std_logic
 
+
+	generic(
+		BITCOUNT: integer := 8
+	);
+	
+
 	port(
 
 		X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
-	signal compVec: std_logic_vector( (BITCOUNT-1) downto 0 );
-begin
-	compVec <= X xor Y;
 
-	res_compute: process (compVec)
+		IS_EQUAL : out std_logic
-		variable res_tmp: std_logic;
+
+	);
+	
+
+end EqualCheck;
+
+
+architecture EqualCheckArch of EqualCheck is
+
 
-		res_tmp := '0';
+	signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
-		for i in compVec'range loop
+
-			res_tmp := res_tmp or compVec(i);
+
+begin
+
 
-		isEqual <= not res_tmp;
+	COMP_VEC <= X xor Y;
+
+	
 
 	RES_COMPUTE: process (COMP_VEC)
 	

IEEE754Adder.xise

@@ -66,22 +66,18 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
     </file>
     <file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
     <file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
-    <file xil_pn:name="FullAdder.vhd" xil_pn:type="FILE_VHDL">
+    <file xil_pn:name="TwoComplementTest.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="227"/>
-    </file>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="227"/>
-    <file xil_pn:name="FullAdderTest.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="227"/>
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="195"/>
-      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="195"/>
-      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="195"/>
     </file>
     <file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
@@ -153,7 +149,7 @@
     <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
     <property xil_pn:name="Device" xil_pn:value="xa6slx4" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
     <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -315,6 +311,7 @@
     <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
     <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -356,6 +353,8 @@
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/AddSubTest" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.AddSubTest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TwoComplementTest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -375,6 +374,7 @@
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.AddSubTest" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -431,6 +431,7 @@
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AddSubTest|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TwoComplementTest|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>

NaNCheck.vhd

@@ -2,37 +2,44 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
 entity NaNCheck is
+
 	port(
-		X, Y: in std_logic_vector(31 downto 0);
+		X, Y : in std_logic_vector(31 downto 0);
-		isNan: out std_logic
+		IS_NAN : out std_logic
 	);
+	
 end NaNCheck;
 
 architecture NaNCheckArch of NaNCheck is
+
 	component TypeCheck is
+	
 		port(
-			N: in std_logic_vector(31 downto 0);
+			N : in std_logic_vector(30 downto 0);
-			NaN, INF: out std_logic
+			NAN, INF : out std_logic
 		);
+		
 	end component;
 	
-	signal xNan: std_logic;
+	signal X_NAN : std_logic;
-	signal xInf: std_logic;
+	signal X_INF : std_logic;
-	signal xSign: std_logic;
+	signal X_SIGN : std_logic;
-	signal yNan: std_logic;
+	signal Y_NAN : std_logic;
-	signal yInf: std_logic;
+	signal Y_INF : std_logic;
-	signal ySign: std_logic;
+	signal Y_SIGN : std_logic;
 	
 begin
+
 	xCheck: TypeCheck
-		port map (N => X, NaN => xNan, INF => xInf);
+		port map (N => X(30 downto 0), NAN => X_NAN, INF => X_INF);
+		
 	yCheck: TypeCheck
-		port map (N => Y, NaN => yNan, INF => yInf);
+		port map (N => Y(30 downto 0), NAN => Y_NAN, INF => Y_INF);
 
-	xSign <= X(31);
+	X_SIGN <= X(31);
-	ySign <= Y(31);
+	Y_SIGN <= Y(31);
 	
-	isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign);
+	IS_NAN <= X_NAN or Y_NAN or (X_INF and X_SIGN and Y_INF and (not Y_SIGN)) or (X_INF and (not X_SIGN) and Y_INF and Y_SIGN);
 	
 end NaNCheckArch;
 

SpecialCasesCheck.vhd

@@ -2,32 +2,43 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
 entity SpecialCasesCheck is
+
 	port(
-		X, Y: in std_logic_vector(31 downto 0);
+		X, Y : in std_logic_vector(31 downto 0);
-		isNaN, isZero: out std_logic
+		IS_NAN, IS_ZERO : out std_logic
 	);
+	
 end SpecialCasesCheck;
 
 
 architecture SpecialCasesCheckArch of SpecialCasesCheck is
+
 	component NaNCheck is
+	
 		port(
-			X, Y: in std_logic_vector(31 downto 0);
+			X, Y : in std_logic_vector(31 downto 0);
-			isNaN: out std_logic
+			IS_NAN : out std_logic
 		);
+		
 	end component;
 
 	component ZeroCheck is
+	
 		port(
-			X, Y: in std_logic_vector(31 downto 0);
+			X, Y : in std_logic_vector(31 downto 0);
-			isZero: out std_logic
+			IS_ZERO : out std_logic
 		);
+		
 	end component;
+	
 begin
+
 	NC: NaNCheck
-		port map (X => X, Y => Y, isNaN => isNaN);
+		port map (X => X, Y => Y, IS_NAN => IS_NAN);
+		
 	ZC: ZeroCheck
-		port map (X => X, Y => Y, isZero => isZero);
+		port map (X => X, Y => Y, IS_ZERO => IS_ZERO);
+		
 end SpecialCasesCheckArch;
 
 

Swap.vhd

@@ -2,25 +2,32 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
 entity Swap is
-	generic(BITCOUNT : integer := 8);
+
+	generic(
+		BITCOUNT : integer := 8
+	);
+	
 	port(
 		X_IN, Y_IN : in std_logic_vector((BITCOUNT-1) downto 0);
 		SW : in std_logic;
 		X_OUT, Y_OUT : out std_logic_vector((BITCOUNT-1) downto 0)
 	);
+	
 end Swap;
 
 architecture SwapArch of Swap is
 
 begin
-	SWAP_PRO: process(X_IN, Y_IN, SW)
-	begin
-		for i in (BITCOUNT-1) downto 0 loop
 
+	SWAP_PROCESS: process(X_IN, Y_IN, SW)
+	
+	begin
+	
+		for i in (BITCOUNT-1) downto 0 loop
 			X_OUT(i) <= (not(SW) and X_IN(i)) or (SW and Y_IN(i));
 			Y_OUT(i) <= (not(SW) and Y_IN(i)) or (SW and X_IN(i));
-		
 		end loop;
+		
 	end process;
 
 end SwapArch;

TwoComplement.vhd

@@ -2,30 +2,53 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
 entity TwoComplement is
-	generic(BITCOUNT : integer := 8);
+
+	generic(
+		BITCOUNT : integer := 8
+	);
+	
 	port(
 		DIFF_EXP_C2 : in std_logic_vector((BITCOUNT-1) downto 0);
-		DIFF_EXP_ABS : out std_logic_vector((BITCOUNT-2) downto 0)
+		DIFF_EXP : out std_logic_vector((BITCOUNT-1) downto 0)
 	);
+	
 end TwoComplement;
 
 architecture TwoComplementArch of TwoComplement is
-	signal S : std_logic;
-	signal M : std_logic_vector((BITCOUNT-2) downto 0);
-begin
-	S <= DIFF_EXP_C2(BITCOUNT-1);
-	M <= DIFF_EXP_C2((BITCOUNT-2) downto 0);
 
-	C2 : process(DIFF_EXP_C2)
+	signal SIGN : std_logic;
+	signal DIFF_EXP_ABS : std_logic_vector((BITCOUNT-2) downto 0);
+	
+begin
+
+	SIGN <= DIFF_EXP_C2(BITCOUNT-1);
+	
+	C2_PROCESS : process(DIFF_EXP_C2, SIGN)
+	
 	begin
+	
 		for i in (BITCOUNT-2) downto 0 loop
-			M(i) <= S xor M(i);
+			DIFF_EXP_ABS(i) <= SIGN xor DIFF_EXP_C2(i);
 		end loop;
+		
 	end process;
 	
-	--sommare 1 a M se S = '1'
+	SUM : process(DIFF_EXP_ABS, SIGN)
 	
-	DIFF_EXP_ABS <= M;
+		variable CARRY : std_logic;
+	
+	begin
+	
+		CARRY := SIGN;
+	
+		for i in 0 to (BITCOUNT-2) loop
+			DIFF_EXP(i) <= DIFF_EXP_ABS(i) xor CARRY;
+			CARRY := DIFF_EXP_ABS(i) and CARRY;
+		end loop;
+		
+		DIFF_EXP(BITCOUNT-1) <= CARRY;
+	
+	end process;
 
 end TwoComplementArch;
 

TwoComplementTest.vhd

@@ -0,0 +1,85 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+ 
+-- Uncomment the following library declaration if using
+-- arithmetic functions with Signed or Unsigned values
+--USE ieee.numeric_std.ALL;
+ 
+ENTITY TwoComplementTest IS
+END TwoComplementTest;
+ 
+ARCHITECTURE behavior OF TwoComplementTest IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT TwoComplement
+    PORT(
+         DIFF_EXP_C2 : IN  std_logic_vector(7 downto 0);
+         DIFF_EXP : OUT  std_logic_vector(7 downto 0)
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := "00000000";
+
+ 	--Outputs
+   signal DIFF_EXP : std_logic_vector(7 downto 0);
+	signal clock : std_logic;
+   -- No clocks detected in port list. Replace clock below with 
+   -- appropriate port name 
+ 
+   constant clock_period : time := 10 ns;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: TwoComplement PORT MAP (
+          DIFF_EXP_C2 => DIFF_EXP_C2,
+          DIFF_EXP => DIFF_EXP
+        );
+
+   -- Clock process definitions
+   clock_process :process
+   begin
+		clock <= '0';
+		wait for clock_period/2;
+		clock <= '1';
+		wait for clock_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin		
+      -- hold reset state for 100 ns.
+      wait for 100 ns;	
+
+      wait for clock_period*10;
+
+      -- insert stimulus here 
+
+      wait;
+   end process;
+	
+	test_process :process
+   begin
+		DIFF_EXP_C2 <= "01001110";
+		wait for clock_period;
+		DIFF_EXP_C2 <= "11111111";
+		wait for clock_period;
+		DIFF_EXP_C2 <= "10000000";
+		wait for clock_period;
+		DIFF_EXP_C2 <= "01111111";
+		wait for clock_period;
+		DIFF_EXP_C2 <= "01100101";
+		wait for clock_period;
+		DIFF_EXP_C2 <= "10011101";
+		wait for clock_period;
+		DIFF_EXP_C2 <= "11100010";
+		wait for clock_period;
+		DIFF_EXP_C2 <= "10010011";
+		wait for clock_period;
+   end process;
+
+END;

TypeCheck.vhd

@@ -2,42 +2,60 @@ library IEEE;
 use IEEE.STD_LOGIC_1164.ALL;
 
 entity TypeCheck is
+
 	port(
-		N: in std_logic_vector(31 downto 0);
+		N : in std_logic_vector(30 downto 0);
-		NaN, INF: out std_logic
+		NAN, INF : out std_logic
 	);
+	
 end TypeCheck;
 
 architecture TypeCheckArch of TypeCheck is
-	signal G_Bus: std_logic_vector(7 downto 0);
+
-	signal T_Bus: std_logic_vector(22 downto 0);
+	signal G_BUS : std_logic_vector(7 downto 0);
-	signal G: std_logic := '1';
+	signal T_BUS : std_logic_vector(22 downto 0);
-	signal T: std_logic := '0';
+	signal G : std_logic := '1';
+	signal T : std_logic := '0';
+	
 begin
-	G_Bus <= N(30 downto 23);
-	T_Bus <= N(22 downto 0);
 
-	G_compute: process (G_Bus)
+	G_BUS <= N(30 downto 23);
-		variable G_tmp: std_logic;
+	T_BUS <= N(22 downto 0);
+	
+	G_compute: process (G_BUS)
+	
+		variable G_TMP : std_logic;
+		
 	begin
-		G_tmp := '1';
+	
-		for i in G_Bus'range loop
+		G_TMP := '1';
-			G_tmp := G_tmp and G_Bus(i);
+		
+		for i in G_BUS'range loop
+			G_TMP := G_TMP and G_BUS(i);
 		end loop;
-		G <= G_tmp;
+		
+		G <= G_TMP;
+		
 	end process;
 	
-	T_compute: process (T_Bus)
+	T_compute: process (T_BUS)
-		variable T_tmp: std_logic;
+	
+		variable T_TMP : std_logic;
+		
 	begin
-		T_tmp := '0';
+	
-		for i in T_Bus'range loop
+		T_TMP := '0';
-			T_tmp := T_tmp or T_Bus(i);
+		
+		for i in T_BUS'range loop
+			T_TMP := T_TMP or T_BUS(i);
 		end loop;
-		T <= T_tmp;
+		
+		T <= T_TMP;
+		
 	end process;
 	
-	NaN <= G and T;
+	NAN <= G and T;
 	INF <= G and (not T);
+	
 end TypeCheckArch;
 

ZeroCheck.vhd

@@ -3,38 +3,50 @@ use IEEE.STD_LOGIC_1164.ALL;
 
 
 entity ZeroCheck is
+
 	port(
-		X, Y: in std_logic_vector(31 downto 0);
+		X, Y : in std_logic_vector(31 downto 0);
-		isZero: out std_logic
+		IS_ZERO : out std_logic
 	);
+	
 end ZeroCheck;
 
 architecture ZeroCheckArch of ZeroCheck is
+
 	component EqualCheck is
-		generic( BITCOUNT: integer := 8 );
+	
-		port(
+		generic(
-			X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
+			BITCOUNT : integer := 8
-			isEqual: out std_logic
 		);
+		
+		port(
+			X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
+			IS_EQUAL : out std_logic
+		);
+		
 	end component;
 
-	signal xSign: std_logic;
+	signal S_SIGN : std_logic;
-	signal ySign: std_logic;
+	signal Y_SIGN : std_logic;
-	signal xAbs: std_logic_vector(30 downto 0);
+	signal X_ABS : std_logic_vector(30 downto 0);
-	signal yAbs: std_logic_vector(30 downto 0);
+	signal Y_ABS : std_logic_vector(30 downto 0);
-	signal isSameAbsValue: std_logic;
+	signal IS_SAME_ABS_VALUE : std_logic;
-	signal isSameSign: std_logic;
+	signal IS_SAME_SIGN : std_logic;
-begin
+	
-	xSign <= X(31);
+begin
-	ySign <= Y(31);
+
-	xAbs  <= X(30 downto 0);
+	S_SIGN <= X(31);
-	yAbs  <= Y(30 downto 0);
+	Y_SIGN <= Y(31);
+	X_ABS  <= X(30 downto 0);
+	Y_ABS  <= Y(30 downto 0);
+
+	IS_SAME_SIGN <= S_SIGN xnor Y_SIGN;
 	
-	isSameSign <= xSign xnor ySign;
 	AbsCheck: EqualCheck
 		generic map ( BITCOUNT => 31 )
-		port map (X => xAbs, Y => yAbs, isEqual => isSameAbsValue);
+		port map (X => X_ABS, Y => Y_ABS, IS_EQUAL => IS_SAME_ABS_VALUE);
+	
+	IS_ZERO <= (not IS_SAME_SIGN) and IS_SAME_ABS_VALUE;
 	
-	isZero <= (not isSameSign) and isSameAbsValue;
 end ZeroCheckArch;
 

equalCheck.vhd

@@ -1,28 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity EqualCheck is
-	generic( BITCOUNT: integer := 8 );
-	port(
-		X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
-		isEqual: out std_logic
-	);
-end EqualCheck;
-
-architecture EqualCheckArch of EqualCheck is
-	signal compVec: std_logic_vector( (BITCOUNT-1) downto 0 );
-begin
-	compVec <= X xor Y;
-	
-	res_compute: process (compVec)
-		variable res_tmp: std_logic;
-	begin
-		res_tmp := '0';
-		for i in compVec'range loop
-			res_tmp := res_tmp or compVec(i);
-		end loop;
-		isEqual <= not res_tmp;
-	end process;
-
-end EqualCheckArch;
-

fuse.log

@@ -1,24 +1,21 @@
-Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AddSubTest_beh.prj work.AddSubTest 
+Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj work.TwoComplementTest 
-ISim P.20131013 (signature 0xfbc00daa)
+ISim P.20160913 (signature 0xfbc00daa)
-Number of CPUs detected in this system: 4
+Number of CPUs detected in this system: 1
-Turning on mult-threading, number of parallel sub-compilation jobs: 8 
+Turning on mult-threading, number of parallel sub-compilation jobs: 0 
 Determining compilation order of HDL files
-Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
+Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplement.vhd" into library work
-Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSub.vhd" into library work
+Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TwoComplementTest.vhd" into library work
-Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSubTest.vhd" into library work
 Starting static elaboration
 Completed static elaboration
-Fuse Memory Usage: 94376 KB
+Fuse Memory Usage: 95308 KB
-Fuse CPU Usage: 1040 ms
+Fuse CPU Usage: 2300 ms
 Compiling package standard
 Compiling package std_logic_1164
-Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
+Compiling architecture twocomplementarch of entity TwoComplement [\TwoComplement(8)\]
-Compiling architecture addsubarch of entity AddSub [\AddSub(8)\]
+Compiling architecture behavior of entity twocomplementtest
-Compiling architecture behavior of entity addsubtest
 Time Resolution for simulation is 1ps.
-Waiting for 1 sub-compilation(s) to finish...
+Compiled 5 VHDL Units
-Compiled 7 VHDL Units
+Built simulation executable /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe
-Built simulation executable /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe
+Fuse Memory Usage: 103960 KB
-Fuse Memory Usage: 658004 KB
+Fuse CPU Usage: 2400 ms
-Fuse CPU Usage: 1060 ms
+GCC CPU Usage: 1480 ms
-GCC CPU Usage: 210 ms

fuseRelaunch.cmd

@@ -1 +1 @@
--intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/AddSubTest_beh.prj" "work.AddSubTest" 
+-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/TwoComplementTest_beh.prj" "work.TwoComplementTest" 

isim.log

@@ -1,10 +1,12 @@
 ISim log file
-Running: /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/Luca/ISE/IEEE754Adder/AddSubTest_isim_beh.wdb 
+Running: /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/TwoComplementTest_isim_beh.wdb 
-ISim P.20131013 (signature 0xfbc00daa)
+ISim P.20160913 (signature 0xfbc00daa)
-WARNING: A WEBPACK license was found.
+----------------------------------------------------------------------
-WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
+WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
-WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
+
-This is a Lite version of ISim.
+
+----------------------------------------------------------------------
+This is a Full version of ISim.
 Time resolution is 1 ps
 # onerror resume
 # wave add /