62 lines
881 B
VHDL
62 lines
881 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity TypeCheck is
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port(
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N : in std_logic_vector(30 downto 0);
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NAN, INF : out std_logic
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);
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end TypeCheck;
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architecture TypeCheckArch of TypeCheck is
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signal G_BUS : std_logic_vector(7 downto 0);
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signal T_BUS : std_logic_vector(22 downto 0);
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signal G : std_logic := '1';
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signal T : std_logic := '0';
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begin
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G_BUS <= N(30 downto 23);
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T_BUS <= N(22 downto 0);
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G_compute: process (G_BUS)
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variable G_TMP : std_logic;
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begin
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G_TMP := '1';
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for i in G_BUS'range loop
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G_TMP := G_TMP and G_BUS(i);
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end loop;
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G <= G_TMP;
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end process;
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T_compute: process (T_BUS)
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variable T_TMP : std_logic;
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begin
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T_TMP := '0';
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for i in T_BUS'range loop
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T_TMP := T_TMP or T_BUS(i);
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end loop;
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T <= T_TMP;
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end process;
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NAN <= G and T;
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INF <= G and (not T);
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end TypeCheckArch;
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