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Merge branch 'master' of github.com:optimize-fast/IEEE754Adder

Browse Source 
Conflicts:
	IEEE754Adder.xise
	fuse.log
	fuseRelaunch.cmd
	isim.log
	isim/isim_usage_statistics.html
	isim/precompiled.exe.sim/ieee/p_2592010699.didat
This commit is contained in:
Luca Cuzzocrea
2019-08-28 22:03:08 +02:00
parent a91e1252d0 8b08af2782
commit b6c1d7abe2
130 changed files with 4284 additions and 57 deletions
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34
Comparator.vhd Normal file
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@@ -0,0 +1,34 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Comparator is
generic( BITCOUNT: integer := 8 );
port(
xT, yT: in std_logic_vector((BITCOUNT-1) downto 0);
needSwap: out std_logic
);
end Comparator;
architecture ComparatorArch of Comparator is
signal xGTy: std_logic_vector((BITCOUNT-1) downto 0);
signal yGTx: std_logic_vector((BITCOUNT-1) downto 0);
begin
xGTy <= xT and (not yT);
yGTx <= (not xT) and yT;
needSwap_compute: process (xGTy, yGTx)
variable SW: std_logic;
variable K: std_logic;
begin
SW := '0';
K := '1';
for i in (BITCOUNT-1) downto 0 loop
SW := SW or ((not(xGTy(i)) and yGTx(i)) and K);
K := K and (not(xGTy(i) and not(yGTx(i))));
end loop;
needSwap <= SW;
end process;
end ComparatorArch;

65
ComparatorTest.vhd Normal file
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@@ -0,0 +1,65 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY ComparatorTest IS
END ComparatorTest;
ARCHITECTURE behavior OF ComparatorTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Comparator
PORT(
xT : IN std_logic_vector(7 downto 0);
yT : IN std_logic_vector(7 downto 0);
needSwap : OUT std_logic
);
END COMPONENT;
--Inputs
signal xT : std_logic_vector(7 downto 0) := "11111111";
signal yT : std_logic_vector(7 downto 0) := "11111111";
--Outputs
signal needSwap : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
signal clock: std_logic;
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Comparator PORT MAP (
xT => xT,
yT => yT,
needSwap => needSwap
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
END;

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18
FullAdder.vhd Normal file
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@@ -0,0 +1,18 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity FullAdder is
port(
X, Y, C_IN : in std_logic;
S, C_OUT : out std_logic
);
end FullAdder;
architecture FullAdderArch of FullAdder is
begin
S <= C_IN xor X xor Y;
C_OUT <= (C_IN and X) or (C_IN and Y) or (X and Y);
end FullAdderArch;

97
FullAdderTest.vhd Normal file
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@@ -0,0 +1,97 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY FullAdderTest IS
END FullAdderTest;
ARCHITECTURE behavior OF FullAdderTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT FullAdder
PORT(
X : IN std_logic;
Y : IN std_logic;
C_IN : IN std_logic;
S : OUT std_logic;
C_OUT : OUT std_logic
);
END COMPONENT;
--Inputs
signal X : std_logic := '0';
signal Y : std_logic := '0';
signal C_IN : std_logic := '0';
--Outputs
signal S : std_logic;
signal C_OUT : std_logic;
signal clock : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: FullAdder PORT MAP (
X => X,
Y => Y,
C_IN => C_IN,
S => S,
C_OUT => C_OUT
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
test_process :process
begin
X <= '0';
Y <= '0';
C_IN <= '0';
wait for clock_period;
X <= '1';
Y <= '0';
C_IN <= '0';
wait for clock_period;
X <= '0';
Y <= '1';
C_IN <= '0';
wait for clock_period;
X <= '0';
Y <= '0';
C_IN <= '1';
wait for clock_period;
X <= '1';
Y <= '1';
C_IN <= '0';
wait for clock_period;
X <= '1';
Y <= '0';
C_IN <= '1';
wait for clock_period;
X <= '0';
Y <= '1';
C_IN <= '1';
wait for clock_period;
X <= '1';
Y <= '1';
C_IN <= '1';
wait for clock_period;
end process;
END;

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FullAdderTest_isim_beh.exe Normal file
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FullAdderTest_isim_beh.wdb Normal file
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55
IEEE754Adder.xise
View File

@@ -41,22 +41,47 @@
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
</file>
<file xil_pn:name="SpecialCasesCheck.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="SwapTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="160"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="160"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="FullAdder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AdderTest.vhd" xil_pn:type="FILE_VHDL">
<file xil_pn:name="FullAdderTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="195"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="195"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="195"/>
</file>
</files>
@@ -315,8 +340,8 @@
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/SpecialCasesTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.SpecialCasesTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/FullAdderTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.FullAdderTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -335,7 +360,7 @@
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.SpecialCasesTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.FullAdderTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -391,7 +416,7 @@
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AdderTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|FullAdderTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
@@ -406,9 +431,7 @@
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/Adder" xil_pn:name="SpecialCasesCheck.ucf"/>
</bindings>
<bindings/>
<libraries/>

492
IEEE754Adder.xise~ Normal file
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@@ -0,0 +1,492 @@
<?xml version="1.0" encoding="UTF-8" standalone="no" ?>
<project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
<header>
<!-- ISE source project file created by Project Navigator. -->
<!-- -->
<!-- This file contains project source information including a list of -->
<!-- project source files, project and process properties. This file, -->
<!-- along with the project source files, is sufficient to open and -->
<!-- implement in ISE Project Navigator. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
</header>
<version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
<files>
<file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<<<<<<< HEAD
<association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file>
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file>
<file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file>
<file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
=======
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
</file>
<file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
</file>
<<<<<<< HEAD
<file xil_pn:name="SpecialCasesCheck.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AdderTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
=======
<file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="128"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="128"/>
</file>
<file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="SwapTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="160"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="160"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="160"/>
</file>
<file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="FullAdder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file>
<file xil_pn:name="FullAdderTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="195"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="195"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="195"/>
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
</file>
</files>
<properties>
<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unexpanded Blocks" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched LOC Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Allow Unmatched Timing Group Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Analysis Effort Level" xil_pn:value="Standard" xil_pn:valueState="default"/>
<property xil_pn:name="Asynchronous To Synchronous" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Auto Implementation Top" xil_pn:value="false" xil_pn:valueState="non-default"/>
<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Bus Delimiter" xil_pn:value="&lt;>" xil_pn:valueState="default"/>
<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile UNISIM (Functional) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile XilinxCoreLib (CORE Generator) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Compile for HDL Debugging" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
<property xil_pn:name="Device" xil_pn:value="xa6slx4" xil_pn:valueState="default"/>
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="default"/>
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Implementation Top" xil_pn:value="Architecture|FullAdder|FullAdderArch" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top File" xil_pn:value="FullAdder.vhd" xil_pn:valueState="non-default"/>
<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/FullAdder" xil_pn:valueState="non-default"/>
<property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
<property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
<property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="FullAdder" xil_pn:valueState="default"/>
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="csg225" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
<property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="FullAdder_map.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="FullAdder_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="FullAdder_synthesis.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="FullAdder_translate.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
<property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Entity to" xil_pn:value="FullAdder" xil_pn:valueState="default"/>
<property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Module Instance Name" xil_pn:value="/FullAdderTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.FullAdderTest" xil_pn:valueState="non-default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
<property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
<property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.FullAdderTest" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Target UCF File Name" xil_pn:value="SpecialCasesCheck.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6_runtime.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<<<<<<< HEAD
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AdderTest|behavior" xil_pn:valueState="non-default"/>
=======
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|FullAdderTest|behavior" xil_pn:valueState="non-default"/>
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-08-24T16:50:37" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="444E2DA6F875B400D5DCC2E6514F4196" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties>
<bindings>
<binding xil_pn:location="/Adder" xil_pn:name="SpecialCasesCheck.ucf"/>
</bindings>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

18
OperationCheck.vhd Normal file
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@@ -0,0 +1,18 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity OperationCheck is
port(
X_SIGN, Y_SIGN : in std_logic;
OP, RES_SIGN : out std_logic
);
end OperationCheck;
architecture OperationCheckArch of OperationCheck is
begin
OP <= X_SIGN xor Y_SIGN;
RES_SIGN <= X_SIGN;
end OperationCheckArch;

42
PrepareForShift.vhd Normal file
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@@ -0,0 +1,42 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity PrepareForShift is
port(
X, Y: in std_logic_vector(31 downto 0);
DIFF_EXP: out std_logic_vector(8 downto 0);
SW: out std_logic
);
end PrepareForShift;
architecture PrepareForShiftArch of PrepareForShift is
signal LT: std_logic;
signal EQ: std_logic;
component Comparator is
generic( BITCOUNT: integer := 8 );
port(
xT, yT: in std_logic_vector((BITCOUNT-1) downto 0);
needSwap: out std_logic
);
end component;
begin
C: Comparator
port map (xT => X(22 downto 0), yT => Y(22 downto 0), needSwap => LT);
--istaziare sommatore la cui uscita va mappata in X(31 downto 23), Y(31 downto 23), DIFF_EXP
EQ <= '0';
O: process (DIFF_EXP)
begin
for i in 8 downto 0 loop
EQ <= EQ or DIFF_EXP(i);
end loop;
end process;
SW <= DIFF_EXP(8) or (EQ and LT);
end PrepareForShiftArch;

BIN
SpecialCasesTest_isim_beh.wdb
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27
Swap.vhd Normal file
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@@ -0,0 +1,27 @@
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Swap is
generic(BITCOUNT : integer := 8);
port(
X_IN, Y_IN : in std_logic_vector((BITCOUNT-1) downto 0);
SW : in std_logic;
X_OUT, Y_OUT : out std_logic_vector((BITCOUNT-1) downto 0)
);
end Swap;
architecture SwapArch of Swap is
begin
SWAP_PRO: process(X_IN, Y_IN, SW)
begin
for i in (BITCOUNT-1) downto 0 loop
X_OUT(i) <= (not(SW) and X_IN(i)) or (SW and Y_IN(i));
Y_OUT(i) <= (not(SW) and Y_IN(i)) or (SW and X_IN(i));
end loop;
end process;
end SwapArch;

74
SwapTest.vhd Normal file
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@@ -0,0 +1,74 @@
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY SwapTest IS
END SwapTest;
ARCHITECTURE behavior OF SwapTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Swap
PORT(
X_IN : IN std_logic_vector(7 downto 0);
Y_IN : IN std_logic_vector(7 downto 0);
SW : IN std_logic;
X_OUT : OUT std_logic_vector(7 downto 0);
Y_OUT : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--Inputs
signal X_IN : std_logic_vector(7 downto 0) := "01010101";
signal Y_IN : std_logic_vector(7 downto 0) := "10101010";
signal SW : std_logic := '1';
--Outputs
signal X_OUT : std_logic_vector(7 downto 0);
signal Y_OUT : std_logic_vector(7 downto 0);
signal clock : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Swap PORT MAP (
X_IN => X_IN,
Y_IN => Y_IN,
SW => SW,
X_OUT => X_OUT,
Y_OUT => Y_OUT
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
-- Stimulus process
stim_proc: process
begin
-- hold reset state for 100 ns.
wait for 100 ns;
wait for clock_period*10;
-- insert stimulus here
wait;
end process;
END;

BIN
SwapTest_isim_beh.exe Normal file
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SwapTest_isim_beh.wdb Normal file
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31
TwoComplement.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TwoComplement is
generic(BITCOUNT : integer := 8);
port(
DIFF_EXP_C2 : in std_logic_vector((BITCOUNT-1) downto 0);
DIFF_EXP_ABS : out std_logic_vector((BITCOUNT-2) downto 0);
);
end TwoComplement;
architecture TwoComplementArch of TwoComplement is
signal S : std_logic;
signal M : std_logic_vector((BITCOUNT-2) downto 0);
begin
S <= DIFF_EXP_C2(BITCOUNT-1);
M <= DIFF_EXP_C2((BITCOUNT-2) downto 0);
C2 : process(DIFF_EXP_C2)
begin
for i in (BITCOUNT-2) downto 0 loop
M(i) <= S xor M(i);
end loop;
end process;
--sommare 1 a M se S = '1'
DIFF_EXP_ABS <= M;
end TwoComplementArch;

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TypeCheck_isim_beh.exe Normal file
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2
equalCheck.vhd
View File

@@ -21,7 +21,7 @@ begin
for i in compVec'range loop
res_tmp := res_tmp or compVec(i);
end loop;
isEqual <= res_tmp;
isEqual <= not res_tmp;
end process;
end EqualCheckArch;

29
fuse.log
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@@ -1,22 +1,21 @@
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj work.AdderTest
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest"
ISim P.20160913 (signature 0xfbc00daa)
Number of CPUs detected in this system: 1
Turning on mult-threading, number of parallel sub-compilation jobs: 0
Determining compilation order of HDL files
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AdderTest.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdder.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdderTest.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 94252 KB
Fuse CPU Usage: 950 ms
Fuse Memory Usage: 95308 KB
Fuse CPU Usage: 2530 ms
Compiling package standard
Compiling package std_logic_1164
Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
Compiling architecture behavior of entity addertest
Compiling architecture fulladderarch of entity FullAdder [fulladder_default]
Compiling architecture behavior of entity fulladdertest
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 5 VHDL Units
Built simulation executable /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe
Fuse Memory Usage: 657936 KB
Fuse CPU Usage: 980 ms
GCC CPU Usage: 140 ms
Built simulation executable /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe
Fuse Memory Usage: 103940 KB
Fuse CPU Usage: 2640 ms
GCC CPU Usage: 440 ms

46
fuse.log~ Normal file
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<<<<<<< HEAD
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj work.AdderTest
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AdderTest.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 94252 KB
Fuse CPU Usage: 950 ms
Compiling package standard
Compiling package std_logic_1164
Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
Compiling architecture behavior of entity addertest
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 5 VHDL Units
Built simulation executable /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe
Fuse Memory Usage: 657936 KB
Fuse CPU Usage: 980 ms
GCC CPU Usage: 140 ms
=======
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest"
ISim P.20160913 (signature 0xfbc00daa)
Number of CPUs detected in this system: 1
Turning on mult-threading, number of parallel sub-compilation jobs: 0
Determining compilation order of HDL files
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdder.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdderTest.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 95308 KB
Fuse CPU Usage: 2530 ms
Compiling package standard
Compiling package std_logic_1164
Compiling architecture fulladderarch of entity FullAdder [fulladder_default]
Compiling architecture behavior of entity fulladdertest
Time Resolution for simulation is 1ps.
Compiled 5 VHDL Units
Built simulation executable /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe
Fuse Memory Usage: 103940 KB
Fuse CPU Usage: 2640 ms
GCC CPU Usage: 440 ms
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d

2
fuseRelaunch.cmd
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@@ -1 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj" "work.AdderTest"
-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest"

5
fuseRelaunch.cmd~ Normal file
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@@ -0,0 +1,5 @@
<<<<<<< HEAD
-intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj" "work.AdderTest"
=======
-intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest"
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d

24
isim.log
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@@ -1,14 +1,26 @@
ISim log file
Running: /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.wdb
ISim P.20131013 (signature 0xfbc00daa)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
Running: /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.wdb
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# exit 0

35
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ISim log file
<<<<<<< HEAD
Running: /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.wdb
ISim P.20131013 (signature 0xfbc00daa)
WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.
WARNING: ISim will run in Lite mode. Please refer to the ISim documentation for more information on the differences between the Lite and the Full version.
This is a Lite version of ISim.
=======
Running: /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.wdb
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
Time resolution is 1 ps
# onerror resume
# wave add /
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
ISim P.20160913 (signature 0xfbc00daa)
----------------------------------------------------------------------
WARNING:Security:42 - Your software subscription period has lapsed. Your current version of Xilinx tools will continue to function, but you no longer qualify for Xilinx software updates or new releases.
----------------------------------------------------------------------
This is a Full version of ISim.
# run 1000 ns
Simulator is doing circuit initialization process.
Finished circuit initialization process.
# exit 0

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Command line:
ComparatorTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 40809
Tue Aug 27 09:47:36 2019
Elaboration Time: 0.12 sec
Current Memory Usage: 198.607 Meg
Total Signals : 9
Total Nets : 34
Total Signal Drivers : 4
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 5
Total Traceable Variables : 10
Total Scalar Nets and Variables : 396
Total Simulation Time: 0.13 sec
Current Memory Usage: 276.206 Meg
Tue Aug 27 09:47:41 2019

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_0883098610_0495709306_init();
work_a_1038528572_2372691052_init();
xsi_register_tops("work_a_1038528572_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/Comparator.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439989832805790689_503743352(char *, char *, char *, char *, char *, char *);
char *ieee_p_2592010699_sub_207919886985903570_503743352(char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_0883098610_0495709306_p_0(char *t0)
{
char t1[16];
char t4[16];
char *t2;
char *t3;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(17, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 6144U);
t5 = (t0 + 1192U);
t6 = *((char **)t5);
t5 = (t0 + 6160U);
t7 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t4, t6, t5);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t3, t2, t7, t4);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4112);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4000);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_0883098610_0495709306_p_1(char *t0)
{
char t1[16];
char t2[16];
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t3 = (t0 + 1032U);
t4 = *((char **)t3);
t3 = (t0 + 6144U);
t5 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t2, t4, t3);
t6 = (t0 + 1192U);
t7 = *((char **)t6);
t6 = (t0 + 6160U);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t5, t2, t7, t6);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4176);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4016);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_0883098610_0495709306_p_2(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
int t5;
char *t6;
char *t7;
unsigned char t8;
char *t9;
int t10;
int t11;
unsigned int t12;
unsigned int t13;
unsigned int t14;
char *t15;
unsigned char t16;
unsigned char t17;
char *t18;
char *t19;
int t20;
int t21;
unsigned int t22;
unsigned int t23;
unsigned int t24;
char *t25;
unsigned char t26;
unsigned char t27;
char *t28;
char *t29;
unsigned char t30;
unsigned char t31;
unsigned char t32;
char *t33;
LAB0: xsi_set_current_line(24, ng0);
t1 = (t0 + 2088U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(25, ng0);
t1 = (t0 + 2208U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(26, ng0);
t3 = (8 - 1);
t1 = (t0 + 6254);
*((int *)t1) = t3;
t2 = (t0 + 6258);
*((int *)t2) = 0;
t4 = t3;
t5 = 0;
LAB2: if (t4 >= t5)
goto LAB3;
LAB5: xsi_set_current_line(30, ng0);
t1 = (t0 + 2088U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 4240);
t6 = (t1 + 56U);
t7 = *((char **)t6);
t9 = (t7 + 56U);
t15 = *((char **)t9);
*((unsigned char *)t15) = t8;
xsi_driver_first_trans_fast_port(t1);
t1 = (t0 + 4032);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(27, ng0);
t6 = (t0 + 2088U);
t7 = *((char **)t6);
t8 = *((unsigned char *)t7);
t6 = (t0 + 1512U);
t9 = *((char **)t6);
t6 = (t0 + 6254);
t10 = *((int *)t6);
t11 = (t10 - 7);
t12 = (t11 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t6));
t13 = (1U * t12);
t14 = (0 + t13);
t15 = (t9 + t14);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16);
t18 = (t0 + 1672U);
t19 = *((char **)t18);
t18 = (t0 + 6254);
t20 = *((int *)t18);
t21 = (t20 - 7);
t22 = (t21 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t18));
t23 = (1U * t22);
t24 = (0 + t23);
t25 = (t19 + t24);
t26 = *((unsigned char *)t25);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t17, t26);
t28 = (t0 + 2208U);
t29 = *((char **)t28);
t30 = *((unsigned char *)t29);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t27, t30);
t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t8, t31);
t28 = (t0 + 2088U);
t33 = *((char **)t28);
t28 = (t33 + 0);
*((unsigned char *)t28) = t32;
xsi_set_current_line(28, ng0);
t1 = (t0 + 2208U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 1512U);
t6 = *((char **)t1);
t1 = (t0 + 6254);
t3 = *((int *)t1);
t10 = (t3 - 7);
t12 = (t10 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t1));
t13 = (1U * t12);
t14 = (0 + t13);
t7 = (t6 + t14);
t16 = *((unsigned char *)t7);
t9 = (t0 + 1672U);
t15 = *((char **)t9);
t9 = (t0 + 6254);
t11 = *((int *)t9);
t20 = (t11 - 7);
t22 = (t20 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t9));
t23 = (1U * t22);
t24 = (0 + t23);
t18 = (t15 + t24);
t17 = *((unsigned char *)t18);
t26 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t17);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t16, t26);
t30 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t27);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t30);
t19 = (t0 + 2208U);
t25 = *((char **)t19);
t19 = (t25 + 0);
*((unsigned char *)t19) = t31;
LAB4: t1 = (t0 + 6254);
t4 = *((int *)t1);
t2 = (t0 + 6258);
t5 = *((int *)t2);
if (t4 == t5)
goto LAB5;
LAB6: t3 = (t4 + -1);
t4 = t3;
t6 = (t0 + 6254);
*((int *)t6) = t4;
goto LAB2;
}
extern void work_a_0883098610_0495709306_init()
{
static char *pe[] = {(void *)work_a_0883098610_0495709306_p_0,(void *)work_a_0883098610_0495709306_p_1,(void *)work_a_0883098610_0495709306_p_2};
xsi_register_didat("work_a_0883098610_0495709306", "isim/ComparatorTest_isim_beh.exe.sim/work/a_0883098610_0495709306.didat");
xsi_register_executes(pe);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/ComparatorTest.vhd";
static void work_a_1038528572_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 2784U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(45, ng0);
t2 = (t0 + 3416);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(46, ng0);
t2 = (t0 + 1808U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2592);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(47, ng0);
t2 = (t0 + 3416);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(48, ng0);
t2 = (t0 + 1808U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2592);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_1038528572_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
LAB0: t1 = (t0 + 3032U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(56, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 2840);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(58, ng0);
t2 = (t0 + 1808U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 2840);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(62, ng0);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: goto LAB2;
LAB13: goto LAB12;
LAB15: goto LAB13;
}
extern void work_a_1038528572_2372691052_init()
{
static char *pe[] = {(void *)work_a_1038528572_2372691052_p_0,(void *)work_a_1038528572_2372691052_p_1};
xsi_register_didat("work_a_1038528572_2372691052", "isim/ComparatorTest_isim_beh.exe.sim/work/a_1038528572_2372691052.didat");
xsi_register_executes(pe);
}

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Command line:
FullAdderTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 51967
Tue Aug 27 15:05:31 2019
Elaboration Time: 0.11 sec
Current Memory Usage: 198.607 Meg
Total Signals : 11
Total Nets : 6
Total Signal Drivers : 6
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 4
Total Traceable Variables : 9
Total Scalar Nets and Variables : 367
Total Simulation Time: 0.15 sec
Current Memory Usage: 276.206 Meg
Tue Aug 27 15:08:11 2019

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_1130988942_2801528920_init();
work_a_2258021406_2372691052_init();
xsi_register_tops("work_a_2258021406_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/FullAdder.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768497506413324_503743352(char *, unsigned char , unsigned char );
static void work_a_1130988942_2801528920_p_0(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
unsigned char t8;
unsigned char t9;
char *t10;
char *t11;
char *t12;
char *t13;
char *t14;
LAB0: xsi_set_current_line(14, ng0);
LAB3: t1 = (t0 + 1352U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1032U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768497506413324_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 1192U);
t7 = *((char **)t1);
t8 = *((unsigned char *)t7);
t9 = ieee_p_2592010699_sub_3488768497506413324_503743352(IEEE_P_2592010699, t6, t8);
t1 = (t0 + 3488);
t10 = (t1 + 56U);
t11 = *((char **)t10);
t12 = (t11 + 56U);
t13 = *((char **)t12);
*((unsigned char *)t13) = t9;
xsi_driver_first_trans_fast_port(t1);
LAB2: t14 = (t0 + 3392);
*((int *)t14) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1130988942_2801528920_p_1(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
unsigned char t8;
char *t9;
unsigned char t10;
unsigned char t11;
unsigned char t12;
char *t13;
unsigned char t14;
char *t15;
unsigned char t16;
unsigned char t17;
unsigned char t18;
char *t19;
char *t20;
char *t21;
char *t22;
char *t23;
LAB0: xsi_set_current_line(15, ng0);
LAB3: t1 = (t0 + 1352U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1032U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 1352U);
t7 = *((char **)t1);
t8 = *((unsigned char *)t7);
t1 = (t0 + 1192U);
t9 = *((char **)t1);
t10 = *((unsigned char *)t9);
t11 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t10);
t12 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t6, t11);
t1 = (t0 + 1032U);
t13 = *((char **)t1);
t14 = *((unsigned char *)t13);
t1 = (t0 + 1192U);
t15 = *((char **)t1);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t14, t16);
t18 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t12, t17);
t1 = (t0 + 3552);
t19 = (t1 + 56U);
t20 = *((char **)t19);
t21 = (t20 + 56U);
t22 = *((char **)t21);
*((unsigned char *)t22) = t18;
xsi_driver_first_trans_fast_port(t1);
LAB2: t23 = (t0 + 3408);
*((int *)t23) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_1130988942_2801528920_init()
{
static char *pe[] = {(void *)work_a_1130988942_2801528920_p_0,(void *)work_a_1130988942_2801528920_p_1};
xsi_register_didat("work_a_1130988942_2801528920", "isim/FullAdderTest_isim_beh.exe.sim/work/a_1130988942_2801528920.didat");
xsi_register_executes(pe);
}

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isim/FullAdderTest_isim_beh.exe.sim/work/a_2258021406_2372691052.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/FullAdderTest.vhd";
static void work_a_2258021406_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 3104U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(54, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(55, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(56, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(57, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_2258021406_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
LAB0: t1 = (t0 + 3352U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(63, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(64, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(65, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(66, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(67, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(68, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(69, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(70, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(71, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(72, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(73, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(74, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: xsi_set_current_line(75, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(76, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(77, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(78, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB18: *((char **)t1) = &&LAB19;
goto LAB1;
LAB13: goto LAB12;
LAB15: goto LAB13;
LAB16: xsi_set_current_line(79, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(80, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(81, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(82, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB22: *((char **)t1) = &&LAB23;
goto LAB1;
LAB17: goto LAB16;
LAB19: goto LAB17;
LAB20: xsi_set_current_line(83, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(84, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(85, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(86, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB26: *((char **)t1) = &&LAB27;
goto LAB1;
LAB21: goto LAB20;
LAB23: goto LAB21;
LAB24: xsi_set_current_line(87, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(88, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(89, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(90, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB30: *((char **)t1) = &&LAB31;
goto LAB1;
LAB25: goto LAB24;
LAB27: goto LAB25;
LAB28: xsi_set_current_line(91, ng0);
t2 = (t0 + 3800);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(92, ng0);
t2 = (t0 + 3864);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(93, ng0);
t2 = (t0 + 3928);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(94, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t2 = (t0 + 3160);
xsi_process_wait(t2, t7);
LAB34: *((char **)t1) = &&LAB35;
goto LAB1;
LAB29: goto LAB28;
LAB31: goto LAB29;
LAB32: goto LAB2;
LAB33: goto LAB32;
LAB35: goto LAB33;
}
extern void work_a_2258021406_2372691052_init()
{
static char *pe[] = {(void *)work_a_2258021406_2372691052_p_0,(void *)work_a_2258021406_2372691052_p_1};
xsi_register_didat("work_a_2258021406_2372691052", "isim/FullAdderTest_isim_beh.exe.sim/work/a_2258021406_2372691052.didat");
xsi_register_executes(pe);
}

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Command line:
SwapTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 45337
Tue Aug 27 12:56:25 2019
Elaboration Time: 0.09 sec
Current Memory Usage: 198.603 Meg
Total Signals : 11
Total Nets : 34
Total Signal Drivers : 3
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 3
Total Traceable Variables : 10
Total Scalar Nets and Variables : 396
Total Simulation Time: 0.11 sec
Current Memory Usage: 276.201 Meg
Tue Aug 27 12:56:46 2019

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isim/SwapTest_isim_beh.exe.sim/work/SwapTest_isim_beh.exe_main.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_2579272516_1004118533_init();
work_a_0464846403_2372691052_init();
xsi_register_tops("work_a_0464846403_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/SwapTest.vhd";
static void work_a_0464846403_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 3104U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(54, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(55, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(56, ng0);
t2 = (t0 + 3736);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(57, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_0464846403_2372691052_p_1(char *t0)
{
char *t1;
char *t2;
int64 t3;
char *t4;
int64 t5;
LAB0: t1 = (t0 + 3352U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(65, ng0);
t3 = (100 * 1000LL);
t2 = (t0 + 3160);
xsi_process_wait(t2, t3);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(67, ng0);
t2 = (t0 + 2128U);
t4 = *((char **)t2);
t3 = *((int64 *)t4);
t5 = (t3 * 10);
t2 = (t0 + 3160);
xsi_process_wait(t2, t5);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: xsi_set_current_line(71, ng0);
LAB14: *((char **)t1) = &&LAB15;
goto LAB1;
LAB9: goto LAB8;
LAB11: goto LAB9;
LAB12: goto LAB2;
LAB13: goto LAB12;
LAB15: goto LAB13;
}
extern void work_a_0464846403_2372691052_init()
{
static char *pe[] = {(void *)work_a_0464846403_2372691052_p_0,(void *)work_a_0464846403_2372691052_p_1};
xsi_register_didat("work_a_0464846403_2372691052", "isim/SwapTest_isim_beh.exe.sim/work/a_0464846403_2372691052.didat");
xsi_register_executes(pe);
}

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isim/SwapTest_isim_beh.exe.sim/work/a_2579272516_1004118533.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/Swap.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_2579272516_1004118533_p_0(char *t0)
{
int t1;
char *t2;
char *t3;
int t4;
int t5;
char *t6;
char *t7;
unsigned char t8;
unsigned char t9;
char *t10;
int t11;
int t12;
unsigned int t13;
unsigned int t14;
unsigned int t15;
char *t16;
unsigned char t17;
unsigned char t18;
char *t19;
char *t20;
unsigned char t21;
char *t22;
int t23;
int t24;
unsigned int t25;
unsigned int t26;
unsigned int t27;
char *t28;
unsigned char t29;
unsigned char t30;
unsigned char t31;
char *t32;
int t33;
int t34;
unsigned int t35;
unsigned int t36;
unsigned int t37;
char *t38;
char *t39;
char *t40;
char *t41;
char *t42;
LAB0: xsi_set_current_line(18, ng0);
t1 = (8 - 1);
t2 = (t0 + 5109);
*((int *)t2) = t1;
t3 = (t0 + 5113);
*((int *)t3) = 0;
t4 = t1;
t5 = 0;
LAB2: if (t4 >= t5)
goto LAB3;
LAB5: t2 = (t0 + 3264);
*((int *)t2) = 1;
LAB1: return;
LAB3: xsi_set_current_line(20, ng0);
t6 = (t0 + 1352U);
t7 = *((char **)t6);
t8 = *((unsigned char *)t7);
t9 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t8);
t6 = (t0 + 1032U);
t10 = *((char **)t6);
t6 = (t0 + 5109);
t11 = *((int *)t6);
t12 = (t11 - 7);
t13 = (t12 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t6));
t14 = (1U * t13);
t15 = (0 + t14);
t16 = (t10 + t15);
t17 = *((unsigned char *)t16);
t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t9, t17);
t19 = (t0 + 1352U);
t20 = *((char **)t19);
t21 = *((unsigned char *)t20);
t19 = (t0 + 1192U);
t22 = *((char **)t19);
t19 = (t0 + 5109);
t23 = *((int *)t19);
t24 = (t23 - 7);
t25 = (t24 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t19));
t26 = (1U * t25);
t27 = (0 + t26);
t28 = (t22 + t27);
t29 = *((unsigned char *)t28);
t30 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t21, t29);
t31 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t18, t30);
t32 = (t0 + 5109);
t33 = *((int *)t32);
t34 = (t33 - 7);
t35 = (t34 * -1);
t36 = (1 * t35);
t37 = (0U + t36);
t38 = (t0 + 3344);
t39 = (t38 + 56U);
t40 = *((char **)t39);
t41 = (t40 + 56U);
t42 = *((char **)t41);
*((unsigned char *)t42) = t31;
xsi_driver_first_trans_delta(t38, t37, 1, 0LL);
xsi_set_current_line(21, ng0);
t2 = (t0 + 1352U);
t3 = *((char **)t2);
t8 = *((unsigned char *)t3);
t9 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t8);
t2 = (t0 + 1192U);
t6 = *((char **)t2);
t2 = (t0 + 5109);
t1 = *((int *)t2);
t11 = (t1 - 7);
t13 = (t11 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t2));
t14 = (1U * t13);
t15 = (0 + t14);
t7 = (t6 + t15);
t17 = *((unsigned char *)t7);
t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t9, t17);
t10 = (t0 + 1352U);
t16 = *((char **)t10);
t21 = *((unsigned char *)t16);
t10 = (t0 + 1032U);
t19 = *((char **)t10);
t10 = (t0 + 5109);
t12 = *((int *)t10);
t23 = (t12 - 7);
t25 = (t23 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t10));
t26 = (1U * t25);
t27 = (0 + t26);
t20 = (t19 + t27);
t29 = *((unsigned char *)t20);
t30 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t21, t29);
t31 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t18, t30);
t22 = (t0 + 5109);
t24 = *((int *)t22);
t33 = (t24 - 7);
t35 = (t33 * -1);
t36 = (1 * t35);
t37 = (0U + t36);
t28 = (t0 + 3408);
t32 = (t28 + 56U);
t38 = *((char **)t32);
t39 = (t38 + 56U);
t40 = *((char **)t39);
*((unsigned char *)t40) = t31;
xsi_driver_first_trans_delta(t28, t37, 1, 0LL);
LAB4: t2 = (t0 + 5109);
t4 = *((int *)t2);
t3 = (t0 + 5113);
t5 = *((int *)t3);
if (t4 == t5)
goto LAB5;
LAB6: t1 = (t4 + -1);
t4 = t1;
t6 = (t0 + 5109);
*((int *)t6) = t4;
goto LAB2;
}
extern void work_a_2579272516_1004118533_init()
{
static char *pe[] = {(void *)work_a_2579272516_1004118533_p_0};
xsi_register_didat("work_a_2579272516_1004118533", "isim/SwapTest_isim_beh.exe.sim/work/a_2579272516_1004118533.didat");
xsi_register_executes(pe);
}

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isim/TypeCheck_isim_beh.exe.sim/isimkernel.log Normal file
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Command line:
TypeCheck_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 60560
Tue Aug 27 12:53:49 2019
Elaboration Time: 0.14 sec
Current Memory Usage: 198.603 Meg
Total Signals : 7
Total Nets : 67
Total Signal Drivers : 6
Total Blocks : 2
Total Primitive Blocks : 2
Total Processes : 6
Total Traceable Variables : 8
Total Scalar Nets and Variables : 427
Total Simulation Time: 0.15 sec
Current Memory Usage: 276.201 Meg
Tue Aug 27 12:53:56 2019

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isim/TypeCheck_isim_beh.exe.sim/work/TypeCheck_isim_beh.exe_main.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_4228824053_1272247069_init();
xsi_register_tops("work_a_4228824053_1272247069");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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isim/TypeCheck_isim_beh.exe.sim/work/a_4228824053_1272247069.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/TypeCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_4228824053_1272247069_p_0(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(17, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5104);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 8U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4944);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_4228824053_1272247069_p_1(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 22);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5168);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 23U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4960);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_4228824053_1272247069_p_2(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(23, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(24, ng0);
t1 = (t0 + 7635);
*((int *)t1) = 7;
t2 = (t0 + 7639);
*((int *)t2) = 0;
t3 = 7;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(27, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5232);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4976);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(25, ng0);
t5 = (t0 + 2288U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1512U);
t8 = *((char **)t5);
t5 = (t0 + 7635);
t9 = *((int *)t5);
t10 = (t9 - 7);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2288U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7635);
t3 = *((int *)t1);
t2 = (t0 + 7639);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7635);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_4228824053_1272247069_p_3(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(33, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(34, ng0);
t1 = (t0 + 7643);
*((int *)t1) = 22;
t2 = (t0 + 7647);
*((int *)t2) = 0;
t3 = 22;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(37, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5296);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4992);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(35, ng0);
t5 = (t0 + 2408U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1672U);
t8 = *((char **)t5);
t5 = (t0 + 7643);
t9 = *((int *)t5);
t10 = (t9 - 22);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2408U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7643);
t3 = *((int *)t1);
t2 = (t0 + 7647);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7643);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_4228824053_1272247069_p_4(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(40, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 5360);
t7 = (t1 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
*((unsigned char *)t10) = t6;
xsi_driver_first_trans_fast_port(t1);
LAB2: t11 = (t0 + 5008);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_4228824053_1272247069_p_5(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
LAB0: xsi_set_current_line(41, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t5);
t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t6);
t1 = (t0 + 5424);
t8 = (t1 + 56U);
t9 = *((char **)t8);
t10 = (t9 + 56U);
t11 = *((char **)t10);
*((unsigned char *)t11) = t7;
xsi_driver_first_trans_fast_port(t1);
LAB2: t12 = (t0 + 5024);
*((int *)t12) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_4228824053_1272247069_init()
{
static char *pe[] = {(void *)work_a_4228824053_1272247069_p_0,(void *)work_a_4228824053_1272247069_p_1,(void *)work_a_4228824053_1272247069_p_2,(void *)work_a_4228824053_1272247069_p_3,(void *)work_a_4228824053_1272247069_p_4,(void *)work_a_4228824053_1272247069_p_5};
xsi_register_didat("work_a_4228824053_1272247069", "isim/TypeCheck_isim_beh.exe.sim/work/a_4228824053_1272247069.didat");
xsi_register_executes(pe);
}

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isim/isim_usage_statistics.html
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<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>980 ms, 657936 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>2640 ms, 103940 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>15</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>59</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>11</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>9</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>4</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 271896 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.15 sec, 275152 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>

27
isim/isim_usage_statistics.html~ Normal file
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@@ -0,0 +1,27 @@
<TABLE BORDER CELLSPACING=0 WIDTH='100%'>
<xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<<<<<<< HEAD
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>980 ms, 657936 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>15</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>59</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>9</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 271896 KB</xtag-isim-property-value></TD></TR>
=======
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>2640 ms, 103940 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>11</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>6</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>4</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.15 sec, 275152 KB</xtag-isim-property-value></TD></TR>
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section>
</TABLE>

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isim/pr_isim_beh.exe.sim/isimcrash.log Normal file
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28
isim/pr_isim_beh.exe.sim/isimkernel.log Normal file
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@@ -0,0 +1,28 @@
Command line:
pr_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 53338
Tue Aug 27 08:37:19 2019
Elaboration Time: 0.13 sec
Current Memory Usage: 198.603 Meg
Total Signals : 7
Total Nets : 49
Total Signal Drivers : 5
Total Blocks : 2
Total Primitive Blocks : 2
Total Processes : 5
Total Traceable Variables : 9
Total Scalar Nets and Variables : 410
Total Simulation Time: 0.14 sec
Current Memory Usage: 276.201 Meg
Tue Aug 27 08:37:30 2019

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325
isim/pr_isim_beh.exe.sim/work/a_2734820196_0181651160.c Normal file
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@@ -0,0 +1,325 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/pr.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439989832805790689_503743352(char *, char *, char *, char *, char *, char *);
char *ieee_p_2592010699_sub_207919886985903570_503743352(char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_2734820196_0181651160_p_0(char *t0)
{
char t1[16];
char t4[16];
char *t2;
char *t3;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 7008U);
t5 = (t0 + 1192U);
t6 = *((char **)t5);
t5 = (t0 + 7008U);
t7 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t4, t6, t5);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t3, t2, t7, t4);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4840);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4696);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_2734820196_0181651160_p_1(char *t0)
{
char t1[16];
char t2[16];
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(19, ng0);
LAB3: t3 = (t0 + 1032U);
t4 = *((char **)t3);
t3 = (t0 + 7008U);
t5 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t2, t4, t3);
t6 = (t0 + 1192U);
t7 = *((char **)t6);
t6 = (t0 + 7008U);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t5, t2, t7, t6);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4904);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4712);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_2734820196_0181651160_p_2(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(21, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t1 = (t0 + 4968);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 4728);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_2734820196_0181651160_p_3(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(22, ng0);
LAB3: t1 = (t0 + 1992U);
t2 = *((char **)t1);
t1 = (t0 + 5032);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 4744);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_2734820196_0181651160_p_4(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
int t19;
int t20;
unsigned int t21;
unsigned int t22;
unsigned int t23;
char *t24;
unsigned char t25;
unsigned char t26;
unsigned char t27;
char *t28;
char *t29;
LAB0: xsi_set_current_line(27, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(28, ng0);
t1 = (t0 + 7117);
*((int *)t1) = 7;
t2 = (t0 + 7121);
*((int *)t2) = 0;
t3 = 7;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(31, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5096);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast_port(t1);
t1 = (t0 + 4760);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(29, ng0);
t5 = (t0 + 2408U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1832U);
t8 = *((char **)t5);
t5 = (t0 + 7117);
t9 = *((int *)t5);
t10 = (t9 - 7);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t15);
t17 = (t0 + 1992U);
t18 = *((char **)t17);
t17 = (t0 + 7117);
t19 = *((int *)t17);
t20 = (t19 - 7);
t21 = (t20 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t17));
t22 = (1U * t21);
t23 = (0 + t22);
t24 = (t18 + t23);
t25 = *((unsigned char *)t24);
t26 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t16, t25);
t27 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t26);
t28 = (t0 + 2408U);
t29 = *((char **)t28);
t28 = (t29 + 0);
*((unsigned char *)t28) = t27;
LAB4: t1 = (t0 + 7117);
t3 = *((int *)t1);
t2 = (t0 + 7121);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7117);
*((int *)t5) = t3;
goto LAB2;
}
extern void work_a_2734820196_0181651160_init()
{
static char *pe[] = {(void *)work_a_2734820196_0181651160_p_0,(void *)work_a_2734820196_0181651160_p_1,(void *)work_a_2734820196_0181651160_p_2,(void *)work_a_2734820196_0181651160_p_3,(void *)work_a_2734820196_0181651160_p_4};
xsi_register_didat("work_a_2734820196_0181651160", "isim/pr_isim_beh.exe.sim/work/a_2734820196_0181651160.didat");
xsi_register_executes(pe);
}

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isim/pr_isim_beh.exe.sim/work/a_2734820196_0181651160.lin64.o Normal file
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39
isim/pr_isim_beh.exe.sim/work/pr_isim_beh.exe_main.c Normal file
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@@ -0,0 +1,39 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_2734820196_0181651160_init();
xsi_register_tops("work_a_2734820196_0181651160");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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isim/pr_isim_beh.exe.sim/work/pr_isim_beh.exe_main.lin64.o Normal file
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24
isim/precompiled.exe.sim/ieee/p_2592010699.c
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@@ -723,7 +723,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7736);
LAB9: t46 = (t1 + 7752);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -999,7 +999,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7801);
LAB9: t46 = (t1 + 7817);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -1280,7 +1280,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7866);
LAB9: t46 = (t1 + 7882);
xsi_report(t46, 66U, (unsigned char)3);
goto LAB10;
@@ -1571,7 +1571,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7932);
LAB9: t46 = (t1 + 7948);
xsi_report(t46, 66U, (unsigned char)3);
goto LAB10;
@@ -1853,7 +1853,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 7998);
LAB9: t46 = (t1 + 8014);
xsi_report(t46, 64U, (unsigned char)3);
goto LAB10;
@@ -2129,7 +2129,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8062);
LAB9: t46 = (t1 + 8078);
xsi_report(t46, 64U, (unsigned char)3);
goto LAB10;
@@ -2410,7 +2410,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8126);
LAB9: t46 = (t1 + 8142);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -2701,7 +2701,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8191);
LAB9: t46 = (t1 + 8207);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -2983,7 +2983,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8256);
LAB9: t46 = (t1 + 8272);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -3259,7 +3259,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8321);
LAB9: t46 = (t1 + 8337);
xsi_report(t46, 65U, (unsigned char)3);
goto LAB10;
@@ -3540,7 +3540,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8386);
LAB9: t46 = (t1 + 8402);
xsi_report(t46, 66U, (unsigned char)3);
goto LAB10;
@@ -3831,7 +3831,7 @@ LAB6: if ((unsigned char)0 == 0)
LAB10: goto LAB7;
LAB9: t46 = (t1 + 8452);
LAB9: t46 = (t1 + 8468);
xsi_report(t46, 66U, (unsigned char)3);
goto LAB10;

BIN
isim/precompiled.exe.sim/ieee/p_2592010699.lin64.o
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isim/tb_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Normal file
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0
isim/tb_isim_beh.exe.sim/isimcrash.log Normal file
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28
isim/tb_isim_beh.exe.sim/isimkernel.log Normal file
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@@ -0,0 +1,28 @@
Command line:
tb_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 49451
Tue Aug 27 09:36:05 2019
Elaboration Time: 0.12 sec
Current Memory Usage: 198.607 Meg
Total Signals : 13
Total Nets : 50
Total Signal Drivers : 6
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 7
Total Traceable Variables : 10
Total Scalar Nets and Variables : 412
Total Simulation Time: 0.13 sec
Current Memory Usage: 276.206 Meg
Tue Aug 27 09:36:11 2019

BIN
isim/tb_isim_beh.exe.sim/netId.dat Normal file
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isim/tb_isim_beh.exe.sim/tb_isim_beh.exe Normal file
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isim/tb_isim_beh.exe.sim/tmp_save/_1 Normal file
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374
isim/tb_isim_beh.exe.sim/work/a_3230118638_0181651160.c Normal file
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@@ -0,0 +1,374 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/ise/gianni/IEEE754Adder/pr.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439989832805790689_503743352(char *, char *, char *, char *, char *, char *);
char *ieee_p_2592010699_sub_207919886985903570_503743352(char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_3230118638_0181651160_p_0(char *t0)
{
char t1[16];
char t4[16];
char *t2;
char *t3;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 7176U);
t5 = (t0 + 1192U);
t6 = *((char **)t5);
t5 = (t0 + 7192U);
t7 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t4, t6, t5);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t3, t2, t7, t4);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 4960);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4816);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_3230118638_0181651160_p_1(char *t0)
{
char t1[16];
char t2[16];
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
char *t8;
char *t9;
unsigned int t10;
unsigned int t11;
unsigned char t12;
char *t13;
char *t14;
char *t15;
char *t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(19, ng0);
LAB3: t3 = (t0 + 1032U);
t4 = *((char **)t3);
t3 = (t0 + 7176U);
t5 = ieee_p_2592010699_sub_207919886985903570_503743352(IEEE_P_2592010699, t2, t4, t3);
t6 = (t0 + 1192U);
t7 = *((char **)t6);
t6 = (t0 + 7192U);
t8 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t5, t2, t7, t6);
t9 = (t1 + 12U);
t10 = *((unsigned int *)t9);
t11 = (1U * t10);
t12 = (8U != t11);
if (t12 == 1)
goto LAB5;
LAB6: t13 = (t0 + 5024);
t14 = (t13 + 56U);
t15 = *((char **)t14);
t16 = (t15 + 56U);
t17 = *((char **)t16);
memcpy(t17, t8, 8U);
xsi_driver_first_trans_fast(t13);
LAB2: t18 = (t0 + 4832);
*((int *)t18) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t11, 0);
goto LAB6;
}
static void work_a_3230118638_0181651160_p_2(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(21, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t1 = (t0 + 5088);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 4848);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_3230118638_0181651160_p_3(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(22, ng0);
LAB3: t1 = (t0 + 1992U);
t2 = *((char **)t1);
t1 = (t0 + 5152);
t3 = (t1 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
memcpy(t6, t2, 8U);
xsi_driver_first_trans_fast_port(t1);
LAB2: t7 = (t0 + 4864);
*((int *)t7) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_3230118638_0181651160_p_4(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
int t5;
char *t6;
char *t7;
unsigned char t8;
char *t9;
int t10;
int t11;
unsigned int t12;
unsigned int t13;
unsigned int t14;
char *t15;
unsigned char t16;
unsigned char t17;
char *t18;
char *t19;
int t20;
int t21;
unsigned int t22;
unsigned int t23;
unsigned int t24;
char *t25;
unsigned char t26;
unsigned char t27;
char *t28;
char *t29;
unsigned char t30;
unsigned char t31;
unsigned char t32;
char *t33;
LAB0: xsi_set_current_line(28, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(29, ng0);
t1 = (t0 + 2528U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(30, ng0);
t3 = (8 - 1);
t1 = (t0 + 7318);
*((int *)t1) = t3;
t2 = (t0 + 7322);
*((int *)t2) = 0;
t4 = t3;
t5 = 0;
LAB2: if (t4 >= t5)
goto LAB3;
LAB5: xsi_set_current_line(34, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 5216);
t6 = (t1 + 56U);
t7 = *((char **)t6);
t9 = (t7 + 56U);
t15 = *((char **)t9);
*((unsigned char *)t15) = t8;
xsi_driver_first_trans_fast_port(t1);
t1 = (t0 + 4880);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(31, ng0);
t6 = (t0 + 2408U);
t7 = *((char **)t6);
t8 = *((unsigned char *)t7);
t6 = (t0 + 1832U);
t9 = *((char **)t6);
t6 = (t0 + 7318);
t10 = *((int *)t6);
t11 = (t10 - 7);
t12 = (t11 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t6));
t13 = (1U * t12);
t14 = (0 + t13);
t15 = (t9 + t14);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16);
t18 = (t0 + 1992U);
t19 = *((char **)t18);
t18 = (t0 + 7318);
t20 = *((int *)t18);
t21 = (t20 - 7);
t22 = (t21 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t18));
t23 = (1U * t22);
t24 = (0 + t23);
t25 = (t19 + t24);
t26 = *((unsigned char *)t25);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t17, t26);
t28 = (t0 + 2528U);
t29 = *((char **)t28);
t30 = *((unsigned char *)t29);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t27, t30);
t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t8, t31);
t28 = (t0 + 2408U);
t33 = *((char **)t28);
t28 = (t33 + 0);
*((unsigned char *)t28) = t32;
xsi_set_current_line(32, ng0);
t1 = (t0 + 2528U);
t2 = *((char **)t1);
t8 = *((unsigned char *)t2);
t1 = (t0 + 1832U);
t6 = *((char **)t1);
t1 = (t0 + 7318);
t3 = *((int *)t1);
t10 = (t3 - 7);
t12 = (t10 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t1));
t13 = (1U * t12);
t14 = (0 + t13);
t7 = (t6 + t14);
t16 = *((unsigned char *)t7);
t9 = (t0 + 1992U);
t15 = *((char **)t9);
t9 = (t0 + 7318);
t11 = *((int *)t9);
t20 = (t11 - 7);
t22 = (t20 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t9));
t23 = (1U * t22);
t24 = (0 + t23);
t18 = (t15 + t24);
t17 = *((unsigned char *)t18);
t26 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t17);
t27 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t16, t26);
t30 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t27);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t30);
t19 = (t0 + 2528U);
t25 = *((char **)t19);
t19 = (t25 + 0);
*((unsigned char *)t19) = t31;
LAB4: t1 = (t0 + 7318);
t4 = *((int *)t1);
t2 = (t0 + 7322);
t5 = *((int *)t2);
if (t4 == t5)
goto LAB5;
LAB6: t3 = (t4 + -1);
t4 = t3;
t6 = (t0 + 7318);
*((int *)t6) = t4;
goto LAB2;
}
extern void work_a_3230118638_0181651160_init()
{
static char *pe[] = {(void *)work_a_3230118638_0181651160_p_0,(void *)work_a_3230118638_0181651160_p_1,(void *)work_a_3230118638_0181651160_p_2,(void *)work_a_3230118638_0181651160_p_3,(void *)work_a_3230118638_0181651160_p_4};
xsi_register_didat("work_a_3230118638_0181651160", "isim/tb_isim_beh.exe.sim/work/a_3230118638_0181651160.didat");
xsi_register_executes(pe);
}

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