lucacuzzocrea/IEEE754Adder
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

Merge branch 'master' of github.com:optimize-fast/IEEE754Adder

Browse Source 
Conflicts:
	IEEE754Adder.xise
	fuse.log
	fuseRelaunch.cmd
	isim.log
	isim/isim_usage_statistics.html
	isim/precompiled.exe.sim/ieee/p_2592010699.didat
This commit is contained in:
Luca Cuzzocrea
2019-08-28 22:03:08 +02:00
parent a91e1252d0 8b08af2782
commit b6c1d7abe2
130 changed files with 4284 additions and 57 deletions
Download Patch File Download Diff File Expand all files Collapse all files

46
fuse.log~ Normal file
View File

@@ -0,0 +1,46 @@
<<<<<<< HEAD
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj work.AdderTest
ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AdderTest.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 94252 KB
Fuse CPU Usage: 950 ms
Compiling package standard
Compiling package std_logic_1164
Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
Compiling architecture behavior of entity addertest
Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish...
Compiled 5 VHDL Units
Built simulation executable /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe
Fuse Memory Usage: 657936 KB
Fuse CPU Usage: 980 ms
GCC CPU Usage: 140 ms
=======
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -relaunch -intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/FullAdderTest_beh.prj" "work.FullAdderTest"
ISim P.20160913 (signature 0xfbc00daa)
Number of CPUs detected in this system: 1
Turning on mult-threading, number of parallel sub-compilation jobs: 0
Determining compilation order of HDL files
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdder.vhd" into library work
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/FullAdderTest.vhd" into library work
Starting static elaboration
Completed static elaboration
Fuse Memory Usage: 95308 KB
Fuse CPU Usage: 2530 ms
Compiling package standard
Compiling package std_logic_1164
Compiling architecture fulladderarch of entity FullAdder [fulladder_default]
Compiling architecture behavior of entity fulladdertest
Time Resolution for simulation is 1ps.
Compiled 5 VHDL Units
Built simulation executable /home/ise/gianni/IEEE754Adder/FullAdderTest_isim_beh.exe
Fuse Memory Usage: 103940 KB
Fuse CPU Usage: 2640 ms
GCC CPU Usage: 440 ms
>>>>>>> 8b08af27823a5242424518ae45bac27cb9e28f6d