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Luca
2019-08-17 17:41:27 +02:00
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<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Constraints Interaction Report Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Datasheet Section Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Detailed MAP Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Multiple Hierarchical Netlist Files" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Power Report" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Post-Place &amp; Route Simulation Model" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate RTL Schematic" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Generate SAIF File for Power Optimization/Estimation Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Testbench File" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Implementation Top Instance Path" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
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<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
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<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
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<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
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<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Output File Name" xil_pn:value="TypeCheck" xil_pn:valueState="default"/>
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<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
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<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="TypeCheck_timesim.vhd" xil_pn:valueState="default"/>
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="TypeCheck_synthesis.vhd" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
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<property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
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<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
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<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
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<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
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<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
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<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
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<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
<property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
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<property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
<!-- -->
<!-- The following properties are for internal use only. These should not be modified.-->
<!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="YYYY-MM-DDTHH:MM:SS" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnableToCalculate" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Unknown" xil_pn:valueState="default"/>
</properties>
<bindings/>
<libraries/>
<autoManagedFiles>
<!-- The following files are identified by `include statements in verilog -->
<!-- source files and are automatically managed by Project Navigator. -->
<!-- -->
<!-- Do not hand-edit this section, as it will be overwritten when the -->
<!-- project is analyzed based on files automatically identified as -->
<!-- include files. -->
</autoManagedFiles>
</project>

4
SpecialCasesCheck.cmd_log Normal file
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xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"

1
SpecialCasesCheck.lso Normal file
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work

1
SpecialCasesCheck.prj Normal file
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vhdl work "SpecialCasesCheck.vhd"

126
SpecialCasesCheck.syr Normal file
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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.04 secs
-->
Reading design: SpecialCasesCheck.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "SpecialCasesCheck.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "SpecialCasesCheck"
Output Format : NGC
Target Device : xc3s50-5-pq208
---- Source Options
Top Module Name : SpecialCasesCheck
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work.
Entity <typecheck> compiled.
Entity <typecheck> (Architecture <typecheckarch>) compiled.
ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. Undefined symbol 'std_logic_vector'.
ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. std_logic_vector: Undefined symbol (last report in this block)
ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. Undefined symbol 'std_logic'.
ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. std_logic: Undefined symbol (last report in this block)
ERROR:HDLParsers:3010 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 55. Entity SpecialCasesCheck does not exist.
-->
Total memory usage is 584420 kilobytes
Number of errors : 5 ( 0 filtered)
Number of warnings : 0 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

59
SpecialCasesCheck.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity TypeCheck is
port(
N: in std_logic_vector(31 downto 0);
NaN, INF: out std_logic
);
end TypeCheck;
architecture TypeCheckArch of TypeCheck is
signal G_Bus: std_logic_vector(7 downto 0);
signal T_Bus: std_logic_vector(22 downto 0);
signal G: std_logic := '1';
signal T: std_logic := '0';
begin
G_Bus <= N(30 downto 23);
T_Bus <= N(22 downto 0);
G_compute: process (G_Bus)
variable G_tmp: std_logic;
begin
G_tmp := '1';
for i in G_Bus'range loop
G_tmp := G_tmp and G_Bus(i);
end loop;
G <= G_tmp;
end process;
T_compute: process (T_Bus)
variable T_tmp: std_logic;
begin
T_tmp := '0';
for i in T_Bus'range loop
T_tmp := T_tmp or T_Bus(i);
end loop;
T <= T_tmp;
end process;
NaN <= G and T;
INF <= G and (not T);
end TypeCheckArch;
--entity SpecialCasesCheck is
-- port(
-- X, Y: in std_logic_vector(31 downto 0);
-- isNan, isZero: out std_logic
-- );
--end SpecialCasesCheck;
--
--
--architecture SpecialCasesCheckArch of SpecialCasesCheck is
--
--begin
--
--end SpecialCasesCheckArch;

56
SpecialCasesCheck.xst Normal file
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set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn SpecialCasesCheck.prj
-ifmt mixed
-ofn SpecialCasesCheck
-ofmt NGC
-p xc3s50-5-pq208
-top SpecialCasesCheck
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract Yes
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract Yes
-resource_sharing YES
-async_to_sync NO
-mult_style Auto
-iobuf YES
-max_fanout 500
-bufg 8
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

382
SpecialCasesCheck_envsettings.html Normal file
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<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<center><big><big><b>System Settings</b></big></big></center><br>
<A NAME="Environment Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Environment Variable</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>LD_LIBRARY_PATH</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>PATH</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_DSP</td>
<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_EDK</td>
<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
<tr>
<td>XILINX_PLANAHEAD</td>
<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
</tr>
</TABLE>
<A NAME="Synthesis Property Settings"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Switch Name</b></td>
<td><b>Property Name</b></td>
<td><b>Value</b></td>
<td><b>Default Value</b></td>
</tr>
<tr>
<td>-ifn</td>
<td>&nbsp;</td>
<td>SpecialCasesCheck.prj</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ifmt</td>
<td>&nbsp;</td>
<td>mixed</td>
<td>MIXED</td>
</tr>
<tr>
<td>-ofn</td>
<td>&nbsp;</td>
<td>SpecialCasesCheck</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-ofmt</td>
<td>&nbsp;</td>
<td>NGC</td>
<td>NGC</td>
</tr>
<tr>
<td>-p</td>
<td>&nbsp;</td>
<td>xc3s50-5-pq208</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-top</td>
<td>&nbsp;</td>
<td>SpecialCasesCheck</td>
<td>&nbsp;</td>
</tr>
<tr>
<td>-opt_mode</td>
<td>Optimization Goal</td>
<td>Speed</td>
<td>SPEED</td>
</tr>
<tr>
<td>-opt_level</td>
<td>Optimization Effort</td>
<td>1</td>
<td>1</td>
</tr>
<tr>
<td>-iuc</td>
<td>Use synthesis Constraints File</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-keep_hierarchy</td>
<td>Keep Hierarchy</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-netlist_hierarchy</td>
<td>Netlist Hierarchy</td>
<td>As_Optimized</td>
<td>as_optimized</td>
</tr>
<tr>
<td>-rtlview</td>
<td>Generate RTL Schematic</td>
<td>Yes</td>
<td>NO</td>
</tr>
<tr>
<td>-glob_opt</td>
<td>Global Optimization Goal</td>
<td>AllClockNets</td>
<td>ALLCLOCKNETS</td>
</tr>
<tr>
<td>-read_cores</td>
<td>Read Cores</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-write_timing_constraints</td>
<td>Write Timing Constraints</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-cross_clock_analysis</td>
<td>Cross Clock Analysis</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-bus_delimiter</td>
<td>Bus Delimiter</td>
<td>&lt;&gt;</td>
<td>&lt;&gt;</td>
</tr>
<tr>
<td>-slice_utilization_ratio</td>
<td>Slice Utilization Ratio</td>
<td>100</td>
<td>100%</td>
</tr>
<tr>
<td>-bram_utilization_ratio</td>
<td>BRAM Utilization Ratio</td>
<td>100</td>
<td>100%</td>
</tr>
<tr>
<td>-verilog2001</td>
<td>Verilog 2001</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-fsm_encoding</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-safe_implementation</td>
<td>&nbsp;</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-fsm_style</td>
<td>&nbsp;</td>
<td>LUT</td>
<td>LUT</td>
</tr>
<tr>
<td>-ram_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-ram_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-rom_extract</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-shreg_extract</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-rom_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-auto_bram_packing</td>
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-resource_sharing</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-async_to_sync</td>
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-mult_style</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
</tr>
<tr>
<td>-iobuf</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-max_fanout</td>
<td>&nbsp;</td>
<td>500</td>
<td>500</td>
</tr>
<tr>
<td>-bufg</td>
<td>&nbsp;</td>
<td>8</td>
<td>8</td>
</tr>
<tr>
<td>-register_duplication</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
</tr>
<tr>
<td>-register_balancing</td>
<td>&nbsp;</td>
<td>No</td>
<td>NO</td>
</tr>
<tr>
<td>-optimize_primitives</td>
<td>&nbsp;</td>
<td>NO</td>
<td>NO</td>
</tr>
<tr>
<td>-use_clock_enable</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-use_sync_set</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-use_sync_reset</td>
<td>&nbsp;</td>
<td>Yes</td>
<td>YES</td>
</tr>
<tr>
<td>-iob</td>
<td>&nbsp;</td>
<td>Auto</td>
<td>AUTO</td>
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<tr>
<td>-equivalent_register_removal</td>
<td>&nbsp;</td>
<td>YES</td>
<td>YES</td>
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<tr>
<td>-slice_utilization_ratio_maxmargin</td>
<td>&nbsp;</td>
<td>5</td>
<td>0%</td>
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<A NAME="Operating System Information"></A>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
</tr>
<tr bgcolor='#ffff99'>
<td><b>Operating System Information</b></td>
<td><b>xst</b></td>
<td><b>ngdbuild</b></td>
<td><b>map</b></td>
<td><b>par</b></td>
</tr>
<tr>
<td>CPU Architecture/Speed</td>
<td>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
<tr>
<td>Host</td>
<td>Xilinx</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
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<tr>
<td>OS Name</td>
<td>CentOS</td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
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<tr>
<td>OS Release</td>
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<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
<td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
</tr>
</TABLE>
</BODY> </HTML>

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<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
<TD ALIGN=CENTER COLSPAN='4'><B>SpecialCasesCheck Project Status (08/17/2019 - 16:41:04)</B></TD></TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
<TD>IEEE754Adder.xise</TD>
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
<TD> No Errors </TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
<TD>SpecialCasesCheck</TD>
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
<TD>Synthesized</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
<TD>xc3s50-5pq208</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
<TD>Balanced</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
<TD>
&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
<TD>&nbsp;</TD>
</TR>
<TR ALIGN=LEFT>
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
<TD>
<A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_envsettings.html'>
System Settings</A>
</TD>
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
<TD>&nbsp;&nbsp;</TD>
</TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 17 16:39:00 2019</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Post-PAR Static Timing Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
</TABLE>
&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
</TABLE>
<br><center><b>Date Generated:</b> 08/17/2019 - 16:41:04</center>
</BODY></HTML>

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vhdl work "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd"

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Release 14.7 ngdbuild P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle
ise -dd _ngo -nt timestamp -i -p xc3s50-pq208-5 TypeCheck.ngc TypeCheck.ngd
Reading NGO file "/home/Luca/ISE/IEEE754Adder/TypeCheck.ngc" ...
Gathering constraint information from source properties...
Done.
Resolving constraint associations...
Checking Constraint Associations...
Done...
Checking expanded design ...
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
NGDBUILD Design Results Summary:
Number of errors: 0
Number of warnings: 0
Total memory usage is 484492 kilobytes
Writing NGD file "TypeCheck.ngd" ...
Total REAL time to NGDBUILD completion: 2 sec
Total CPU time to NGDBUILD completion: 2 sec
Writing NGDBUILD log file "TypeCheck.bld"...

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map -intstyle ise -p xc3s50-pq208-5 -cm area -ir off -pr off -c 100 -o TypeCheck_map.ncd TypeCheck.ngd TypeCheck.pcf
par -w -intstyle ise -ol high -t 1 TypeCheck_map.ncd TypeCheck.ncd TypeCheck.pcf
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xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr"
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xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr"
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr"
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work

3
TypeCheck.ncd Normal file
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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6e
$72x74=(`fgn#A{la.KPA*OBML=>8Ljkes-Pt`enieIjh}Lhdah*snc9918>7GAPTV9J956294j7><5N=12>58e3:y><}=09/60>GIL;<0MCJ=B068EKB?02H^_RGAFN;8GJKJA]^NH:5LRDCWAA7<O11LSdc_F31?L653@;97D<=;H11?L253@?97D8=;H50?LHAk2CEJRgbp^KMB41<DFMBOLB;;O>3:0=I48:596@310<6?K:6:7?0B1?<>49M8429=2D7=80:;O>22;3<F5;<285A<0:=1>H;904?7C2>>49M8769=2D7><0:;O>16;3<F588285A<36=1>H;:<4>7C2=6?78J9406<1E0?615:L?6<833G69285A<22=3>H;;80;285A<23=0>H;;7>0B1:14:L?1;2<F5<586@37?68J9>9<2D753=4N`L`?KgIW`g{SCoA109L7>IU::1D^>=4OS:`?U(5889:<<=PL59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ3:PWHg=TANH^_RGAFNc8WLAXJ\YBHUl4SHE\FPUIIDO:7Y:4TXRF<>RXadzTX<m4T^vntZiu89:;h6ZPtlr\kw6789;o7YQ{mq]lv5678;n0XRzbp^mq4567;8:0XRzbp^mq4567W`g{o6ZPtlr\kw6788n0XRzbp^mq45669m1_Syc_np34575l2^Tx`~Pos23445682^Tx`~Pos2344Yney30Xt~jCig`o<=QAL]TXT^J1e9[MIOIP$RON->!1!QWQG&7&8*J_NGF6:ZPPIOE9l1S_YQFMQNFI@HSI]CDBRM@NRVQELHS[8:0T^ZPRUN\TWIWM[^R:6Vkb^Kg55=_ldUFmga}Vdppmjh682RoaRCfnnpUawungg90T~z6;YqwCHicmel0b{}cd]emiciidon7um<s42.1(vv:92vLM~l4:BC|0b=N381=v]6:4a97`<6;=;=:<4=4`abk3f281e9o49;%7:>03<uZ219n4<e;300401938?mnm4d4194?7=9rY268m53d827171>8098lmn;wD76?6=93;1<v]6:4a97`<6;=;=:<4=4`ab?!3328<0(>h53:`67?6=:;0=6?;tL4595~"4n3?m7pB:8;3x 0c=82w/8:4:3:X4>4}62tP??7?t2;l7=<722e:87>5;h13>5<#<809j6`;0;28?l4b290/8<4=f:l74?7<3`8h6=4+4081b>h383807d<m:18'04<5n2d?<7=4;h0b>5<#<809j6`;0;68?l4>290/8<4=f:l74?3<3`836=4+4081b>h383<07d<8:18'04<5n2d?<794;h05>5<#<809j6`;0;:8?l42290/8<4=f:l74??<3`8?6=4+4081b>h383k07d<<:18'04<5n2d?<7l4;h02>5<#<809j6`;0;a8?l47290/8<4=f:l74?b<3`;m6=4+4081b>h383o07d?j:18'04<5n2d?<7h4;h3g>5<#<809j6`;0;33?>o6k3:1(9?52g9m05<6921b=o4?:%62>7`<f=:1=?54i0c94?"3938m7c:?:018?l7>290/8<4=f:l74?7332c:47>5$5396c=i<90:965f3683>!262;l0b9>51798m60=83.?=7<i;o63>41<3`9>6=4+4081b>h383;376g<4;29 17=:o1e8=4>9:9j76<72->:6?h4n5295d=<a:81<7*;1;0e?k2728h07d=>:18'04<5n2d?<7?l;:k1`?6=,=;1>k5a4182`>=n:;0;6):>:3d8j16=9l10e<950;&75?4a3g>;6<h4;c6g>5<d2:0nw):8:5f8k1?=831b>84?::k10?6=3`886=44i3394?=n:90;66g>f;29?l7b2900e<j50;9j5f<722c:n7>5;h3b>5<<j=k1<7750;2x 11=;m1C9;5fc;29?lb=831bi7>5;hd94?=n990;66g>1;29?l752900e<=50;9l7d<722wi8o4?:583>5}#<>08o6F:6:k`>5<<am0;66gj:188k6g=831vn9m50;194?6|,==1?o5G579jg?6=3`n1<75`3`83>>{t<00;6?uQ489>0f<4i2wx>84?:3y]60=:<h0o7p}=4;296~X5<27?m7m4}r00>5<5sW8870:n:d9~w77=838pR??4=5c955=z{;:1<7<t^32891g=n2wx=k4?:3y]5c=:<h0:=6s|1d83>7}Y9l168l4>3:p5a<72;qU=i524`826>{t9j0;6?uQ1b9>0g<c3ty:n7>52z\2f>;3j3i0q~?n:181[7f34>i6h5rs5c94?4|5=k1?l524b8`?xu3j3:1>v3;b;1b?82d2m1vqo;=:18`>6<bs-><68<4o5g94?=n<00;66g>9;29?l7?2900e>950;9j73<722c897>5;h17>5<<a:91<75f3383>>o493:17d<k:188f1`=8331<7>t$5597a=O=?1bo7>5;hf94?=nm3:17dh50;9j55<722c:=7>5;h31>5<<a891<75`3`83>>{e=90;694?:1y'02<4k2B>:6gl:188ma<722cn6=44o2c94?=zj<;1<7=50;2x 11=;k1C9;5fc;29?lb=831d?l4?::p0`<72;qU8h525080e>{t<00;6?uQ489>0c<c3ty:57>52z\2=>;3n3i0q~?7:181[7?34>m6h5rs2594?4|V:=019h5119~w60=838pR>84=5d9b>{t;<0;6?uQ349>0c<692wx?94?:3y]71=:<o0:?6s|3283>7}Y;:168k4>2:p77<72;qU??52518g?xu493:1>vP<1:?64?e<uz8o6=4={_0g?8372l1v9h50;0x91`=;h169<4l;|q64?6=:r7><7=n;<72>a=zuk926=4<:183!202=1C9;5fc;29?lb=831d?l4?::af?6=13:1<v*;7;48L00<aj0;66gk:188m`<722cm6=44i0294?=n980;66g>2;29?l742900c>o50;9~f1>=83>1<7>t$5597f=O=?1bo7>5;hf94?=nm3:17b=n:188yg7229086=4?{%64>0=O=?1bo7>5;hf94?=h;h0;66s|3983>7}Y;116?44<a:p51<72;qU=9521480e>{ti3:1?v3<9;a89g<4i27:97j4}r65>5<4s4926i524980e>;6=3i0q~:6:18182c2=3018<5489~w1c=838p18<54d9>0=<d3ty9i7>52z\1a>;e2j1/884=f:l70?7<uz8h6=4={_0`?8d=l2.?97<i;o67>7=z{;h1<7<t^3`89g<b3->>6?h4n5697>{t:h0;6?uQ2`9>f?`<,=?1>k5a4587?xu513:1>vP=9:?a>46<,=?1>k5a4586?xu503:1>vP=8:?a>47<,=?1>k5a4585?xu5?3:1>vP=7:?a>44<,=?1>k5a4584?xu5>3:1>vP=6:?a>45<,=?1>k5a458;?xu5=3:1>vP=5:?7`?423->>6?h4n569=>{t:=0;6?uQ259>0a<5<2.?97<i;o67>d=z{;91<7<t^31891b=::1/884=f:l70?d<uz8:6=4={_02?82c2;;0(9;52g9m01<d3ty9<7>52z\14>;3l38;7):::3d8j12=l2wx=k4?:3y]5c=:<m0:j6*;5;0e?k232l1v<k50;0xZ4c<5=n1=h5+4481b>h3<3l0q~?k:181[7c34>o6<j4$5796c=i<=0:<6s|1b83>7}Y9j168i4>c:&71?4a3g>?6<?4}r3a>5<5sW;i70:k:0`8 13=:o1e894>2:p5d<72;qU=l524e82e>"3=38m7c:;:018yv7>2909wS?6;<71>4?<,=?1>k5a45820>{t910;6?uQ199>17<602.?97<i;o67>43<uz9<6=4={_14?8352:=0(9;52g9m01<6>2wx?;4?:3y]73=:=;08:6*;5;0e?k2328=0q~=::181[5234?96>;4$5796c=i<=0:46s|3583>7}Y;=169?4<4:&71?4a3g>?6<74}r10>5<5sW9870;=:218 13=:o1e894>a:p77<72;qU??5253806>"3=38m7c:;:0`8yv562909wS=>;<71>67<,=?1>k5a4582g>{t:m0;6?uQ2e9>17<5l2.?97<i;o67>4b<uz896=4={_01?82?2m1/884=f:l70?7b3ty:;7>52z\23>;303o0(9;52g9m01<6n2wvqpsO@By`0?02m0;j89sO@Cy3yEFWstJK

238
TypeCheck.pad Normal file
View File

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Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sat Aug 17 16:41:02 2019
# NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
INPUT FILE: TypeCheck_map.ncd
OUTPUT FILE: TypeCheck.pad
PART TYPE: xc3s50
SPEED GRADE: -5
PACKAGE: pq208
Pinout by Pin Number:
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity|
P1|||GND||||||||||||
P2||DIFFM|IO_L01P_7/VRN_7|UNUSED||7|||||||||
P3||DIFFS|IO_L01N_7/VRP_7|UNUSED||7|||||||||
P4|||NC||||||||||||
P5|||NC||||||||||||
P6|||VCCO_7|||7|||||any******||||
P7||DIFFM|IO_L19P_7|UNUSED||7|||||||||
P8|||GND||||||||||||
P9||DIFFS|IO_L19N_7/VREF_7|UNUSED||7|||||||||
P10||DIFFM|IO_L20P_7|UNUSED||7|||||||||
P11||DIFFS|IO_L20N_7|UNUSED||7|||||||||
P12||DIFFM|IO_L21P_7|UNUSED||7|||||||||
P13||DIFFS|IO_L21N_7|UNUSED||7|||||||||
P14|||GND||||||||||||
P15||DIFFM|IO_L22P_7|UNUSED||7|||||||||
P16||DIFFS|IO_L22N_7|UNUSED||7|||||||||
P17|||VCCAUX||||||||2.5||||
P18||DIFFM|IO_L23P_7|UNUSED||7|||||||||
P19||DIFFS|IO_L23N_7|UNUSED||7|||||||||
P20||DIFFM|IO_L24P_7|UNUSED||7|||||||||
P21||DIFFS|IO_L24N_7|UNUSED||7|||||||||
P22|||NC||||||||||||
P23|||VCCO_7|||7|||||any******||||
P24|||NC||||||||||||
P25|||GND||||||||||||
P26||DIFFM|IO_L40P_7|UNUSED||7|||||||||
P27||DIFFS|IO_L40N_7/VREF_7|UNUSED||7|||||||||
P28||DIFFM|IO_L40P_6/VREF_6|UNUSED||6|||||||||
P29||DIFFS|IO_L40N_6|UNUSED||6|||||||||
P30|||GND||||||||||||
P31|||NC||||||||||||
P32|||VCCO_6|||6|||||any******||||
P33|||NC||||||||||||
P34||DIFFM|IO_L24P_6|UNUSED||6|||||||||
P35||DIFFS|IO_L24N_6/VREF_6|UNUSED||6|||||||||
P36||DIFFM|IO_L23P_6|UNUSED||6|||||||||
P37||DIFFS|IO_L23N_6|UNUSED||6|||||||||
P38|||VCCAUX||||||||2.5||||
P39||DIFFM|IO_L22P_6|UNUSED||6|||||||||
P40||DIFFS|IO_L22N_6|UNUSED||6|||||||||
P41|||GND||||||||||||
P42||DIFFM|IO_L21P_6|UNUSED||6|||||||||
P43||DIFFS|IO_L21N_6|UNUSED||6|||||||||
P44||DIFFM|IO_L20P_6|UNUSED||6|||||||||
P45||DIFFS|IO_L20N_6|UNUSED||6|||||||||
P46||DIFFM|IO_L19P_6|UNUSED||6|||||||||
P47|||GND||||||||||||
P48||DIFFS|IO_L19N_6|UNUSED||6|||||||||
P49|||VCCO_6|||6|||||any******||||
P50|||NC||||||||||||
P51||DIFFM|IO_L01P_6/VRN_6|UNUSED||6|||||||||
P52||DIFFS|IO_L01N_6/VRP_6|UNUSED||6|||||||||
P53|||GND||||||||||||
P54|||M1||||||||||||
P55|||M0||||||||||||
P56|||M2||||||||||||
P57||DIFFM|IO_L01P_5/CS_B|UNUSED||5|||||||||
P58||DIFFS|IO_L01N_5/RDWR_B|UNUSED||5|||||||||
P59|||GND||||||||||||
P60|||VCCO_5|||5|||||any******||||
P61||DIFFM|IO_L10P_5/VRN_5|UNUSED||5|||||||||
P62||DIFFS|IO_L10N_5/VRP_5|UNUSED||5|||||||||
P63||IOB|IO|UNUSED||5|||||||||
P64||DIFFM|IO_L27P_5|UNUSED||5|||||||||
P65||DIFFS|IO_L27N_5/VREF_5|UNUSED||5|||||||||
P66|||GND||||||||||||
P67||DIFFM|IO_L28P_5/D7|UNUSED||5|||||||||
P68||DIFFS|IO_L28N_5/D6|UNUSED||5|||||||||
P69|||VCCAUX||||||||2.5||||
P70|||VCCINT||||||||1.2||||
P71||IOB|IO|UNUSED||5|||||||||
P72||DIFFM|IO_L31P_5/D5|UNUSED||5|||||||||
P73|||VCCO_5|||5|||||any******||||
P74||DIFFS|IO_L31N_5/D4|UNUSED||5|||||||||
P75|||GND||||||||||||
P76||DIFFM|IO_L32P_5/GCLK2|UNUSED||5|||||||||
P77||DIFFS|IO_L32N_5/GCLK3|UNUSED||5|||||||||
P78||IOB|IO/VREF_5|UNUSED||5|||||||||
P79||DIFFM|IO_L32P_4/GCLK0|UNUSED||4|||||||||
P80||DIFFS|IO_L32N_4/GCLK1|UNUSED||4|||||||||
P81||DIFFM|IO_L31P_4/DOUT/BUSY|UNUSED||4|||||||||
P82|||GND||||||||||||
P83||DIFFS|IO_L31N_4/INIT_B|UNUSED||4|||||||||
P84|||VCCO_4|||4|||||any******||||
P85||IOB|IO/VREF_4|UNUSED||4|||||||||
P86||DIFFM|IO_L30P_4/D3|UNUSED||4|||||||||
P87||DIFFS|IO_L30N_4/D2|UNUSED||4|||||||||
P88|||VCCINT||||||||1.2||||
P89|||VCCAUX||||||||2.5||||
P90||DIFFM|IO_L27P_4/D1|UNUSED||4|||||||||
P91|||GND||||||||||||
P92||DIFFS|IO_L27N_4/DIN/D0|UNUSED||4|||||||||
P93||IOB|IO|UNUSED||4|||||||||
P94||DIFFM|IO_L25P_4|UNUSED||4|||||||||
P95||DIFFS|IO_L25N_4|UNUSED||4|||||||||
P96|||NC||||||||||||
P97|||NC||||||||||||
P98|||VCCO_4|||4|||||any******||||
P99|||GND||||||||||||
P100||DIFFM|IO_L01P_4/VRN_4|UNUSED||4|||||||||
P101||DIFFS|IO_L01N_4/VRP_4|UNUSED||4|||||||||
P102||IOB|IO/VREF_4|UNUSED||4|||||||||
P103|||DONE||||||||||||
P104|||CCLK||||||||||||
P105|||GND||||||||||||
P106||DIFFM|IO_L01P_3/VRN_3|UNUSED||3|||||||||
P107||DIFFS|IO_L01N_3/VRP_3|UNUSED||3|||||||||
P108|||NC||||||||||||
P109|||NC||||||||||||
P110|||VCCO_3|||3|||||any******||||
P111||DIFFM|IO_L19P_3|UNUSED||3|||||||||
P112|||GND||||||||||||
P113||DIFFS|IO_L19N_3|UNUSED||3|||||||||
P114||DIFFM|IO_L20P_3|UNUSED||3|||||||||
P115||DIFFS|IO_L20N_3|UNUSED||3|||||||||
P116||DIFFM|IO_L21P_3|UNUSED||3|||||||||
P117||DIFFS|IO_L21N_3|UNUSED||3|||||||||
P118|||GND||||||||||||
P119||DIFFM|IO_L22P_3|UNUSED||3|||||||||
P120||DIFFS|IO_L22N_3|UNUSED||3|||||||||
P121|||VCCAUX||||||||2.5||||
P122||DIFFM|IO_L23P_3/VREF_3|UNUSED||3|||||||||
P123||DIFFS|IO_L23N_3|UNUSED||3|||||||||
P124||DIFFM|IO_L24P_3|UNUSED||3|||||||||
P125||DIFFS|IO_L24N_3|UNUSED||3|||||||||
P126|||NC||||||||||||
P127|||VCCO_3|||3|||||any******||||
P128|||NC||||||||||||
P129|||GND||||||||||||
P130||DIFFM|IO_L40P_3|UNUSED||3|||||||||
P131||DIFFS|IO_L40N_3/VREF_3|UNUSED||3|||||||||
P132||DIFFM|IO_L40P_2/VREF_2|UNUSED||2|||||||||
P133||DIFFS|IO_L40N_2|UNUSED||2|||||||||
P134|||GND||||||||||||
P135|||NC||||||||||||
P136|||VCCO_2|||2|||||any******||||
P137|||NC||||||||||||
P138||DIFFM|IO_L24P_2|UNUSED||2|||||||||
P139||DIFFS|IO_L24N_2|UNUSED||2|||||||||
P140||DIFFM|IO_L23P_2|UNUSED||2|||||||||
P141||DIFFS|IO_L23N_2/VREF_2|UNUSED||2|||||||||
P142|||VCCAUX||||||||2.5||||
P143||DIFFM|IO_L22P_2|UNUSED||2|||||||||
P144||DIFFS|IO_L22N_2|UNUSED||2|||||||||
P145|||GND||||||||||||
P146||DIFFM|IO_L21P_2|UNUSED||2|||||||||
P147||DIFFS|IO_L21N_2|UNUSED||2|||||||||
P148||DIFFM|IO_L20P_2|UNUSED||2|||||||||
P149||DIFFS|IO_L20N_2|UNUSED||2|||||||||
P150||DIFFM|IO_L19P_2|UNUSED||2|||||||||
P151|||GND||||||||||||
P152||DIFFS|IO_L19N_2|UNUSED||2|||||||||
P153|||VCCO_2|||2|||||any******||||
P154|||NC||||||||||||
P155||DIFFM|IO_L01P_2/VRN_2|UNUSED||2|||||||||
P156||DIFFS|IO_L01N_2/VRP_2|UNUSED||2|||||||||
P157|||GND||||||||||||
P158|||TDO||||||||||||
P159|||TCK||||||||||||
P160|||TMS||||||||||||
P161||DIFFM|IO_L01P_1/VRN_1|UNUSED||1|||||||||
P162||DIFFS|IO_L01N_1/VRP_1|UNUSED||1|||||||||
P163|||GND||||||||||||
P164|||VCCO_1|||1|||||any******||||
P165||DIFFM|IO_L10P_1|UNUSED||1|||||||||
P166||DIFFS|IO_L10N_1/VREF_1|UNUSED||1|||||||||
P167||IOB|IO|UNUSED||1|||||||||
P168||DIFFM|IO_L27P_1|UNUSED||1|||||||||
P169||DIFFS|IO_L27N_1|UNUSED||1|||||||||
P170|||GND||||||||||||
P171||DIFFM|IO_L28P_1|UNUSED||1|||||||||
P172||DIFFS|IO_L28N_1|UNUSED||1|||||||||
P173|||VCCAUX||||||||2.5||||
P174|||VCCINT||||||||1.2||||
P175||IOB|IO|UNUSED||1|||||||||
P176||DIFFM|IO_L31P_1|UNUSED||1|||||||||
P177|||VCCO_1|||1|||||any******||||
P178||DIFFS|IO_L31N_1/VREF_1|UNUSED||1|||||||||
P179|||GND||||||||||||
P180||DIFFM|IO_L32P_1/GCLK4|UNUSED||1|||||||||
P181||DIFFS|IO_L32N_1/GCLK5|UNUSED||1|||||||||
P182||IOB|IO|UNUSED||1|||||||||
P183|NaN|IOB|IO_L32P_0/GCLK6|OUTPUT|LVCMOS25*|0|12|SLOW|NONE**|||UNLOCATED|NO|NONE|
P184|N<0>|IOB|IO_L32N_0/GCLK7|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
P185|N<23>|IOB|IO_L31P_0/VREF_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE|
P186|||GND||||||||||||
P187|INF|IOB|IO_L31N_0|OUTPUT|LVCMOS25*|0|12|SLOW|NONE**|||UNLOCATED|NO|NONE|
P188|||VCCO_0|||0|||||2.50||||
P189||IOB|IO|UNUSED||0|||||||||
P190||DIFFM|IO_L30P_0|UNUSED||0|||||||||
P191||DIFFS|IO_L30N_0|UNUSED||0|||||||||
P192|||VCCINT||||||||1.2||||
P193|||VCCAUX||||||||2.5||||
P194||DIFFM|IO_L27P_0|UNUSED||0|||||||||
P195|||GND||||||||||||
P196||DIFFS|IO_L27N_0|UNUSED||0|||||||||
P197||IOB|IO|UNUSED||0|||||||||
P198||DIFFM|IO_L25P_0|UNUSED||0|||||||||
P199||DIFFS|IO_L25N_0|UNUSED||0|||||||||
P200|||NC||||||||||||
P201|||VCCO_0|||0|||||2.50||||
P202|||GND||||||||||||
P203||DIFFM|IO_L01P_0/VRN_0|UNUSED||0|||||||||
P204||DIFFS|IO_L01N_0/VRP_0|UNUSED||0|||||||||
P205||IOB|IO/VREF_0|UNUSED||0|||||||||
P206|||HSWAP_EN||||||||||||
P207|||PROG_B||||||||||||
P208|||TDI||||||||||||
-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

148
TypeCheck.par Normal file
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Release 14.7 par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Xilinx:: Sat Aug 17 16:41:01 2019
par -w -intstyle ise -ol high -t 1 TypeCheck_map.ncd TypeCheck.ncd
TypeCheck.pcf
Constraints file: TypeCheck.pcf.
Loading device for application Rf_Device from file '3s50.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"TypeCheck" is an NCD, version 3.2, device xc3s50, package pq208, speed -5
Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
-x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
internal clocks in this design. Because there are not defined timing requirements, a timing score will not be
reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock.
Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high".
Device speed data version: "PRODUCTION 1.39 2013-10-13".
Device Utilization Summary:
Number of External IOBs 4 out of 124 3%
Number of LOCed IOBs 0 out of 4 0%
Number of Slices 2 out of 768 1%
Number of SLICEMs 0 out of 384 0%
Overall effort level (-ol): High
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): High
Starting initial Timing Analysis. REAL time: 0 secs
Finished initial Timing Analysis. REAL time: 0 secs
Starting Placer
Total REAL time at the beginning of Placer: 0 secs
Total CPU time at the beginning of Placer: 0 secs
Phase 1.1 Initial Placement Analysis
Phase 1.1 Initial Placement Analysis (Checksum:14) REAL time: 0 secs
Phase 2.7 Design Feasibility Check
Phase 2.7 Design Feasibility Check (Checksum:14) REAL time: 0 secs
Phase 3.31 Local Placement Optimization
Phase 3.31 Local Placement Optimization (Checksum:14) REAL time: 0 secs
Phase 4.2 Initial Clock and IO Placement
...
Phase 4.2 Initial Clock and IO Placement (Checksum:14) REAL time: 0 secs
Phase 5.36 Local Placement Optimization
Phase 5.36 Local Placement Optimization (Checksum:14) REAL time: 0 secs
Phase 6.3 Local Placement Optimization
...
Phase 6.3 Local Placement Optimization (Checksum:2a817b) REAL time: 0 secs
Phase 7.5 Local Placement Optimization
Phase 7.5 Local Placement Optimization (Checksum:2a817b) REAL time: 0 secs
Phase 8.8 Global Placement
..
Phase 8.8 Global Placement (Checksum:78ce46) REAL time: 0 secs
Phase 9.5 Local Placement Optimization
Phase 9.5 Local Placement Optimization (Checksum:78ce46) REAL time: 0 secs
Phase 10.18 Placement Optimization
Phase 10.18 Placement Optimization (Checksum:78ce46) REAL time: 0 secs
Phase 11.5 Local Placement Optimization
Phase 11.5 Local Placement Optimization (Checksum:78ce46) REAL time: 0 secs
Total REAL time to Placer completion: 0 secs
Total CPU time to Placer completion: 0 secs
Writing design to file TypeCheck.ncd
Starting Router
Phase 1 : 10 unrouted; REAL time: 0 secs
Phase 2 : 10 unrouted; REAL time: 0 secs
Phase 3 : 2 unrouted; REAL time: 0 secs
Phase 4 : 2 unrouted; (Par is working to improve performance) REAL time: 1 secs
Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
Updating file: TypeCheck.ncd with current fully routed design.
Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs
Total REAL time to Router completion: 1 secs
Total CPU time to Router completion: 1 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
Timing Score: 0 (Setup: 0, Hold: 0)
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 1 secs
Total CPU time to PAR completion: 1 secs
Peak Memory Usage: 600 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 1
Writing design to file TypeCheck.ncd
PAR done!

4
TypeCheck.pcf Normal file
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@@ -0,0 +1,4 @@
//! **************************************************************************
// Written by: Map P.20131013 on Sat Aug 17 16:40:58 2019
//! **************************************************************************

1
TypeCheck.prj Normal file
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@@ -0,0 +1 @@
vhdl work "SpecialCasesCheck.vhd"

332
TypeCheck.ptwx Normal file
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@@ -0,0 +1,332 @@
<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twBody><twSumRpt></twSumRpt></twBody></twReport>

0
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296
TypeCheck.syr Normal file
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Release 14.7 - xst P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
-->
Parameter TMPDIR set to xst/projnav.tmp
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
-->
Parameter xsthdpdir set to xst
Total REAL time to Xst completion: 0.00 secs
Total CPU time to Xst completion: 0.05 secs
-->
Reading design: TypeCheck.prj
TABLE OF CONTENTS
1) Synthesis Options Summary
2) HDL Compilation
3) Design Hierarchy Analysis
4) HDL Analysis
5) HDL Synthesis
5.1) HDL Synthesis Report
6) Advanced HDL Synthesis
6.1) Advanced HDL Synthesis Report
7) Low Level Synthesis
8) Partition Report
9) Final Report
9.1) Device utilization summary
9.2) Partition Resource Summary
9.3) TIMING REPORT
=========================================================================
* Synthesis Options Summary *
=========================================================================
---- Source Parameters
Input File Name : "TypeCheck.prj"
Input Format : mixed
Ignore Synthesis Constraint File : NO
---- Target Parameters
Output File Name : "TypeCheck"
Output Format : NGC
Target Device : xc3s50-5-pq208
---- Source Options
Top Module Name : TypeCheck
Automatic FSM Extraction : YES
FSM Encoding Algorithm : Auto
Safe Implementation : No
FSM Style : LUT
RAM Extraction : Yes
RAM Style : Auto
ROM Extraction : Yes
Mux Style : Auto
Decoder Extraction : YES
Priority Encoder Extraction : Yes
Shift Register Extraction : YES
Logical Shifter Extraction : YES
XOR Collapsing : YES
ROM Style : Auto
Mux Extraction : Yes
Resource Sharing : YES
Asynchronous To Synchronous : NO
Multiplier Style : Auto
Automatic Register Balancing : No
---- Target Options
Add IO Buffers : YES
Global Maximum Fanout : 500
Add Generic Clock Buffer(BUFG) : 8
Register Duplication : YES
Slice Packing : YES
Optimize Instantiated Primitives : NO
Use Clock Enable : Yes
Use Synchronous Set : Yes
Use Synchronous Reset : Yes
Pack IO Registers into IOBs : Auto
Equivalent register Removal : YES
---- General Options
Optimization Goal : Speed
Optimization Effort : 1
Keep Hierarchy : No
Netlist Hierarchy : As_Optimized
RTL Output : Yes
Global Optimization : AllClockNets
Read Cores : YES
Write Timing Constraints : NO
Cross Clock Analysis : NO
Hierarchy Separator : /
Bus Delimiter : <>
Case Specifier : Maintain
Slice Utilization Ratio : 100
BRAM Utilization Ratio : 100
Verilog 2001 : YES
Auto BRAM Packing : NO
Slice Utilization Ratio Delta : 5
=========================================================================
=========================================================================
* HDL Compilation *
=========================================================================
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work.
Architecture typecheckarch of Entity typecheck is up to date.
=========================================================================
* Design Hierarchy Analysis *
=========================================================================
Analyzing hierarchy for entity <TypeCheck> in library <work> (architecture <typecheckarch>).
=========================================================================
* HDL Analysis *
=========================================================================
Analyzing Entity <TypeCheck> in library <work> (Architecture <typecheckarch>).
Entity <TypeCheck> analyzed. Unit <TypeCheck> generated.
=========================================================================
* HDL Synthesis *
=========================================================================
Performing bidirectional port resolution...
Synthesizing Unit <TypeCheck>.
Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd".
WARNING:Xst:647 - Input <N<31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
Unit <TypeCheck> synthesized.
=========================================================================
HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Advanced HDL Synthesis *
=========================================================================
=========================================================================
Advanced HDL Synthesis Report
Found no macro
=========================================================================
=========================================================================
* Low Level Synthesis *
=========================================================================
Optimizing unit <TypeCheck> ...
Mapping all equations...
Building and optimizing final netlist ...
Found area constraint ratio of 100 (+ 5) on block TypeCheck, actual ratio is 0.
Final Macro Processing ...
=========================================================================
Final Register Report
Found no macro
=========================================================================
=========================================================================
* Partition Report *
=========================================================================
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
=========================================================================
* Final Report *
=========================================================================
Final Results
RTL Top Level Output File Name : TypeCheck.ngr
Top Level Output File Name : TypeCheck
Output Format : NGC
Optimization Goal : Speed
Keep Hierarchy : No
Design Statistics
# IOs : 34
Cell Usage :
# BELS : 18
# GND : 1
# LUT3 : 3
# LUT4 : 7
# MUXCY : 6
# VCC : 1
# IO Buffers : 33
# IBUF : 31
# OBUF : 2
=========================================================================
Device utilization summary:
---------------------------
Selected Device : 3s50pq208-5
Number of Slices: 5 out of 768 0%
Number of 4 input LUTs: 10 out of 1536 0%
Number of IOs: 34
Number of bonded IOBs: 33 out of 124 26%
---------------------------
Partition Resource Summary:
---------------------------
No Partitions were found in this design.
---------------------------
=========================================================================
TIMING REPORT
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
GENERATED AFTER PLACE-and-ROUTE.
Clock Information:
------------------
No clock signals found in this design
Asynchronous Control Signals Information:
----------------------------------------
No asynchronous control signals found in this design
Timing Summary:
---------------
Speed Grade: -5
Minimum period: No path found
Minimum input arrival time before clock: No path found
Maximum output required time after clock: No path found
Maximum combinational path delay: 9.965ns
Timing Detail:
--------------
All values displayed in nanoseconds (ns)
=========================================================================
Timing constraint: Default path analysis
Total number of paths / destination ports: 62 / 2
-------------------------------------------------------------------------
Delay: 9.965ns (Levels of Logic = 10)
Source: N<3> (PAD)
Destination: NaN (PAD)
Data Path: N<3> to NaN
Gate Net
Cell:in->out fanout Delay Delay Logical Name (Net Name)
---------------------------------------- ------------
IBUF:I->O 1 0.715 0.976 N_3_IBUF (N_3_IBUF)
LUT3:I0->O 1 0.479 0.000 T_wg_lut<0> (T_wg_lut<0>)
MUXCY:S->O 1 0.435 0.000 T_wg_cy<0> (T_wg_cy<0>)
MUXCY:CI->O 1 0.056 0.000 T_wg_cy<1> (T_wg_cy<1>)
MUXCY:CI->O 1 0.056 0.000 T_wg_cy<2> (T_wg_cy<2>)
MUXCY:CI->O 1 0.056 0.000 T_wg_cy<3> (T_wg_cy<3>)
MUXCY:CI->O 1 0.056 0.000 T_wg_cy<4> (T_wg_cy<4>)
MUXCY:CI->O 2 0.265 0.804 T_wg_cy<5> (T)
LUT3:I2->O 1 0.479 0.681 NaN1 (NaN_OBUF)
OBUF:I->O 4.909 NaN_OBUF (NaN)
----------------------------------------
Total 9.965ns (7.503ns logic, 2.461ns route)
(75.3% logic, 24.7% route)
=========================================================================
Total REAL time to Xst completion: 3.00 secs
Total CPU time to Xst completion: 3.06 secs
-->
Total memory usage is 605836 kilobytes
Number of errors : 0 ( 0 filtered)
Number of warnings : 1 ( 0 filtered)
Number of infos : 0 ( 0 filtered)

63
TypeCheck.twr Normal file
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--------------------------------------------------------------------------------
Release 14.7 Trace (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 5 -n
3 -fastpaths -xml TypeCheck.twx TypeCheck.ncd -o TypeCheck.twr TypeCheck.pcf
Design file: TypeCheck.ncd
Physical constraint file: TypeCheck.pcf
Device,package,speed: xc3s50,pq208,-5 (PRODUCTION 1.39 2013-10-13)
Report level: verbose report
Environment Variable Effect
-------------------- ------
NONE No environment variables were set
--------------------------------------------------------------------------------
INFO:Timing:2698 - No timing constraints found, doing default enumeration.
INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).
INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
option. All paths that are not constrained will be reported in the
unconstrained paths section(s) of the report.
INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
a 50 Ohm transmission line loading model. For the details of this model,
and for more information on accounting for different loading conditions,
please see the device datasheet.
INFO:Timing:3390 - This architecture does not support a default System Jitter
value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock
Uncertainty calculation.
INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and
'Phase Error' calculations, these terms will be zero in the Clock
Uncertainty calculation. Please make appropriate modification to
SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase
Error.
Data Sheet report:
-----------------
All values displayed in nanoseconds (ns)
Pad to Pad
---------------+---------------+---------+
Source Pad |Destination Pad| Delay |
---------------+---------------+---------+
N<0> |INF | 7.509|
N<0> |NaN | 7.466|
N<23> |INF | 7.017|
N<23> |NaN | 7.274|
---------------+---------------+---------+
Analysis completed Sat Aug 17 16:41:03 2019
--------------------------------------------------------------------------------
Trace Settings:
-------------------------
Trace Settings
Peak Memory Usage: 309 MB

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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE twReport [
<!ELEMENT twReport (twHead?, (twWarn | twDebug | twInfo)*, twBody, twSum?,
twDebug*, twFoot?, twClientInfo?)>
<!ATTLIST twReport version CDATA "10,4">
<!ELEMENT twHead (twExecVer?, twCopyright, twCmdLine?, twDesign?, twPCF?, twDevInfo, twRptInfo, twEnvVar*)>
<!ELEMENT twExecVer (#PCDATA)>
<!ELEMENT twCopyright (#PCDATA)>
<!ELEMENT twCmdLine (#PCDATA)>
<!ELEMENT twDesign (#PCDATA)>
<!ELEMENT twPCF (#PCDATA)>
<!ELEMENT twDevInfo (twDevName, twSpeedGrade, twSpeedVer?)>
<!ELEMENT twDevName (#PCDATA)>
<!ATTLIST twDevInfo arch CDATA #IMPLIED pkg CDATA #IMPLIED>
<!ELEMENT twSpeedGrade (#PCDATA)>
<!ELEMENT twSpeedVer (#PCDATA)>
<!ELEMENT twRptInfo (twItemLimit?, (twUnconst, twUnconstLimit?)?)>
<!ATTLIST twRptInfo twRptLvl (twErr | twVerbose | twTerseErr | twSum | twTimeGrp) #REQUIRED>
<!ATTLIST twRptInfo twAdvRpt (TRUE | FALSE) "FALSE">
<!ATTLIST twRptInfo twTimeUnits (twPsec | twNsec | twUsec | twMsec | twSec) "twNsec">
<!ATTLIST twRptInfo twFreqUnits (twGHz | twMHz | twHz) "twMHz">
<!ATTLIST twRptInfo twReportMinPaths CDATA #IMPLIED>
<!ELEMENT twItemLimit (#PCDATA)>
<!ELEMENT twUnconst EMPTY>
<!ELEMENT twUnconstLimit (#PCDATA)>
<!ELEMENT twEnvVar EMPTY>
<!ATTLIST twEnvVar name CDATA #REQUIRED>
<!ATTLIST twEnvVar description CDATA #REQUIRED>
<!ELEMENT twWarn (#PCDATA)>
<!ELEMENT twInfo (#PCDATA)>
<!ELEMENT twDebug (#PCDATA)>
<!ELEMENT twBody (twDerating?, (twSumRpt | twVerboseRpt | twErrRpt | twTerseErrRpt | twTimeGrpRpt), twNonDedClks?)>
<!ATTLIST twBody twFastPaths CDATA #IMPLIED>
<!ELEMENT twDerating (twProc?, twTemp?, twVolt?)>
<!ELEMENT twProc (#PCDATA)>
<!ELEMENT twTemp (#PCDATA)>
<!ELEMENT twVolt (#PCDATA)>
<!ELEMENT twSumRpt (twConstRollupTable*, twConstList?, twConstSummaryTable?, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?)>
<!ELEMENT twErrRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twTerseErrRpt (twConstList, twUnmetConstCnt?, twDataSheet?)>
<!ELEMENT twVerboseRpt (twCycles?, (twConst | twTIG | twConstRollupTable)*, twUnmetConstCnt?, (twWarn | twInfo | twDebug)*, twDataSheet?, twTimeGrp*)>
<!ELEMENT twCycles (twSigConn+)>
<!ATTLIST twCycles twNum CDATA #REQUIRED>
<!ELEMENT twSigConn (twSig, twDriver, twLoad)>
<!ELEMENT twSig (#PCDATA)>
<!ELEMENT twDriver (#PCDATA)>
<!ELEMENT twLoad (#PCDATA)>
<!ELEMENT twConst (twConstHead, ((twPathRpt?,twRacePathRpt?, twPathRptBanner?)* | (twPathRpt*, twRacePathRpt?) | twNetRpt* | twClkSkewLimit*))>
<!ATTLIST twConst twConstType (NET |
NETDELAY |
NETSKEW |
PATH |
DEFPERIOD |
UNCONSTPATH |
DEFPATH |
PATH2SETUP |
UNCONSTPATH2SETUP |
PATHCLASS |
PATHDELAY |
PERIOD |
FREQUENCY |
PATHBLOCK |
OFFSET |
OFFSETIN |
OFFSETINCLOCK |
UNCONSTOFFSETINCLOCK |
OFFSETINDELAY |
OFFSETINMOD |
OFFSETOUT |
OFFSETOUTCLOCK |
UNCONSTOFFSETOUTCLOCK |
OFFSETOUTDELAY |
OFFSETOUTMOD| CLOCK_SKEW_LIMITS) #IMPLIED>
<!ELEMENT twConstHead (twConstName, twItemCnt, twErrCntSetup, twErrCntEndPt?, twErrCntHold,
twEndPtCnt?,
twPathErrCnt?, (twMinPer| twMaxDel| twMaxFreq| twMaxNetDel| twMaxNetSkew| twMinOff| twMaxOff)*)>
<!ELEMENT twConstName (#PCDATA)>
<!ATTLIST twConstName UCFConstName CDATA #IMPLIED>
<!ATTLIST twConstHead uID CDATA #IMPLIED>
<!ELEMENT twItemCnt (#PCDATA)>
<!ELEMENT twErrCnt (#PCDATA)>
<!ELEMENT twErrCntEndPt (#PCDATA)>
<!ELEMENT twErrCntSetup (#PCDATA)>
<!ELEMENT twErrCntHold (#PCDATA)>
<!ATTLIST twErrCntHold twRaceChecked (TRUE | FALSE) "FALSE">
<!ELEMENT twEndPtCnt (#PCDATA)>
<!ELEMENT twPathErrCnt (#PCDATA)>
<!ELEMENT twMinPer (#PCDATA) >
<!ELEMENT twFootnote EMPTY>
<!ATTLIST twFootnote number CDATA #REQUIRED>
<!ELEMENT twMaxDel (#PCDATA)>
<!ELEMENT twMaxFreq (#PCDATA)>
<!ELEMENT twMinOff (#PCDATA)>
<!ELEMENT twMaxOff (#PCDATA)>
<!ELEMENT twTIG (twTIGHead, (twPathRpt*,twRacePathRpt?))>
<!ELEMENT twTIGHead (twTIGName, twInstantiated, twBlocked)>
<!ELEMENT twTIGName (#PCDATA)>
<!ELEMENT twInstantiated (#PCDATA)>
<!ELEMENT twBlocked (#PCDATA)>
<!ELEMENT twRacePathRpt (twRacePath+)>
<!ELEMENT twPathRpt (twUnconstPath | twConstPath | twUnconstOffIn | twConstOffIn | twUnconstOffOut | twConstOffOut | twModOffOut)>
<!ELEMENT twUnconstPath (twTotDel, twSrc, twDest, (twDel, twSUTime)?, twTotPathDel?, twClkSkew?, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twUnconstPath twDataPathType CDATA #IMPLIED
twSimpleMinPath CDATA #IMPLIED>
<!ELEMENT twTotDel (#PCDATA)>
<!ELEMENT twSrc (#PCDATA)>
<!ATTLIST twSrc BELType CDATA #IMPLIED>
<!ELEMENT twDest (#PCDATA)>
<!ATTLIST twDest BELType CDATA #IMPLIED>
<!ELEMENT twDel (#PCDATA)>
<!ELEMENT twSUTime (#PCDATA)>
<!ELEMENT twTotPathDel (#PCDATA)>
<!ELEMENT twClkSkew (#PCDATA)>
<!ATTLIST twClkSkew dest CDATA #IMPLIED src CDATA #IMPLIED>
<!ELEMENT twConstPath (twSlack, twSrc, twDest, twTotPathDel?, twClkSkew?, twDelConst, tw2Phase?, twClkUncert?, twDetPath?)>
<!ATTLIST twConstPath twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstPath constType (period | fromto | unknown) "unknown">
<!ELEMENT twSlack (#PCDATA)>
<!ELEMENT twDelConst (#PCDATA)>
<!ELEMENT tw2Phase EMPTY>
<!ELEMENT twClkUncert (#PCDATA)>
<!ATTLIST twClkUncert fSysJit CDATA #IMPLIED fInputJit CDATA #IMPLIED
fDCMJit CDATA #IMPLIED
fPhaseErr CDATA #IMPLIED
sEqu CDATA #IMPLIED>
<!ELEMENT twRacePath (twSlack, twSrc, twDest, twClkSkew, twDelConst?, twClkUncert?, twDetPath)>
<!ELEMENT twPathRptBanner (#PCDATA)>
<!ATTLIST twPathRptBanner sType CDATA #IMPLIED iPaths CDATA #IMPLIED iCriticalPaths CDATA #IMPLIED>
<!ELEMENT twUnconstOffIn (twOff, twSrc, twDest, twGuaranteed?, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twUnconstOffIn twDataPathType CDATA #IMPLIED>
<!ELEMENT twOff (#PCDATA)>
<!ELEMENT twGuaranteed EMPTY>
<!ELEMENT twConstOffIn (twSlack, twSrc, twDest, ((twClkDel, twClkSrc, twClkDest) | twGuarInSetup), twOff, twOffSrc, twOffDest, twClkUncert?, (twDataPath, twClkPath)?)>
<!ATTLIST twConstOffIn twDataPathType CDATA "twDataPathMaxDelay">
<!ATTLIST twConstOffIn twDurationNotSpecified CDATA #IMPLIED>
<!ELEMENT twClkDel (#PCDATA)>
<!ELEMENT twClkSrc (#PCDATA)>
<!ELEMENT twClkDest (#PCDATA)>
<!ELEMENT twGuarInSetup (#PCDATA)>
<!ELEMENT twOffSrc (#PCDATA)>
<!ELEMENT twOffDest (#PCDATA)>
<!ELEMENT twUnconstOffOut (twOff, twSrc, twDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twUnconstOffOut twDataPathType CDATA #IMPLIED>
<!ELEMENT twConstOffOut (twSlack, twSrc, twDest, twClkDel, twClkSrc, twClkDest, twDataDel, twDataSrc, twDataDest, twOff, twOffSrc, twOffDest, twClkUncert?, (twClkPath, twDataPath)?)>
<!ATTLIST twConstOffOut twDataPathType CDATA "twDataPathMaxDelay">
<!ELEMENT twDataDel (#PCDATA)>
<!ELEMENT twDataSrc (#PCDATA)>
<!ELEMENT twDataDest (#PCDATA)>
<!ELEMENT twModOffOut (twSlack, twDest, twDataDel, twDataSrc, twDataDest, twClkUncert?, twDataPath?)>
<!ELEMENT twDetPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDetPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twDataPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twDataPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twClkPath (twSrc, twDest, twLogLvls, twSrcSite, twSrcClk?, twPathDel*, (twLogDel, twRouteDel, twTotDel)?, twDestClk?, (twPctLog, twPctRoute)?)>
<!ATTLIST twClkPath maxSiteLen CDATA #IMPLIED>
<!ELEMENT twLogLvls (#PCDATA)>
<!ELEMENT twSrcSite (#PCDATA)>
<!ELEMENT twSrcClk (#PCDATA)>
<!ATTLIST twSrcClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twSrcClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twSrcClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPathDel (twSite, twDelType, twFanCnt?, twDelInfo?, twComp, twNet?, twBEL*)>
<!ATTLIST twPathDel twHoldTime (TRUE | FALSE) "FALSE">
<!ELEMENT twDelInfo (#PCDATA)>
<!ATTLIST twDelInfo twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ATTLIST twDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twSite (#PCDATA)>
<!ELEMENT twDelType (#PCDATA)>
<!ELEMENT twFanCnt (#PCDATA)>
<!ELEMENT twComp (#PCDATA)>
<!ELEMENT twNet (#PCDATA)>
<!ELEMENT twBEL (#PCDATA)>
<!ELEMENT twLogDel (#PCDATA)>
<!ELEMENT twRouteDel (#PCDATA)>
<!ELEMENT twDestClk (#PCDATA)>
<!ATTLIST twDestClk twEdge (twRising | twFalling) "twRising">
<!ATTLIST twDestClk twArriveTime CDATA #IMPLIED>
<!ATTLIST twDestClk twClkRes CDATA #IMPLIED>
<!ELEMENT twPctLog (#PCDATA)>
<!ELEMENT twPctRoute (#PCDATA)>
<!ELEMENT twNetRpt (twDelNet | twSlackNet | twSkewNet)>
<!ELEMENT twDelNet (twDel, twNet, twDetNet?)>
<!ELEMENT twSlackNet (twSlack, twNet, twDel, twNotMet?, twTimeConst, twAbsSlack, twDetNet?)>
<!ELEMENT twTimeConst (#PCDATA)>
<!ELEMENT twAbsSlack (#PCDATA)>
<!ELEMENT twSkewNet (twSlack, twNet, twSkew, twNotMet?, twTimeConst, twAbsSlack, twDetSkewNet?)>
<!ELEMENT twSkew (#PCDATA)>
<!ELEMENT twDetNet (twNetDel*)>
<!ELEMENT twNetDel (twSrc, twDest, twNetDelInfo)>
<!ELEMENT twNetDelInfo (#PCDATA)>
<!ATTLIST twNetDelInfo twAcc (twRouted | twEst | twApprox) "twRouted">
<!ELEMENT twDetSkewNet (twNetSkew*)>
<!ELEMENT twNetSkew (twSrc, twDest, twNetDelInfo, twSkew)>
<!ELEMENT twClkSkewLimit EMPTY>
<!ATTLIST twClkSkewLimit slack CDATA #IMPLIED skew CDATA #IMPLIED arrv1name CDATA #IMPLIED arrv1 CDATA #IMPLIED
arrv2name CDATA #IMPLIED arrv2 CDATA #IMPLIED uncert CDATA #IMPLIED>
<!ELEMENT twConstRollupTable (twConstRollup*)>
<!ATTLIST twConstRollupTable uID CDATA #IMPLIED>
<!ELEMENT twConstRollup EMPTY>
<!ATTLIST twConstRollup name CDATA #IMPLIED fullName CDATA #IMPLIED type CDATA #IMPLIED requirement CDATA #IMPLIED prefType CDATA #IMPLIED actual CDATA #IMPLIED>
<!ATTLIST twConstRollup actualRollup CDATA #IMPLIED errors CDATA #IMPLIED errorRollup CDATA #IMPLIED items CDATA #IMPLIED itemsRollup CDATA #IMPLIED>
<!ELEMENT twConstList (twConstListItem)*>
<!ELEMENT twConstListItem (twConstName, twNotMet?, twReqVal?, twActVal?, twLogLvls?)>
<!ATTLIST twConstListItem twUnits (twTime | twFreq) "twTime">
<!ELEMENT twNotMet EMPTY>
<!ELEMENT twReqVal (#PCDATA)>
<!ELEMENT twActVal (#PCDATA)>
<!ELEMENT twConstSummaryTable (twConstStats|twConstSummary)*>
<!ATTLIST twConstSummaryTable twEmptyConstraints CDATA #IMPLIED>
<!ELEMENT twConstStats (twConstName)>
<!ATTLIST twConstStats twUnits (twTime | twFreq) "twTime">
<!ATTLIST twConstStats twRequired CDATA #IMPLIED>
<!ATTLIST twConstStats twActual CDATA #IMPLIED>
<!ATTLIST twConstStats twSlack CDATA #IMPLIED>
<!ATTLIST twConstStats twLogLvls CDATA #IMPLIED>
<!ATTLIST twConstStats twErrors CDATA #IMPLIED>
<!ATTLIST twConstStats twPCFIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twAbsSlackIndex CDATA #IMPLIED>
<!ATTLIST twConstStats twTCType CDATA #IMPLIED>
<!ELEMENT twConstSummary (twConstName, twConstData?, twConstData*)>
<!ATTLIST twConstSummary PCFIndex CDATA #IMPLIED slackIndex CDATA #IMPLIED>
<!ELEMENT twConstData EMPTY>
<!ATTLIST twConstData type CDATA #IMPLIED units (MHz | ns) "ns" slack CDATA #IMPLIED
best CDATA #IMPLIED requested CDATA #IMPLIED
errors CDATA #IMPLIED
score CDATA #IMPLIED>
<!ELEMENT twTimeGrpRpt (twTimeGrp)*>
<!ELEMENT twTimeGrp (twTimeGrpName, twCompList?, twBELList?, twMacList?, twBlockList?, twSigList?, twPinList?)>
<!ELEMENT twTimeGrpName (#PCDATA)>
<!ELEMENT twCompList (twCompName+)>
<!ELEMENT twCompName (#PCDATA)>
<!ELEMENT twSigList (twSigName+)>
<!ELEMENT twSigName (#PCDATA)>
<!ELEMENT twBELList (twBELName+)>
<!ELEMENT twBELName (#PCDATA)>
<!ELEMENT twBlockList (twBlockName+)>
<!ELEMENT twBlockName (#PCDATA)>
<!ELEMENT twMacList (twMacName+)>
<!ELEMENT twMacName (#PCDATA)>
<!ELEMENT twPinList (twPinName+)>
<!ELEMENT twPinName (#PCDATA)>
<!ELEMENT twUnmetConstCnt (#PCDATA)>
<!ELEMENT twDataSheet (twSUH2ClkList*, (twClk2PadList|twClk2OutList)*, twClk2SUList*, twPad2PadList?, twOffsetTables?)>
<!ATTLIST twDataSheet twNameLen CDATA #REQUIRED>
<!ELEMENT twSUH2ClkList (twDest, twSUH2Clk+)>
<!ATTLIST twSUH2ClkList twDestWidth CDATA #IMPLIED>
<!ATTLIST twSUH2ClkList twPhaseWidth CDATA #IMPLIED>
<!ELEMENT twSUH2Clk (twSrc, twSUHTime, twSUHTime?)>
<!ELEMENT twSUHTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHTime twInternalClk CDATA #IMPLIED>
<!ATTLIST twSUHTime twClkPhase CDATA #IMPLIED>
<!ELEMENT twSU2ClkTime (#PCDATA)>
<!ATTLIST twSU2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twH2ClkTime (#PCDATA)>
<!ATTLIST twH2ClkTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2PadList (twSrc, twClk2Pad+)>
<!ELEMENT twClk2Pad (twDest, twTime)>
<!ELEMENT twTime (#PCDATA)>
<!ATTLIST twTime twEdge (twRising | twFalling | twIndet) #REQUIRED>
<!ELEMENT twClk2OutList (twSrc, twClk2Out+)>
<!ATTLIST twClk2OutList twDestWidth CDATA #REQUIRED>
<!ATTLIST twClk2OutList twPhaseWidth CDATA #REQUIRED>
<!ELEMENT twClk2Out EMPTY>
<!ATTLIST twClk2Out twOutPad CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMinEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxTime CDATA #REQUIRED>
<!ATTLIST twClk2Out twMaxEdge CDATA #REQUIRED>
<!ATTLIST twClk2Out twInternalClk CDATA #REQUIRED>
<!ATTLIST twClk2Out twClkPhase CDATA #REQUIRED>
<!ELEMENT twClk2SUList (twDest, twClk2SU+)>
<!ATTLIST twClk2SUList twDestWidth CDATA #IMPLIED>
<!ELEMENT twClk2SU (twSrc, twRiseRise?, twFallRise?, twRiseFall?, twFallFall?)>
<!ELEMENT twRiseRise (#PCDATA)>
<!ELEMENT twFallRise (#PCDATA)>
<!ELEMENT twRiseFall (#PCDATA)>
<!ELEMENT twFallFall (#PCDATA)>
<!ELEMENT twPad2PadList (twPad2Pad+)>
<!ATTLIST twPad2PadList twSrcWidth CDATA #IMPLIED>
<!ATTLIST twPad2PadList twDestWidth CDATA #IMPLIED>
<!ELEMENT twPad2Pad (twSrc, twDest, twDel)>
<!ELEMENT twOffsetTables (twOffsetInTable*,twOffsetOutTable*)>
<!ELEMENT twOffsetInTable (twConstName, twOffInTblRow*)>
<!ATTLIST twOffsetInTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstWindow CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetup CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHold CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstSetupSlack CDATA #IMPLIED>
<!ATTLIST twOffsetInTable twWorstHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffsetOutTable (twConstName, twOffOutTblRow*)>
<!ATTLIST twOffsetOutTable twDestWidth CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMinSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twMaxSlack CDATA #IMPLIED>
<!ATTLIST twOffsetOutTable twRelSkew CDATA #IMPLIED>
<!ELEMENT twOffInTblRow (twSrc, twSUHSlackTime*)>
<!ELEMENT twSUHSlackTime (twSU2ClkTime?,twH2ClkTime?)>
<!ATTLIST twSUHSlackTime twSetupSlack CDATA #IMPLIED twHoldSlack CDATA #IMPLIED>
<!ELEMENT twOffOutTblRow EMPTY>
<!ATTLIST twOffOutTblRow twOutPad CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twSlack CDATA #IMPLIED>
<!ATTLIST twOffOutTblRow twRelSkew CDATA #IMPLIED>
<!ELEMENT twNonDedClks ((twWarn | twInfo), twNonDedClk+)>
<!ELEMENT twNonDedClk (#PCDATA)>
<!ELEMENT twSum ( twErrCnt, twScore, twConstCov, twStats)>
<!ELEMENT twScore (#PCDATA)>
<!ELEMENT twConstCov (twPathCnt, twNetCnt, twConnCnt, twPct?)>
<!ELEMENT twPathCnt (#PCDATA)>
<!ELEMENT twNetCnt (#PCDATA)>
<!ELEMENT twConnCnt (#PCDATA)>
<!ELEMENT twPct (#PCDATA)>
<!ELEMENT twStats ( twMinPer?, twFootnote?, twMaxFreq?, twMaxCombDel?, twMaxFromToDel?, twMaxNetDel?, twMaxNetSkew?, twMaxInAfterClk?, twMinInBeforeClk?, twMaxOutBeforeClk?, twMinOutAfterClk?, (twInfo | twWarn)*)>
<!ELEMENT twMaxCombDel (#PCDATA)>
<!ELEMENT twMaxFromToDel (#PCDATA)>
<!ELEMENT twMaxNetDel (#PCDATA)>
<!ELEMENT twMaxNetSkew (#PCDATA)>
<!ELEMENT twMaxInAfterClk (#PCDATA)>
<!ELEMENT twMinInBeforeClk (#PCDATA)>
<!ELEMENT twMaxOutBeforeClk (#PCDATA)>
<!ELEMENT twMinOutAfterClk (#PCDATA)>
<!ELEMENT twFoot (twFootnoteExplanation*, twTimestamp)>
<!ELEMENT twTimestamp (#PCDATA)>
<!ELEMENT twFootnoteExplanation EMPTY>
<!ATTLIST twFootnoteExplanation number CDATA #REQUIRED>
<!ATTLIST twFootnoteExplanation text CDATA #REQUIRED>
<!ELEMENT twClientInfo (twClientName, twAttrList?)>
<!ELEMENT twClientName (#PCDATA)>
<!ELEMENT twAttrList (twAttrListItem)*>
<!ELEMENT twAttrListItem (twName, twValue*)>
<!ELEMENT twName (#PCDATA)>
<!ELEMENT twValue (#PCDATA)>
]>
<twReport><twHead anchorID="1"><twExecVer>Release 14.7 Trace (lin64)</twExecVer><twCopyright>Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.</twCopyright><twCmdLine>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 5 -n
3 -fastpaths -xml TypeCheck.twx TypeCheck.ncd -o TypeCheck.twr TypeCheck.pcf
</twCmdLine><twDesign>TypeCheck.ncd</twDesign><twDesignPath>TypeCheck.ncd</twDesignPath><twPCF>TypeCheck.pcf</twPCF><twPcfPath>TypeCheck.pcf</twPcfPath><twDevInfo arch="spartan3" pkg="pq208"><twDevName>xc3s50</twDevName><twSpeedGrade>-5</twSpeedGrade><twSpeedVer>PRODUCTION 1.39 2013-10-13</twSpeedVer></twDevInfo><twRptInfo twRptLvl="twVerbose" twReportMinPaths="true" dlyHyperLnks="t" ><twEndptLimit>3</twEndptLimit></twRptInfo><twEnvVar name="NONE" description="No environment variables were set" /></twHead><twInfo anchorID="2">INFO:Timing:2698 - No timing constraints found, doing default enumeration.</twInfo><twInfo anchorID="3">INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).</twInfo><twInfo anchorID="4">INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</twInfo><twInfo anchorID="5">INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</twInfo><twInfo anchorID="6">INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</twInfo><twInfo anchorID="7">INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</twInfo><twBody><twVerboseRpt><twDataSheet anchorID="8" twNameLen="15"><twPad2PadList anchorID="9" twSrcWidth="5" twDestWidth="3"><twPad2Pad><twSrc>N&lt;0&gt;</twSrc><twDest>INF</twDest><twDel>7.509</twDel></twPad2Pad><twPad2Pad><twSrc>N&lt;0&gt;</twSrc><twDest>NaN</twDest><twDel>7.466</twDel></twPad2Pad><twPad2Pad><twSrc>N&lt;23&gt;</twSrc><twDest>INF</twDest><twDel>7.017</twDel></twPad2Pad><twPad2Pad><twSrc>N&lt;23&gt;</twSrc><twDest>NaN</twDest><twDel>7.274</twDel></twPad2Pad></twPad2PadList><twOffsetTables></twOffsetTables></twDataSheet></twVerboseRpt></twBody><twFoot><twTimestamp>Sat Aug 17 16:41:03 2019 </twTimestamp></twFoot><twClientInfo anchorID="10"><twClientName>Trace</twClientName><twAttrList><twAttrListItem><twName>Trace Settings</twName><twValue>
Peak Memory Usage: 309 MB
</twValue></twAttrListItem></twAttrList></twClientInfo></twReport>

9
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Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sat Aug 17 16:41:02 2019
All signals are completely routed.

3
TypeCheck.xpi Normal file
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PROGRAM=PAR
STATE=ROUTED
TIMESPECS_MET=OFF

56
TypeCheck.xst Normal file
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set -tmpdir "xst/projnav.tmp"
set -xsthdpdir "xst"
run
-ifn TypeCheck.prj
-ifmt mixed
-ofn TypeCheck
-ofmt NGC
-p xc3s50-5-pq208
-top TypeCheck
-opt_mode Speed
-opt_level 1
-iuc NO
-keep_hierarchy No
-netlist_hierarchy As_Optimized
-rtlview Yes
-glob_opt AllClockNets
-read_cores YES
-write_timing_constraints NO
-cross_clock_analysis NO
-hierarchy_separator /
-bus_delimiter <>
-case Maintain
-slice_utilization_ratio 100
-bram_utilization_ratio 100
-verilog2001 YES
-fsm_extract YES -fsm_encoding Auto
-safe_implementation No
-fsm_style LUT
-ram_extract Yes
-ram_style Auto
-rom_extract Yes
-mux_style Auto
-decoder_extract YES
-priority_extract Yes
-shreg_extract YES
-shift_extract YES
-xor_collapse YES
-rom_style Auto
-auto_bram_packing NO
-mux_extract Yes
-resource_sharing YES
-async_to_sync NO
-mult_style Auto
-iobuf YES
-max_fanout 500
-bufg 8
-register_duplication YES
-register_balancing No
-slice_packing YES
-optimize_primitives NO
-use_clock_enable Yes
-use_sync_set Yes
-use_sync_reset Yes
-iob Auto
-equivalent_register_removal YES
-slice_utilization_ratio_maxmargin 5

3
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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
###3168:XlxV32DM 18c0 c48eNqNV2t32joW/St84MPM3JXEkizZsm67QsChXgVDwUnT+6Fexo+WmQby6H10Eea3zzmSbWxDbidZSDpbR0dbW9IR9JNiRyzVX+R/rJ/X243XI+d2r0/VGYdPyuBzL9XZevP9+fuPb7lDDu3e+jnvnT30/krZM7fOHh6p5Z7xHgzoJU950jtbP/W2RQEuZZ32iGX1zra96MdDPvyap/+J75OH802aHZDzzZem9ZAWPeCwfoJi+w2Khyeg9d3O1NmfvQ6T7bfe1/WXr72z7z3y91Ok3SmEupgPRoSWNStru6x5pi6Wk2Dox3eEfGIkrU0JFlOwLKbYOcGCgpqMekE4v4m88FdGPOstVQMCH+y6ugkmozgaLMY+FMN3LiDLOAivZ6m6yr8996xzBvRnuba8YHYFnVc318XBnt1EAKQHAChmxtKsJvF12xzDvMPBKL4N/I/xrb9YBrNQquFsOg2iyB85arjwB9DI1HB7/1BTkMbEKdKyaQISNaLqGlZ0TYkaUzWG5pi6ahw/JCA4qVvQHVAVhAw+1zYW0AdlPIMFSAWBL/TiEt0063J0G5Yk1GQ2GPmwG2o6mMfD6WgShH48m0dAf5locDob3Uz8TLejYOovo8F0vtJmuU4YnDzYKvzVesuhJGVFTEVNxUxlm4qbSpjKMZVrKvkWY5nR1MSipWViUROLmljUxKImFjWxqIlFTSwzjFlvHVWeFm0T3cl0aeuS61Lo0tGlq0uJI/3o42zx3lVhbMWBFjeMKdNNpsIktLEA8aHU4lM1A11B8UTNz6lFGLHw1M8Hw/f+iCl9CaBcdGUnXM1Hy/hqMhu+j8fhKL4KwlEQjok8jccL/xoj1X3zyWDoT/0wKhrgzXIw9luhb4fDk6EbuA7dHYNTT8cLstL4aBZGsTnc8U14s/RH8TwIl2Zq0CxegAIQKq2B6NPcT4w1HsXByLjOR9PqPMFR10gQxoPlMhiHMRy2kgaC/l3kh3BqdSRiAut71xTl1h9q9uTQjdMtP4XD5pDmYqshvNFtGMWYRkqNW/gC7hVSggQTjO5WVTscTH1iq/n7eOTrBYTjabyc3SyGfoEomPVVcpW58RdwoKqWXYPjGsRNqpr00LRXqspIF4ODMb4YkKZBm4ZNVJSrqN5V1LHQdklXC2t3EThD/gI2x8C3mJzxMMO5KtrYIspawBSSY8Nezn1IOQZCwYLpHKgFkYkStQ5CVCmuCUyCq6WrojoHli2Qo35rYMM779KXe6LuSKbuArhld2d3oyvIvqS3jG5MY7AcBoFQd9kqDjKgdZfdx9Pk39un2/wJn+sKWm8OkPrkqHhjwR8pGwT0wifZUel99m29yW2FLyVT8G4yBW8zUw/JE1f6CXfVMxjfkw3kA/O000K9jBbBLdyjaHE1u/MIvG+zypjcDqezJeXwOPgfoZh9fHmBY/py7PHykqqXl9GbfwzIvwb0ny9Zbf0XzbrzF7QYWC/7y8sHmarLy7+k8K494ZHdkhKPJZ6wPcJsIgTxKKOrZLeRK4+ojUw9ofoy8aRU+yW1TvjCaWPcS7hnNeGcK3T/f2HxGpwBU8BeZ6r67spzU9Unjgc7smGuxzPuElJI1Wca6zMJw1TfyTzpqD8iwU1IL3k9qKSwLeqD48LM+w8OSrXvOwzcYKYC+/puoYO7uZe4UGVeglJZKJuTVyQS9cNJPJa7UEtdT5jwxK6fEI+rPsxCgJ+XwHdG20sguPASoOpiuX/nOOo3yTy6o+Aovf07UaiJcDymxwNNWB+FXYI59yutFDhChN2jyNSjkOqdyNVvBBdBbG+/5QW4vJNE/e5wj1pKbWkXWXMbkL6TepzBQlaexmgbI4hZbYwCZhdtjCGWtzEbsayNccTSNiYQW7UxB7GkjbmqRd+W7W6JmNvGEsScNrZCjLexFLGOHBlirI3liHUkKhAjHdk0wY5uBMVkHeEIqsk6yhGUk3WkI6gn62hHUFDeEY+goryjHkFJeUczSLcAdkQjqCTvqEZQSi46IGrJO1oSFJN3BdFqdoejnKxLvmht80r3U/zf9d0Ebi3cnAQ2Z0tRH/WLwKBqxTPtBpLvsJ/BZXEopjQYA9zXFCVWW4EbCldIRyUHd1u7wz0TcGgSMyqtgu+ftTvbvYFZaK7egCmE+gyf/bOZWHcJpj7TTO33K33Zjkiv1FrQJmn82tokzTQL17DIDYvVEXcd/Ii7NKPkEXftDtxhMiD4Bsyau5lfd8GyPguK3PW1O+KeHgmenxKcvya4jnpEevWa4NodBc+14GAeBM9LwfOG4Pyk4HlXcHFScOcngvOTgqevCc5LwYURnDcEF6Xgoim43gUBtIThbmvukELW1FwY23Mxn1C8klDJCsSEQJPKgkSyla4mLjNzvDABsZq3U2jetuGdGt6ZWhNehcBkQvQqtpSbtcu8FcMlOgY1MVYmRt6M4VYxtCVUHareOAgJGeozTfBwrg4YB0wiltYYBUzCBj+7sjyplhnroJ97wHBs60RbZqyLAouTAhc/1Zf9RF9xUl/W0uan+han9CUmRnZCX+d1fctMBCFrfaV9wCp9Ja+xI33FCX1FQ9/6ADf0NQee7j7zojrtZdYBDL4DlymnvNSA2Ul1o8vMChhbVWn1sBCw4Xbry5I09hbDUYVJC6evjxVERG9WeldMufEWpbdelG1SnjDe0sQqZxKVGqWTY+CykiYS5pyNq7+G7UzK/t2BXgWgU4PyALo1KA6grEHnAJq8Z86AAW8c4EJ3zGbJyiqyAv6I61j6dwr5ezu3ihTtXAp5yqbS+OeWsE/ZjlXkTRsXvaoJ8gZBCgQpSwoL/uGPu4LrCVe5NIREccpmpX9qGRsnSOsJ2LEC1YDMFTkOkEQTfNUWlrGrFXftRJZ2ucKuXS2oqUBWE7SPFagkqxQoSsmzcsKuXW2paxnCOAEeaL4zefYwgQMTOCzJsoLjAFiL09yzxG2voLKrFXT7i05/ZXfjVQvqxnPKBXbn6/J7bb5qfNcfBShqAaxjAeA51gNIRwDZWUDeWUDeEUB2CHXHy874yu7O341X+VcL7Pq/xr/it8e/y8vhDn6MuwkTae7YYF/t6E6k5osI/OLL1X4n3KYJPvPdB7ielvoAfkQ9EguNR0K0JfHJe5T4gwVc/wfWHr9z

61
TypeCheck_map.map Normal file
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Release 14.7 Map P.20131013 (lin64)
Xilinx Map Application Log File for Design 'TypeCheck'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s50-pq208-5 -cm area -ir off -pr off -c
100 -o TypeCheck_map.ncd TypeCheck.ngd TypeCheck.pcf
Target Device : xc3s50
Target Package : pq208
Target Speed : -5
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Sat Aug 17 16:40:57 2019
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Updating timing models...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of 4 input LUTs: 4 out of 1,536 1%
Logic Distribution:
Number of occupied Slices: 2 out of 768 1%
Number of Slices containing only related logic: 2 out of 2 100%
Number of Slices containing unrelated logic: 0 out of 2 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 4 out of 1,536 1%
Number of bonded IOBs: 4 out of 124 3%
Average Fanout of Non-Clock Nets: 1.67
Peak Memory Usage: 615 MB
Total REAL time to MAP completion: 1 secs
Total CPU time to MAP completion: 1 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "TypeCheck_map.mrp" for details.

147
TypeCheck_map.mrp Normal file
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Release 14.7 Map P.20131013 (lin64)
Xilinx Mapping Report File for Design 'TypeCheck'
Design Information
------------------
Command Line : map -intstyle ise -p xc3s50-pq208-5 -cm area -ir off -pr off -c
100 -o TypeCheck_map.ncd TypeCheck.ngd TypeCheck.pcf
Target Device : xc3s50
Target Package : pq208
Target Speed : -5
Mapper Version : spartan3 -- $Revision: 1.55 $
Mapped Date : Sat Aug 17 16:40:57 2019
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of 4 input LUTs: 4 out of 1,536 1%
Logic Distribution:
Number of occupied Slices: 2 out of 768 1%
Number of Slices containing only related logic: 2 out of 2 100%
Number of Slices containing unrelated logic: 0 out of 2 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 4 out of 1,536 1%
Number of bonded IOBs: 4 out of 124 3%
Average Fanout of Non-Clock Nets: 1.67
Peak Memory Usage: 615 MB
Total REAL time to MAP completion: 1 secs
Total CPU time to MAP completion: 1 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Timing Report
Section 11 - Configuration String Information
Section 12 - Control Set Information
Section 13 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
Section 3 - Informational
-------------------------
INFO:LIT:243 - Logical network N<31> has no load.
INFO:LIT:395 - The above info message is repeated 29 more times for the
following (max. 5 shown):
N<30>,
N<29>,
N<28>,
N<27>,
N<26>
To see the details of these info messages, please use the -detail switch.
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
rate limited output drivers. The delay on speed critical single ended outputs
can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
Section 5 - Removed Logic
-------------------------
Section 6 - IOB Properties
--------------------------
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Term | Strength | Rate | | | Delay |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
| INF | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
| N<0> | IOB | INPUT | LVCMOS25 | | | | | | |
| N<23> | IOB | INPUT | LVCMOS25 | | | | | | |
| NaN | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Timing Report
--------------------------
This design was not run using timing mode.
Section 11 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 12 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 13 - Utilization by Hierarchy
-------------------------------------
Use the "-detail" map option to print out the Utilization by Hierarchy section.

3
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XILINX-XDB 0.1 STUB 0.1 ASCII
XILINX-XDM V1.6
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TypeCheck_map.ngm Normal file
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The structure and the elements are likely to change over the next few releases.
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TypeCheck_ngdbuild.xrpt Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
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The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
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TypeCheck_pad.csv Normal file
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#Release 14.7 - par P.20131013 (lin64)
#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
#Sat Aug 17 16:41:02 2019
#
## NOTE: This file is designed to be imported into a spreadsheet program
# such as Microsoft Excel for viewing, printing and sorting. The |
# character is used as the data field separator. This file is also designed
# to support parsing.
#
#INPUT FILE: TypeCheck_map.ncd
#OUTPUT FILE: TypeCheck_pad.csv
#PART TYPE: xc3s50
#SPEED GRADE: -5
#PACKAGE: pq208
#
# Pinout by Pin Number:
#
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
P1,,,GND,,,,,,,,,,,,
P2,,DIFFM,IO_L01P_7/VRN_7,UNUSED,,7,,,,,,,,,
P3,,DIFFS,IO_L01N_7/VRP_7,UNUSED,,7,,,,,,,,,
P4,,,NC,,,,,,,,,,,,
P5,,,NC,,,,,,,,,,,,
P6,,,VCCO_7,,,7,,,,,any******,,,,
P7,,DIFFM,IO_L19P_7,UNUSED,,7,,,,,,,,,
P8,,,GND,,,,,,,,,,,,
P9,,DIFFS,IO_L19N_7/VREF_7,UNUSED,,7,,,,,,,,,
P10,,DIFFM,IO_L20P_7,UNUSED,,7,,,,,,,,,
P11,,DIFFS,IO_L20N_7,UNUSED,,7,,,,,,,,,
P12,,DIFFM,IO_L21P_7,UNUSED,,7,,,,,,,,,
P13,,DIFFS,IO_L21N_7,UNUSED,,7,,,,,,,,,
P14,,,GND,,,,,,,,,,,,
P15,,DIFFM,IO_L22P_7,UNUSED,,7,,,,,,,,,
P16,,DIFFS,IO_L22N_7,UNUSED,,7,,,,,,,,,
P17,,,VCCAUX,,,,,,,,2.5,,,,
P18,,DIFFM,IO_L23P_7,UNUSED,,7,,,,,,,,,
P19,,DIFFS,IO_L23N_7,UNUSED,,7,,,,,,,,,
P20,,DIFFM,IO_L24P_7,UNUSED,,7,,,,,,,,,
P21,,DIFFS,IO_L24N_7,UNUSED,,7,,,,,,,,,
P22,,,NC,,,,,,,,,,,,
P23,,,VCCO_7,,,7,,,,,any******,,,,
P24,,,NC,,,,,,,,,,,,
P25,,,GND,,,,,,,,,,,,
P26,,DIFFM,IO_L40P_7,UNUSED,,7,,,,,,,,,
P27,,DIFFS,IO_L40N_7/VREF_7,UNUSED,,7,,,,,,,,,
P28,,DIFFM,IO_L40P_6/VREF_6,UNUSED,,6,,,,,,,,,
P29,,DIFFS,IO_L40N_6,UNUSED,,6,,,,,,,,,
P30,,,GND,,,,,,,,,,,,
P31,,,NC,,,,,,,,,,,,
P32,,,VCCO_6,,,6,,,,,any******,,,,
P33,,,NC,,,,,,,,,,,,
P34,,DIFFM,IO_L24P_6,UNUSED,,6,,,,,,,,,
P35,,DIFFS,IO_L24N_6/VREF_6,UNUSED,,6,,,,,,,,,
P36,,DIFFM,IO_L23P_6,UNUSED,,6,,,,,,,,,
P37,,DIFFS,IO_L23N_6,UNUSED,,6,,,,,,,,,
P38,,,VCCAUX,,,,,,,,2.5,,,,
P39,,DIFFM,IO_L22P_6,UNUSED,,6,,,,,,,,,
P40,,DIFFS,IO_L22N_6,UNUSED,,6,,,,,,,,,
P41,,,GND,,,,,,,,,,,,
P42,,DIFFM,IO_L21P_6,UNUSED,,6,,,,,,,,,
P43,,DIFFS,IO_L21N_6,UNUSED,,6,,,,,,,,,
P44,,DIFFM,IO_L20P_6,UNUSED,,6,,,,,,,,,
P45,,DIFFS,IO_L20N_6,UNUSED,,6,,,,,,,,,
P46,,DIFFM,IO_L19P_6,UNUSED,,6,,,,,,,,,
P47,,,GND,,,,,,,,,,,,
P48,,DIFFS,IO_L19N_6,UNUSED,,6,,,,,,,,,
P49,,,VCCO_6,,,6,,,,,any******,,,,
P50,,,NC,,,,,,,,,,,,
P51,,DIFFM,IO_L01P_6/VRN_6,UNUSED,,6,,,,,,,,,
P52,,DIFFS,IO_L01N_6/VRP_6,UNUSED,,6,,,,,,,,,
P53,,,GND,,,,,,,,,,,,
P54,,,M1,,,,,,,,,,,,
P55,,,M0,,,,,,,,,,,,
P56,,,M2,,,,,,,,,,,,
P57,,DIFFM,IO_L01P_5/CS_B,UNUSED,,5,,,,,,,,,
P58,,DIFFS,IO_L01N_5/RDWR_B,UNUSED,,5,,,,,,,,,
P59,,,GND,,,,,,,,,,,,
P60,,,VCCO_5,,,5,,,,,any******,,,,
P61,,DIFFM,IO_L10P_5/VRN_5,UNUSED,,5,,,,,,,,,
P62,,DIFFS,IO_L10N_5/VRP_5,UNUSED,,5,,,,,,,,,
P63,,IOB,IO,UNUSED,,5,,,,,,,,,
P64,,DIFFM,IO_L27P_5,UNUSED,,5,,,,,,,,,
P65,,DIFFS,IO_L27N_5/VREF_5,UNUSED,,5,,,,,,,,,
P66,,,GND,,,,,,,,,,,,
P67,,DIFFM,IO_L28P_5/D7,UNUSED,,5,,,,,,,,,
P68,,DIFFS,IO_L28N_5/D6,UNUSED,,5,,,,,,,,,
P69,,,VCCAUX,,,,,,,,2.5,,,,
P70,,,VCCINT,,,,,,,,1.2,,,,
P71,,IOB,IO,UNUSED,,5,,,,,,,,,
P72,,DIFFM,IO_L31P_5/D5,UNUSED,,5,,,,,,,,,
P73,,,VCCO_5,,,5,,,,,any******,,,,
P74,,DIFFS,IO_L31N_5/D4,UNUSED,,5,,,,,,,,,
P75,,,GND,,,,,,,,,,,,
P76,,DIFFM,IO_L32P_5/GCLK2,UNUSED,,5,,,,,,,,,
P77,,DIFFS,IO_L32N_5/GCLK3,UNUSED,,5,,,,,,,,,
P78,,IOB,IO/VREF_5,UNUSED,,5,,,,,,,,,
P79,,DIFFM,IO_L32P_4/GCLK0,UNUSED,,4,,,,,,,,,
P80,,DIFFS,IO_L32N_4/GCLK1,UNUSED,,4,,,,,,,,,
P81,,DIFFM,IO_L31P_4/DOUT/BUSY,UNUSED,,4,,,,,,,,,
P82,,,GND,,,,,,,,,,,,
P83,,DIFFS,IO_L31N_4/INIT_B,UNUSED,,4,,,,,,,,,
P84,,,VCCO_4,,,4,,,,,any******,,,,
P85,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,
P86,,DIFFM,IO_L30P_4/D3,UNUSED,,4,,,,,,,,,
P87,,DIFFS,IO_L30N_4/D2,UNUSED,,4,,,,,,,,,
P88,,,VCCINT,,,,,,,,1.2,,,,
P89,,,VCCAUX,,,,,,,,2.5,,,,
P90,,DIFFM,IO_L27P_4/D1,UNUSED,,4,,,,,,,,,
P91,,,GND,,,,,,,,,,,,
P92,,DIFFS,IO_L27N_4/DIN/D0,UNUSED,,4,,,,,,,,,
P93,,IOB,IO,UNUSED,,4,,,,,,,,,
P94,,DIFFM,IO_L25P_4,UNUSED,,4,,,,,,,,,
P95,,DIFFS,IO_L25N_4,UNUSED,,4,,,,,,,,,
P96,,,NC,,,,,,,,,,,,
P97,,,NC,,,,,,,,,,,,
P98,,,VCCO_4,,,4,,,,,any******,,,,
P99,,,GND,,,,,,,,,,,,
P100,,DIFFM,IO_L01P_4/VRN_4,UNUSED,,4,,,,,,,,,
P101,,DIFFS,IO_L01N_4/VRP_4,UNUSED,,4,,,,,,,,,
P102,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,
P103,,,DONE,,,,,,,,,,,,
P104,,,CCLK,,,,,,,,,,,,
P105,,,GND,,,,,,,,,,,,
P106,,DIFFM,IO_L01P_3/VRN_3,UNUSED,,3,,,,,,,,,
P107,,DIFFS,IO_L01N_3/VRP_3,UNUSED,,3,,,,,,,,,
P108,,,NC,,,,,,,,,,,,
P109,,,NC,,,,,,,,,,,,
P110,,,VCCO_3,,,3,,,,,any******,,,,
P111,,DIFFM,IO_L19P_3,UNUSED,,3,,,,,,,,,
P112,,,GND,,,,,,,,,,,,
P113,,DIFFS,IO_L19N_3,UNUSED,,3,,,,,,,,,
P114,,DIFFM,IO_L20P_3,UNUSED,,3,,,,,,,,,
P115,,DIFFS,IO_L20N_3,UNUSED,,3,,,,,,,,,
P116,,DIFFM,IO_L21P_3,UNUSED,,3,,,,,,,,,
P117,,DIFFS,IO_L21N_3,UNUSED,,3,,,,,,,,,
P118,,,GND,,,,,,,,,,,,
P119,,DIFFM,IO_L22P_3,UNUSED,,3,,,,,,,,,
P120,,DIFFS,IO_L22N_3,UNUSED,,3,,,,,,,,,
P121,,,VCCAUX,,,,,,,,2.5,,,,
P122,,DIFFM,IO_L23P_3/VREF_3,UNUSED,,3,,,,,,,,,
P123,,DIFFS,IO_L23N_3,UNUSED,,3,,,,,,,,,
P124,,DIFFM,IO_L24P_3,UNUSED,,3,,,,,,,,,
P125,,DIFFS,IO_L24N_3,UNUSED,,3,,,,,,,,,
P126,,,NC,,,,,,,,,,,,
P127,,,VCCO_3,,,3,,,,,any******,,,,
P128,,,NC,,,,,,,,,,,,
P129,,,GND,,,,,,,,,,,,
P130,,DIFFM,IO_L40P_3,UNUSED,,3,,,,,,,,,
P131,,DIFFS,IO_L40N_3/VREF_3,UNUSED,,3,,,,,,,,,
P132,,DIFFM,IO_L40P_2/VREF_2,UNUSED,,2,,,,,,,,,
P133,,DIFFS,IO_L40N_2,UNUSED,,2,,,,,,,,,
P134,,,GND,,,,,,,,,,,,
P135,,,NC,,,,,,,,,,,,
P136,,,VCCO_2,,,2,,,,,any******,,,,
P137,,,NC,,,,,,,,,,,,
P138,,DIFFM,IO_L24P_2,UNUSED,,2,,,,,,,,,
P139,,DIFFS,IO_L24N_2,UNUSED,,2,,,,,,,,,
P140,,DIFFM,IO_L23P_2,UNUSED,,2,,,,,,,,,
P141,,DIFFS,IO_L23N_2/VREF_2,UNUSED,,2,,,,,,,,,
P142,,,VCCAUX,,,,,,,,2.5,,,,
P143,,DIFFM,IO_L22P_2,UNUSED,,2,,,,,,,,,
P144,,DIFFS,IO_L22N_2,UNUSED,,2,,,,,,,,,
P145,,,GND,,,,,,,,,,,,
P146,,DIFFM,IO_L21P_2,UNUSED,,2,,,,,,,,,
P147,,DIFFS,IO_L21N_2,UNUSED,,2,,,,,,,,,
P148,,DIFFM,IO_L20P_2,UNUSED,,2,,,,,,,,,
P149,,DIFFS,IO_L20N_2,UNUSED,,2,,,,,,,,,
P150,,DIFFM,IO_L19P_2,UNUSED,,2,,,,,,,,,
P151,,,GND,,,,,,,,,,,,
P152,,DIFFS,IO_L19N_2,UNUSED,,2,,,,,,,,,
P153,,,VCCO_2,,,2,,,,,any******,,,,
P154,,,NC,,,,,,,,,,,,
P155,,DIFFM,IO_L01P_2/VRN_2,UNUSED,,2,,,,,,,,,
P156,,DIFFS,IO_L01N_2/VRP_2,UNUSED,,2,,,,,,,,,
P157,,,GND,,,,,,,,,,,,
P158,,,TDO,,,,,,,,,,,,
P159,,,TCK,,,,,,,,,,,,
P160,,,TMS,,,,,,,,,,,,
P161,,DIFFM,IO_L01P_1/VRN_1,UNUSED,,1,,,,,,,,,
P162,,DIFFS,IO_L01N_1/VRP_1,UNUSED,,1,,,,,,,,,
P163,,,GND,,,,,,,,,,,,
P164,,,VCCO_1,,,1,,,,,any******,,,,
P165,,DIFFM,IO_L10P_1,UNUSED,,1,,,,,,,,,
P166,,DIFFS,IO_L10N_1/VREF_1,UNUSED,,1,,,,,,,,,
P167,,IOB,IO,UNUSED,,1,,,,,,,,,
P168,,DIFFM,IO_L27P_1,UNUSED,,1,,,,,,,,,
P169,,DIFFS,IO_L27N_1,UNUSED,,1,,,,,,,,,
P170,,,GND,,,,,,,,,,,,
P171,,DIFFM,IO_L28P_1,UNUSED,,1,,,,,,,,,
P172,,DIFFS,IO_L28N_1,UNUSED,,1,,,,,,,,,
P173,,,VCCAUX,,,,,,,,2.5,,,,
P174,,,VCCINT,,,,,,,,1.2,,,,
P175,,IOB,IO,UNUSED,,1,,,,,,,,,
P176,,DIFFM,IO_L31P_1,UNUSED,,1,,,,,,,,,
P177,,,VCCO_1,,,1,,,,,any******,,,,
P178,,DIFFS,IO_L31N_1/VREF_1,UNUSED,,1,,,,,,,,,
P179,,,GND,,,,,,,,,,,,
P180,,DIFFM,IO_L32P_1/GCLK4,UNUSED,,1,,,,,,,,,
P181,,DIFFS,IO_L32N_1/GCLK5,UNUSED,,1,,,,,,,,,
P182,,IOB,IO,UNUSED,,1,,,,,,,,,
P183,NaN,IOB,IO_L32P_0/GCLK6,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P184,N<0>,IOB,IO_L32N_0/GCLK7,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
P185,N<23>,IOB,IO_L31P_0/VREF_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
P186,,,GND,,,,,,,,,,,,
P187,INF,IOB,IO_L31N_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
P188,,,VCCO_0,,,0,,,,,2.50,,,,
P189,,IOB,IO,UNUSED,,0,,,,,,,,,
P190,,DIFFM,IO_L30P_0,UNUSED,,0,,,,,,,,,
P191,,DIFFS,IO_L30N_0,UNUSED,,0,,,,,,,,,
P192,,,VCCINT,,,,,,,,1.2,,,,
P193,,,VCCAUX,,,,,,,,2.5,,,,
P194,,DIFFM,IO_L27P_0,UNUSED,,0,,,,,,,,,
P195,,,GND,,,,,,,,,,,,
P196,,DIFFS,IO_L27N_0,UNUSED,,0,,,,,,,,,
P197,,IOB,IO,UNUSED,,0,,,,,,,,,
P198,,DIFFM,IO_L25P_0,UNUSED,,0,,,,,,,,,
P199,,DIFFS,IO_L25N_0,UNUSED,,0,,,,,,,,,
P200,,,NC,,,,,,,,,,,,
P201,,,VCCO_0,,,0,,,,,2.50,,,,
P202,,,GND,,,,,,,,,,,,
P203,,DIFFM,IO_L01P_0/VRN_0,UNUSED,,0,,,,,,,,,
P204,,DIFFS,IO_L01N_0/VRP_0,UNUSED,,0,,,,,,,,,
P205,,IOB,IO/VREF_0,UNUSED,,0,,,,,,,,,
P206,,,HSWAP_EN,,,,,,,,,,,,
P207,,,PROG_B,,,,,,,,,,,,
P208,,,TDI,,,,,,,,,,,,
# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
#
#* Default value.
#** This default Pullup/Pulldown value can be overridden in Bitgen.
#****** Special VCCO requirements may apply. Please consult the device
# family datasheet for specific guideline on VCCO requirements.
#
#
#
1 #Release 14.7 - par P.20131013 (lin64)
2 #Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
3 #Sat Aug 17 16:41:02 2019
4 #
5 ## NOTE: This file is designed to be imported into a spreadsheet program
6 # such as Microsoft Excel for viewing, printing and sorting. The |
7 # character is used as the data field separator. This file is also designed
8 # to support parsing.
9 #
10 #INPUT FILE: TypeCheck_map.ncd
11 #OUTPUT FILE: TypeCheck_pad.csv
12 #PART TYPE: xc3s50
13 #SPEED GRADE: -5
14 #PACKAGE: pq208
15 #
16 # Pinout by Pin Number:
17 #
18 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
19 Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity,
20 P1,,,GND,,,,,,,,,,,,
21 P2,,DIFFM,IO_L01P_7/VRN_7,UNUSED,,7,,,,,,,,,
22 P3,,DIFFS,IO_L01N_7/VRP_7,UNUSED,,7,,,,,,,,,
23 P4,,,NC,,,,,,,,,,,,
24 P5,,,NC,,,,,,,,,,,,
25 P6,,,VCCO_7,,,7,,,,,any******,,,,
26 P7,,DIFFM,IO_L19P_7,UNUSED,,7,,,,,,,,,
27 P8,,,GND,,,,,,,,,,,,
28 P9,,DIFFS,IO_L19N_7/VREF_7,UNUSED,,7,,,,,,,,,
29 P10,,DIFFM,IO_L20P_7,UNUSED,,7,,,,,,,,,
30 P11,,DIFFS,IO_L20N_7,UNUSED,,7,,,,,,,,,
31 P12,,DIFFM,IO_L21P_7,UNUSED,,7,,,,,,,,,
32 P13,,DIFFS,IO_L21N_7,UNUSED,,7,,,,,,,,,
33 P14,,,GND,,,,,,,,,,,,
34 P15,,DIFFM,IO_L22P_7,UNUSED,,7,,,,,,,,,
35 P16,,DIFFS,IO_L22N_7,UNUSED,,7,,,,,,,,,
36 P17,,,VCCAUX,,,,,,,,2.5,,,,
37 P18,,DIFFM,IO_L23P_7,UNUSED,,7,,,,,,,,,
38 P19,,DIFFS,IO_L23N_7,UNUSED,,7,,,,,,,,,
39 P20,,DIFFM,IO_L24P_7,UNUSED,,7,,,,,,,,,
40 P21,,DIFFS,IO_L24N_7,UNUSED,,7,,,,,,,,,
41 P22,,,NC,,,,,,,,,,,,
42 P23,,,VCCO_7,,,7,,,,,any******,,,,
43 P24,,,NC,,,,,,,,,,,,
44 P25,,,GND,,,,,,,,,,,,
45 P26,,DIFFM,IO_L40P_7,UNUSED,,7,,,,,,,,,
46 P27,,DIFFS,IO_L40N_7/VREF_7,UNUSED,,7,,,,,,,,,
47 P28,,DIFFM,IO_L40P_6/VREF_6,UNUSED,,6,,,,,,,,,
48 P29,,DIFFS,IO_L40N_6,UNUSED,,6,,,,,,,,,
49 P30,,,GND,,,,,,,,,,,,
50 P31,,,NC,,,,,,,,,,,,
51 P32,,,VCCO_6,,,6,,,,,any******,,,,
52 P33,,,NC,,,,,,,,,,,,
53 P34,,DIFFM,IO_L24P_6,UNUSED,,6,,,,,,,,,
54 P35,,DIFFS,IO_L24N_6/VREF_6,UNUSED,,6,,,,,,,,,
55 P36,,DIFFM,IO_L23P_6,UNUSED,,6,,,,,,,,,
56 P37,,DIFFS,IO_L23N_6,UNUSED,,6,,,,,,,,,
57 P38,,,VCCAUX,,,,,,,,2.5,,,,
58 P39,,DIFFM,IO_L22P_6,UNUSED,,6,,,,,,,,,
59 P40,,DIFFS,IO_L22N_6,UNUSED,,6,,,,,,,,,
60 P41,,,GND,,,,,,,,,,,,
61 P42,,DIFFM,IO_L21P_6,UNUSED,,6,,,,,,,,,
62 P43,,DIFFS,IO_L21N_6,UNUSED,,6,,,,,,,,,
63 P44,,DIFFM,IO_L20P_6,UNUSED,,6,,,,,,,,,
64 P45,,DIFFS,IO_L20N_6,UNUSED,,6,,,,,,,,,
65 P46,,DIFFM,IO_L19P_6,UNUSED,,6,,,,,,,,,
66 P47,,,GND,,,,,,,,,,,,
67 P48,,DIFFS,IO_L19N_6,UNUSED,,6,,,,,,,,,
68 P49,,,VCCO_6,,,6,,,,,any******,,,,
69 P50,,,NC,,,,,,,,,,,,
70 P51,,DIFFM,IO_L01P_6/VRN_6,UNUSED,,6,,,,,,,,,
71 P52,,DIFFS,IO_L01N_6/VRP_6,UNUSED,,6,,,,,,,,,
72 P53,,,GND,,,,,,,,,,,,
73 P54,,,M1,,,,,,,,,,,,
74 P55,,,M0,,,,,,,,,,,,
75 P56,,,M2,,,,,,,,,,,,
76 P57,,DIFFM,IO_L01P_5/CS_B,UNUSED,,5,,,,,,,,,
77 P58,,DIFFS,IO_L01N_5/RDWR_B,UNUSED,,5,,,,,,,,,
78 P59,,,GND,,,,,,,,,,,,
79 P60,,,VCCO_5,,,5,,,,,any******,,,,
80 P61,,DIFFM,IO_L10P_5/VRN_5,UNUSED,,5,,,,,,,,,
81 P62,,DIFFS,IO_L10N_5/VRP_5,UNUSED,,5,,,,,,,,,
82 P63,,IOB,IO,UNUSED,,5,,,,,,,,,
83 P64,,DIFFM,IO_L27P_5,UNUSED,,5,,,,,,,,,
84 P65,,DIFFS,IO_L27N_5/VREF_5,UNUSED,,5,,,,,,,,,
85 P66,,,GND,,,,,,,,,,,,
86 P67,,DIFFM,IO_L28P_5/D7,UNUSED,,5,,,,,,,,,
87 P68,,DIFFS,IO_L28N_5/D6,UNUSED,,5,,,,,,,,,
88 P69,,,VCCAUX,,,,,,,,2.5,,,,
89 P70,,,VCCINT,,,,,,,,1.2,,,,
90 P71,,IOB,IO,UNUSED,,5,,,,,,,,,
91 P72,,DIFFM,IO_L31P_5/D5,UNUSED,,5,,,,,,,,,
92 P73,,,VCCO_5,,,5,,,,,any******,,,,
93 P74,,DIFFS,IO_L31N_5/D4,UNUSED,,5,,,,,,,,,
94 P75,,,GND,,,,,,,,,,,,
95 P76,,DIFFM,IO_L32P_5/GCLK2,UNUSED,,5,,,,,,,,,
96 P77,,DIFFS,IO_L32N_5/GCLK3,UNUSED,,5,,,,,,,,,
97 P78,,IOB,IO/VREF_5,UNUSED,,5,,,,,,,,,
98 P79,,DIFFM,IO_L32P_4/GCLK0,UNUSED,,4,,,,,,,,,
99 P80,,DIFFS,IO_L32N_4/GCLK1,UNUSED,,4,,,,,,,,,
100 P81,,DIFFM,IO_L31P_4/DOUT/BUSY,UNUSED,,4,,,,,,,,,
101 P82,,,GND,,,,,,,,,,,,
102 P83,,DIFFS,IO_L31N_4/INIT_B,UNUSED,,4,,,,,,,,,
103 P84,,,VCCO_4,,,4,,,,,any******,,,,
104 P85,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,
105 P86,,DIFFM,IO_L30P_4/D3,UNUSED,,4,,,,,,,,,
106 P87,,DIFFS,IO_L30N_4/D2,UNUSED,,4,,,,,,,,,
107 P88,,,VCCINT,,,,,,,,1.2,,,,
108 P89,,,VCCAUX,,,,,,,,2.5,,,,
109 P90,,DIFFM,IO_L27P_4/D1,UNUSED,,4,,,,,,,,,
110 P91,,,GND,,,,,,,,,,,,
111 P92,,DIFFS,IO_L27N_4/DIN/D0,UNUSED,,4,,,,,,,,,
112 P93,,IOB,IO,UNUSED,,4,,,,,,,,,
113 P94,,DIFFM,IO_L25P_4,UNUSED,,4,,,,,,,,,
114 P95,,DIFFS,IO_L25N_4,UNUSED,,4,,,,,,,,,
115 P96,,,NC,,,,,,,,,,,,
116 P97,,,NC,,,,,,,,,,,,
117 P98,,,VCCO_4,,,4,,,,,any******,,,,
118 P99,,,GND,,,,,,,,,,,,
119 P100,,DIFFM,IO_L01P_4/VRN_4,UNUSED,,4,,,,,,,,,
120 P101,,DIFFS,IO_L01N_4/VRP_4,UNUSED,,4,,,,,,,,,
121 P102,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,,
122 P103,,,DONE,,,,,,,,,,,,
123 P104,,,CCLK,,,,,,,,,,,,
124 P105,,,GND,,,,,,,,,,,,
125 P106,,DIFFM,IO_L01P_3/VRN_3,UNUSED,,3,,,,,,,,,
126 P107,,DIFFS,IO_L01N_3/VRP_3,UNUSED,,3,,,,,,,,,
127 P108,,,NC,,,,,,,,,,,,
128 P109,,,NC,,,,,,,,,,,,
129 P110,,,VCCO_3,,,3,,,,,any******,,,,
130 P111,,DIFFM,IO_L19P_3,UNUSED,,3,,,,,,,,,
131 P112,,,GND,,,,,,,,,,,,
132 P113,,DIFFS,IO_L19N_3,UNUSED,,3,,,,,,,,,
133 P114,,DIFFM,IO_L20P_3,UNUSED,,3,,,,,,,,,
134 P115,,DIFFS,IO_L20N_3,UNUSED,,3,,,,,,,,,
135 P116,,DIFFM,IO_L21P_3,UNUSED,,3,,,,,,,,,
136 P117,,DIFFS,IO_L21N_3,UNUSED,,3,,,,,,,,,
137 P118,,,GND,,,,,,,,,,,,
138 P119,,DIFFM,IO_L22P_3,UNUSED,,3,,,,,,,,,
139 P120,,DIFFS,IO_L22N_3,UNUSED,,3,,,,,,,,,
140 P121,,,VCCAUX,,,,,,,,2.5,,,,
141 P122,,DIFFM,IO_L23P_3/VREF_3,UNUSED,,3,,,,,,,,,
142 P123,,DIFFS,IO_L23N_3,UNUSED,,3,,,,,,,,,
143 P124,,DIFFM,IO_L24P_3,UNUSED,,3,,,,,,,,,
144 P125,,DIFFS,IO_L24N_3,UNUSED,,3,,,,,,,,,
145 P126,,,NC,,,,,,,,,,,,
146 P127,,,VCCO_3,,,3,,,,,any******,,,,
147 P128,,,NC,,,,,,,,,,,,
148 P129,,,GND,,,,,,,,,,,,
149 P130,,DIFFM,IO_L40P_3,UNUSED,,3,,,,,,,,,
150 P131,,DIFFS,IO_L40N_3/VREF_3,UNUSED,,3,,,,,,,,,
151 P132,,DIFFM,IO_L40P_2/VREF_2,UNUSED,,2,,,,,,,,,
152 P133,,DIFFS,IO_L40N_2,UNUSED,,2,,,,,,,,,
153 P134,,,GND,,,,,,,,,,,,
154 P135,,,NC,,,,,,,,,,,,
155 P136,,,VCCO_2,,,2,,,,,any******,,,,
156 P137,,,NC,,,,,,,,,,,,
157 P138,,DIFFM,IO_L24P_2,UNUSED,,2,,,,,,,,,
158 P139,,DIFFS,IO_L24N_2,UNUSED,,2,,,,,,,,,
159 P140,,DIFFM,IO_L23P_2,UNUSED,,2,,,,,,,,,
160 P141,,DIFFS,IO_L23N_2/VREF_2,UNUSED,,2,,,,,,,,,
161 P142,,,VCCAUX,,,,,,,,2.5,,,,
162 P143,,DIFFM,IO_L22P_2,UNUSED,,2,,,,,,,,,
163 P144,,DIFFS,IO_L22N_2,UNUSED,,2,,,,,,,,,
164 P145,,,GND,,,,,,,,,,,,
165 P146,,DIFFM,IO_L21P_2,UNUSED,,2,,,,,,,,,
166 P147,,DIFFS,IO_L21N_2,UNUSED,,2,,,,,,,,,
167 P148,,DIFFM,IO_L20P_2,UNUSED,,2,,,,,,,,,
168 P149,,DIFFS,IO_L20N_2,UNUSED,,2,,,,,,,,,
169 P150,,DIFFM,IO_L19P_2,UNUSED,,2,,,,,,,,,
170 P151,,,GND,,,,,,,,,,,,
171 P152,,DIFFS,IO_L19N_2,UNUSED,,2,,,,,,,,,
172 P153,,,VCCO_2,,,2,,,,,any******,,,,
173 P154,,,NC,,,,,,,,,,,,
174 P155,,DIFFM,IO_L01P_2/VRN_2,UNUSED,,2,,,,,,,,,
175 P156,,DIFFS,IO_L01N_2/VRP_2,UNUSED,,2,,,,,,,,,
176 P157,,,GND,,,,,,,,,,,,
177 P158,,,TDO,,,,,,,,,,,,
178 P159,,,TCK,,,,,,,,,,,,
179 P160,,,TMS,,,,,,,,,,,,
180 P161,,DIFFM,IO_L01P_1/VRN_1,UNUSED,,1,,,,,,,,,
181 P162,,DIFFS,IO_L01N_1/VRP_1,UNUSED,,1,,,,,,,,,
182 P163,,,GND,,,,,,,,,,,,
183 P164,,,VCCO_1,,,1,,,,,any******,,,,
184 P165,,DIFFM,IO_L10P_1,UNUSED,,1,,,,,,,,,
185 P166,,DIFFS,IO_L10N_1/VREF_1,UNUSED,,1,,,,,,,,,
186 P167,,IOB,IO,UNUSED,,1,,,,,,,,,
187 P168,,DIFFM,IO_L27P_1,UNUSED,,1,,,,,,,,,
188 P169,,DIFFS,IO_L27N_1,UNUSED,,1,,,,,,,,,
189 P170,,,GND,,,,,,,,,,,,
190 P171,,DIFFM,IO_L28P_1,UNUSED,,1,,,,,,,,,
191 P172,,DIFFS,IO_L28N_1,UNUSED,,1,,,,,,,,,
192 P173,,,VCCAUX,,,,,,,,2.5,,,,
193 P174,,,VCCINT,,,,,,,,1.2,,,,
194 P175,,IOB,IO,UNUSED,,1,,,,,,,,,
195 P176,,DIFFM,IO_L31P_1,UNUSED,,1,,,,,,,,,
196 P177,,,VCCO_1,,,1,,,,,any******,,,,
197 P178,,DIFFS,IO_L31N_1/VREF_1,UNUSED,,1,,,,,,,,,
198 P179,,,GND,,,,,,,,,,,,
199 P180,,DIFFM,IO_L32P_1/GCLK4,UNUSED,,1,,,,,,,,,
200 P181,,DIFFS,IO_L32N_1/GCLK5,UNUSED,,1,,,,,,,,,
201 P182,,IOB,IO,UNUSED,,1,,,,,,,,,
202 P183,NaN,IOB,IO_L32P_0/GCLK6,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
203 P184,N<0>,IOB,IO_L32N_0/GCLK7,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
204 P185,N<23>,IOB,IO_L31P_0/VREF_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE,
205 P186,,,GND,,,,,,,,,,,,
206 P187,INF,IOB,IO_L31N_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE,
207 P188,,,VCCO_0,,,0,,,,,2.50,,,,
208 P189,,IOB,IO,UNUSED,,0,,,,,,,,,
209 P190,,DIFFM,IO_L30P_0,UNUSED,,0,,,,,,,,,
210 P191,,DIFFS,IO_L30N_0,UNUSED,,0,,,,,,,,,
211 P192,,,VCCINT,,,,,,,,1.2,,,,
212 P193,,,VCCAUX,,,,,,,,2.5,,,,
213 P194,,DIFFM,IO_L27P_0,UNUSED,,0,,,,,,,,,
214 P195,,,GND,,,,,,,,,,,,
215 P196,,DIFFS,IO_L27N_0,UNUSED,,0,,,,,,,,,
216 P197,,IOB,IO,UNUSED,,0,,,,,,,,,
217 P198,,DIFFM,IO_L25P_0,UNUSED,,0,,,,,,,,,
218 P199,,DIFFS,IO_L25N_0,UNUSED,,0,,,,,,,,,
219 P200,,,NC,,,,,,,,,,,,
220 P201,,,VCCO_0,,,0,,,,,2.50,,,,
221 P202,,,GND,,,,,,,,,,,,
222 P203,,DIFFM,IO_L01P_0/VRN_0,UNUSED,,0,,,,,,,,,
223 P204,,DIFFS,IO_L01N_0/VRP_0,UNUSED,,0,,,,,,,,,
224 P205,,IOB,IO/VREF_0,UNUSED,,0,,,,,,,,,
225 P206,,,HSWAP_EN,,,,,,,,,,,,
226 P207,,,PROG_B,,,,,,,,,,,,
227 P208,,,TDI,,,,,,,,,,,,
228 # -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,
229 #
230 #* Default value.
231 #** This default Pullup/Pulldown value can be overridden in Bitgen.
232 #****** Special VCCO requirements may apply. Please consult the device
233 # family datasheet for specific guideline on VCCO requirements.
234 #
235 #
236 #

238
TypeCheck_pad.txt Normal file
View File

@@ -0,0 +1,238 @@
Release 14.7 - par P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Sat Aug 17 16:41:02 2019
INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are:
1. The <design name>_pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors.
2. The <design namd>_pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information.
3. The <design name>.pad file designed for parsing by customers. It uses the "|" as a data field separator.
INPUT FILE: TypeCheck_map.ncd
OUTPUT FILE: TypeCheck_pad.txt
PART TYPE: xc3s50
SPEED GRADE: -5
PACKAGE: pq208
Pinout by Pin Number:
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity|
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
|P1 | | |GND | | | | | | | | | | | |
|P2 | |DIFFM |IO_L01P_7/VRN_7 |UNUSED | |7 | | | | | | | | |
|P3 | |DIFFS |IO_L01N_7/VRP_7 |UNUSED | |7 | | | | | | | | |
|P4 | | |NC | | | | | | | | | | | |
|P5 | | |NC | | | | | | | | | | | |
|P6 | | |VCCO_7 | | |7 | | | | |any******| | | |
|P7 | |DIFFM |IO_L19P_7 |UNUSED | |7 | | | | | | | | |
|P8 | | |GND | | | | | | | | | | | |
|P9 | |DIFFS |IO_L19N_7/VREF_7 |UNUSED | |7 | | | | | | | | |
|P10 | |DIFFM |IO_L20P_7 |UNUSED | |7 | | | | | | | | |
|P11 | |DIFFS |IO_L20N_7 |UNUSED | |7 | | | | | | | | |
|P12 | |DIFFM |IO_L21P_7 |UNUSED | |7 | | | | | | | | |
|P13 | |DIFFS |IO_L21N_7 |UNUSED | |7 | | | | | | | | |
|P14 | | |GND | | | | | | | | | | | |
|P15 | |DIFFM |IO_L22P_7 |UNUSED | |7 | | | | | | | | |
|P16 | |DIFFS |IO_L22N_7 |UNUSED | |7 | | | | | | | | |
|P17 | | |VCCAUX | | | | | | | |2.5 | | | |
|P18 | |DIFFM |IO_L23P_7 |UNUSED | |7 | | | | | | | | |
|P19 | |DIFFS |IO_L23N_7 |UNUSED | |7 | | | | | | | | |
|P20 | |DIFFM |IO_L24P_7 |UNUSED | |7 | | | | | | | | |
|P21 | |DIFFS |IO_L24N_7 |UNUSED | |7 | | | | | | | | |
|P22 | | |NC | | | | | | | | | | | |
|P23 | | |VCCO_7 | | |7 | | | | |any******| | | |
|P24 | | |NC | | | | | | | | | | | |
|P25 | | |GND | | | | | | | | | | | |
|P26 | |DIFFM |IO_L40P_7 |UNUSED | |7 | | | | | | | | |
|P27 | |DIFFS |IO_L40N_7/VREF_7 |UNUSED | |7 | | | | | | | | |
|P28 | |DIFFM |IO_L40P_6/VREF_6 |UNUSED | |6 | | | | | | | | |
|P29 | |DIFFS |IO_L40N_6 |UNUSED | |6 | | | | | | | | |
|P30 | | |GND | | | | | | | | | | | |
|P31 | | |NC | | | | | | | | | | | |
|P32 | | |VCCO_6 | | |6 | | | | |any******| | | |
|P33 | | |NC | | | | | | | | | | | |
|P34 | |DIFFM |IO_L24P_6 |UNUSED | |6 | | | | | | | | |
|P35 | |DIFFS |IO_L24N_6/VREF_6 |UNUSED | |6 | | | | | | | | |
|P36 | |DIFFM |IO_L23P_6 |UNUSED | |6 | | | | | | | | |
|P37 | |DIFFS |IO_L23N_6 |UNUSED | |6 | | | | | | | | |
|P38 | | |VCCAUX | | | | | | | |2.5 | | | |
|P39 | |DIFFM |IO_L22P_6 |UNUSED | |6 | | | | | | | | |
|P40 | |DIFFS |IO_L22N_6 |UNUSED | |6 | | | | | | | | |
|P41 | | |GND | | | | | | | | | | | |
|P42 | |DIFFM |IO_L21P_6 |UNUSED | |6 | | | | | | | | |
|P43 | |DIFFS |IO_L21N_6 |UNUSED | |6 | | | | | | | | |
|P44 | |DIFFM |IO_L20P_6 |UNUSED | |6 | | | | | | | | |
|P45 | |DIFFS |IO_L20N_6 |UNUSED | |6 | | | | | | | | |
|P46 | |DIFFM |IO_L19P_6 |UNUSED | |6 | | | | | | | | |
|P47 | | |GND | | | | | | | | | | | |
|P48 | |DIFFS |IO_L19N_6 |UNUSED | |6 | | | | | | | | |
|P49 | | |VCCO_6 | | |6 | | | | |any******| | | |
|P50 | | |NC | | | | | | | | | | | |
|P51 | |DIFFM |IO_L01P_6/VRN_6 |UNUSED | |6 | | | | | | | | |
|P52 | |DIFFS |IO_L01N_6/VRP_6 |UNUSED | |6 | | | | | | | | |
|P53 | | |GND | | | | | | | | | | | |
|P54 | | |M1 | | | | | | | | | | | |
|P55 | | |M0 | | | | | | | | | | | |
|P56 | | |M2 | | | | | | | | | | | |
|P57 | |DIFFM |IO_L01P_5/CS_B |UNUSED | |5 | | | | | | | | |
|P58 | |DIFFS |IO_L01N_5/RDWR_B |UNUSED | |5 | | | | | | | | |
|P59 | | |GND | | | | | | | | | | | |
|P60 | | |VCCO_5 | | |5 | | | | |any******| | | |
|P61 | |DIFFM |IO_L10P_5/VRN_5 |UNUSED | |5 | | | | | | | | |
|P62 | |DIFFS |IO_L10N_5/VRP_5 |UNUSED | |5 | | | | | | | | |
|P63 | |IOB |IO |UNUSED | |5 | | | | | | | | |
|P64 | |DIFFM |IO_L27P_5 |UNUSED | |5 | | | | | | | | |
|P65 | |DIFFS |IO_L27N_5/VREF_5 |UNUSED | |5 | | | | | | | | |
|P66 | | |GND | | | | | | | | | | | |
|P67 | |DIFFM |IO_L28P_5/D7 |UNUSED | |5 | | | | | | | | |
|P68 | |DIFFS |IO_L28N_5/D6 |UNUSED | |5 | | | | | | | | |
|P69 | | |VCCAUX | | | | | | | |2.5 | | | |
|P70 | | |VCCINT | | | | | | | |1.2 | | | |
|P71 | |IOB |IO |UNUSED | |5 | | | | | | | | |
|P72 | |DIFFM |IO_L31P_5/D5 |UNUSED | |5 | | | | | | | | |
|P73 | | |VCCO_5 | | |5 | | | | |any******| | | |
|P74 | |DIFFS |IO_L31N_5/D4 |UNUSED | |5 | | | | | | | | |
|P75 | | |GND | | | | | | | | | | | |
|P76 | |DIFFM |IO_L32P_5/GCLK2 |UNUSED | |5 | | | | | | | | |
|P77 | |DIFFS |IO_L32N_5/GCLK3 |UNUSED | |5 | | | | | | | | |
|P78 | |IOB |IO/VREF_5 |UNUSED | |5 | | | | | | | | |
|P79 | |DIFFM |IO_L32P_4/GCLK0 |UNUSED | |4 | | | | | | | | |
|P80 | |DIFFS |IO_L32N_4/GCLK1 |UNUSED | |4 | | | | | | | | |
|P81 | |DIFFM |IO_L31P_4/DOUT/BUSY|UNUSED | |4 | | | | | | | | |
|P82 | | |GND | | | | | | | | | | | |
|P83 | |DIFFS |IO_L31N_4/INIT_B |UNUSED | |4 | | | | | | | | |
|P84 | | |VCCO_4 | | |4 | | | | |any******| | | |
|P85 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | |
|P86 | |DIFFM |IO_L30P_4/D3 |UNUSED | |4 | | | | | | | | |
|P87 | |DIFFS |IO_L30N_4/D2 |UNUSED | |4 | | | | | | | | |
|P88 | | |VCCINT | | | | | | | |1.2 | | | |
|P89 | | |VCCAUX | | | | | | | |2.5 | | | |
|P90 | |DIFFM |IO_L27P_4/D1 |UNUSED | |4 | | | | | | | | |
|P91 | | |GND | | | | | | | | | | | |
|P92 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | |
|P93 | |IOB |IO |UNUSED | |4 | | | | | | | | |
|P94 | |DIFFM |IO_L25P_4 |UNUSED | |4 | | | | | | | | |
|P95 | |DIFFS |IO_L25N_4 |UNUSED | |4 | | | | | | | | |
|P96 | | |NC | | | | | | | | | | | |
|P97 | | |NC | | | | | | | | | | | |
|P98 | | |VCCO_4 | | |4 | | | | |any******| | | |
|P99 | | |GND | | | | | | | | | | | |
|P100 | |DIFFM |IO_L01P_4/VRN_4 |UNUSED | |4 | | | | | | | | |
|P101 | |DIFFS |IO_L01N_4/VRP_4 |UNUSED | |4 | | | | | | | | |
|P102 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | |
|P103 | | |DONE | | | | | | | | | | | |
|P104 | | |CCLK | | | | | | | | | | | |
|P105 | | |GND | | | | | | | | | | | |
|P106 | |DIFFM |IO_L01P_3/VRN_3 |UNUSED | |3 | | | | | | | | |
|P107 | |DIFFS |IO_L01N_3/VRP_3 |UNUSED | |3 | | | | | | | | |
|P108 | | |NC | | | | | | | | | | | |
|P109 | | |NC | | | | | | | | | | | |
|P110 | | |VCCO_3 | | |3 | | | | |any******| | | |
|P111 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | |
|P112 | | |GND | | | | | | | | | | | |
|P113 | |DIFFS |IO_L19N_3 |UNUSED | |3 | | | | | | | | |
|P114 | |DIFFM |IO_L20P_3 |UNUSED | |3 | | | | | | | | |
|P115 | |DIFFS |IO_L20N_3 |UNUSED | |3 | | | | | | | | |
|P116 | |DIFFM |IO_L21P_3 |UNUSED | |3 | | | | | | | | |
|P117 | |DIFFS |IO_L21N_3 |UNUSED | |3 | | | | | | | | |
|P118 | | |GND | | | | | | | | | | | |
|P119 | |DIFFM |IO_L22P_3 |UNUSED | |3 | | | | | | | | |
|P120 | |DIFFS |IO_L22N_3 |UNUSED | |3 | | | | | | | | |
|P121 | | |VCCAUX | | | | | | | |2.5 | | | |
|P122 | |DIFFM |IO_L23P_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|P123 | |DIFFS |IO_L23N_3 |UNUSED | |3 | | | | | | | | |
|P124 | |DIFFM |IO_L24P_3 |UNUSED | |3 | | | | | | | | |
|P125 | |DIFFS |IO_L24N_3 |UNUSED | |3 | | | | | | | | |
|P126 | | |NC | | | | | | | | | | | |
|P127 | | |VCCO_3 | | |3 | | | | |any******| | | |
|P128 | | |NC | | | | | | | | | | | |
|P129 | | |GND | | | | | | | | | | | |
|P130 | |DIFFM |IO_L40P_3 |UNUSED | |3 | | | | | | | | |
|P131 | |DIFFS |IO_L40N_3/VREF_3 |UNUSED | |3 | | | | | | | | |
|P132 | |DIFFM |IO_L40P_2/VREF_2 |UNUSED | |2 | | | | | | | | |
|P133 | |DIFFS |IO_L40N_2 |UNUSED | |2 | | | | | | | | |
|P134 | | |GND | | | | | | | | | | | |
|P135 | | |NC | | | | | | | | | | | |
|P136 | | |VCCO_2 | | |2 | | | | |any******| | | |
|P137 | | |NC | | | | | | | | | | | |
|P138 | |DIFFM |IO_L24P_2 |UNUSED | |2 | | | | | | | | |
|P139 | |DIFFS |IO_L24N_2 |UNUSED | |2 | | | | | | | | |
|P140 | |DIFFM |IO_L23P_2 |UNUSED | |2 | | | | | | | | |
|P141 | |DIFFS |IO_L23N_2/VREF_2 |UNUSED | |2 | | | | | | | | |
|P142 | | |VCCAUX | | | | | | | |2.5 | | | |
|P143 | |DIFFM |IO_L22P_2 |UNUSED | |2 | | | | | | | | |
|P144 | |DIFFS |IO_L22N_2 |UNUSED | |2 | | | | | | | | |
|P145 | | |GND | | | | | | | | | | | |
|P146 | |DIFFM |IO_L21P_2 |UNUSED | |2 | | | | | | | | |
|P147 | |DIFFS |IO_L21N_2 |UNUSED | |2 | | | | | | | | |
|P148 | |DIFFM |IO_L20P_2 |UNUSED | |2 | | | | | | | | |
|P149 | |DIFFS |IO_L20N_2 |UNUSED | |2 | | | | | | | | |
|P150 | |DIFFM |IO_L19P_2 |UNUSED | |2 | | | | | | | | |
|P151 | | |GND | | | | | | | | | | | |
|P152 | |DIFFS |IO_L19N_2 |UNUSED | |2 | | | | | | | | |
|P153 | | |VCCO_2 | | |2 | | | | |any******| | | |
|P154 | | |NC | | | | | | | | | | | |
|P155 | |DIFFM |IO_L01P_2/VRN_2 |UNUSED | |2 | | | | | | | | |
|P156 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | |
|P157 | | |GND | | | | | | | | | | | |
|P158 | | |TDO | | | | | | | | | | | |
|P159 | | |TCK | | | | | | | | | | | |
|P160 | | |TMS | | | | | | | | | | | |
|P161 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | |
|P162 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | |
|P163 | | |GND | | | | | | | | | | | |
|P164 | | |VCCO_1 | | |1 | | | | |any******| | | |
|P165 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | |
|P166 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | |
|P167 | |IOB |IO |UNUSED | |1 | | | | | | | | |
|P168 | |DIFFM |IO_L27P_1 |UNUSED | |1 | | | | | | | | |
|P169 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | |
|P170 | | |GND | | | | | | | | | | | |
|P171 | |DIFFM |IO_L28P_1 |UNUSED | |1 | | | | | | | | |
|P172 | |DIFFS |IO_L28N_1 |UNUSED | |1 | | | | | | | | |
|P173 | | |VCCAUX | | | | | | | |2.5 | | | |
|P174 | | |VCCINT | | | | | | | |1.2 | | | |
|P175 | |IOB |IO |UNUSED | |1 | | | | | | | | |
|P176 | |DIFFM |IO_L31P_1 |UNUSED | |1 | | | | | | | | |
|P177 | | |VCCO_1 | | |1 | | | | |any******| | | |
|P178 | |DIFFS |IO_L31N_1/VREF_1 |UNUSED | |1 | | | | | | | | |
|P179 | | |GND | | | | | | | | | | | |
|P180 | |DIFFM |IO_L32P_1/GCLK4 |UNUSED | |1 | | | | | | | | |
|P181 | |DIFFS |IO_L32N_1/GCLK5 |UNUSED | |1 | | | | | | | | |
|P182 | |IOB |IO |UNUSED | |1 | | | | | | | | |
|P183 |NaN |IOB |IO_L32P_0/GCLK6 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P184 |N<0> |IOB |IO_L32N_0/GCLK7 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|P185 |N<23> |IOB |IO_L31P_0/VREF_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE |
|P186 | | |GND | | | | | | | | | | | |
|P187 |INF |IOB |IO_L31N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE |
|P188 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|P189 | |IOB |IO |UNUSED | |0 | | | | | | | | |
|P190 | |DIFFM |IO_L30P_0 |UNUSED | |0 | | | | | | | | |
|P191 | |DIFFS |IO_L30N_0 |UNUSED | |0 | | | | | | | | |
|P192 | | |VCCINT | | | | | | | |1.2 | | | |
|P193 | | |VCCAUX | | | | | | | |2.5 | | | |
|P194 | |DIFFM |IO_L27P_0 |UNUSED | |0 | | | | | | | | |
|P195 | | |GND | | | | | | | | | | | |
|P196 | |DIFFS |IO_L27N_0 |UNUSED | |0 | | | | | | | | |
|P197 | |IOB |IO |UNUSED | |0 | | | | | | | | |
|P198 | |DIFFM |IO_L25P_0 |UNUSED | |0 | | | | | | | | |
|P199 | |DIFFS |IO_L25N_0 |UNUSED | |0 | | | | | | | | |
|P200 | | |NC | | | | | | | | | | | |
|P201 | | |VCCO_0 | | |0 | | | | |2.50 | | | |
|P202 | | |GND | | | | | | | | | | | |
|P203 | |DIFFM |IO_L01P_0/VRN_0 |UNUSED | |0 | | | | | | | | |
|P204 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | |
|P205 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | |
|P206 | | |HSWAP_EN | | | | | | | | | | | |
|P207 | | |PROG_B | | | | | | | | | | | |
|P208 | | |TDI | | | | | | | | | | | |
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Default value.
** This default Pullup/Pulldown value can be overridden in Bitgen.
****** Special VCCO requirements may apply. Please consult the device
family datasheet for specific guideline on VCCO requirements.

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TypeCheck_summary.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DesignSummary rev="2">
<CmdHistory>
</CmdHistory>
</DesignSummary>

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TypeCheck_usage.xml Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<DeviceUsageSummary rev="2">
<DesignStatistics TimeStamp="Sat Aug 17 16:40:59 2019"><group name="MiscellaneousStatistics">
<item name="AGG_BONDED_IO" rev="2">
<attrib name="value" value="4"/></item>
<item name="AGG_IO" rev="2">
<attrib name="value" value="4"/></item>
<item name="AGG_SLICE" rev="2">
<attrib name="value" value="2"/></item>
<item name="NUM_4_INPUT_LUT" rev="2">
<attrib name="value" value="4"/></item>
<item name="NUM_BONDED_IOB" rev="2">
<attrib name="value" value="4"/></item>
<item name="NUM_SLICEL" rev="2">
<attrib name="value" value="2"/></item>
</group>
</DesignStatistics>
<CmdHistory>
</CmdHistory>
</DeviceUsageSummary>

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TypeCheck_xst.xrpt Normal file
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<?xml version="1.0" encoding="UTF-8" standalone="yes" ?>
<document OS="lin64" product="ISE" version="14.7">
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
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<row stringID="row" value="4">
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<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
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<row stringID="row" value="2">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
<item stringID="speed" value="2494.222 MHz"/>
</row>
<row stringID="row" value="3">
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
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<section stringID="XST_OPTION_SUMMARY">
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_ngo/netlist.lst Normal file
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/home/Luca/ISE/IEEE754Adder/TypeCheck.ngc 1566052852
OK

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_xmsgs/map.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="LIT" num="243" delta="old" >Logical network <arg fmt="%s" index="1">N&lt;31&gt;</arg> has no load.
</msg>
<msg type="info" file="LIT" num="395" delta="old" >The above <arg fmt="%s" index="1">info</arg> message is repeated <arg fmt="%d" index="2">29</arg> more times for the following (max. 5 shown):
<arg fmt="%s" index="3">N&lt;30&gt;,
N&lt;29&gt;,
N&lt;28&gt;,
N&lt;27&gt;,
N&lt;26&gt;</arg>
To see the details of these <arg fmt="%s" index="4">info</arg> messages, please use the -detail switch.
</msg>
<msg type="info" file="MapLib" num="562" delta="old" >No environment variables are currently set.
</msg>
<msg type="info" file="LIT" num="244" delta="old" >All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs.
</msg>
</messages>

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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
</messages>

12
_xmsgs/par.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Par" num="282" delta="old" >No user timing constraints were detected or you have set the option to ignore timing constraints (&quot;par -x&quot;). Place and Route will run in &quot;Performance Evaluation Mode&quot; to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to &quot;std&quot;. For best performance, set the effort level to &quot;high&quot;.
</msg>
</messages>

15
_xmsgs/pn_parser.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated -->
<!-- by the Xilinx ISE software. Any direct editing or -->
<!-- changes made to this file may result in unpredictable -->
<!-- behavior or data corruption. It is strongly advised that -->
<!-- users do not edit the contents of this file. -->
<!-- -->
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd&quot; into library work</arg>
</msg>
</messages>

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_xmsgs/trce.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="info" file="Timing" num="2698" delta="old" >No timing constraints found, doing default enumeration.</msg>
<msg type="info" file="Timing" num="3412" delta="old" >To improve timing, see the Timing Closure User Guide (UG612).</msg>
<msg type="info" file="Timing" num="2752" delta="old" >To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.</msg>
<msg type="info" file="Timing" num="3339" delta="old" >The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.</msg>
<msg type="info" file="Timing" num="3390" delta="old" >This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.</msg>
<msg type="info" file="Timing" num="3389" delta="old" >This architecture does not support &apos;Discrete Jitter&apos; and &apos;Phase Error&apos; calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.</msg>
</messages>

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_xmsgs/xst.xmsgs Normal file
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<?xml version="1.0" encoding="UTF-8"?>
<!-- IMPORTANT: This is an internal file that has been generated
by the Xilinx ISE software. Any direct editing or
changes made to this file may result in unpredictable
behavior or data corruption. It is strongly advised that
users do not edit the contents of this file. -->
<messages>
<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">N&lt;31&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
</msg>
</messages>

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iseconfig/SpecialCasesCheck.xreport Normal file
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<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2019-08-17T15:26:24</DateModified>
<ModuleName>SpecialCasesCheck</ModuleName>
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
<SavedFilePath>/home/Luca/ISE/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport</SavedFilePath>
<ImplementationReportsDirectory>/home/Luca/ISE/IEEE754Adder</ImplementationReportsDirectory>
<DateInitialized>2019-08-17T15:26:24</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
<body>
<viewgroup label="Design Overview" >
<view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="SpecialCasesCheck_summary.html" label="Summary" >
<toc-item title="Design Overview" target="Design Overview" />
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
<toc-item title="Performance Summary" target="Performance Summary" />
<toc-item title="Failing Constraints" target="Failing Constraints" />
<toc-item title="Detailed Reports" target="Detailed Reports" />
</view>
<view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="SpecialCasesCheck_envsettings.html" label="System Settings" />
<view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="SpecialCasesCheck_map.xrpt" label="IOB Properties" />
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="SpecialCasesCheck_map.xrpt" label="Control Set Information" />
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<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SpecialCasesCheck_html/fit/report.htm" label="CPLD Fitter Report" />
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="SpecialCasesCheck_html/tim/report.htm" label="CPLD Timing Report" />
</viewgroup>
<viewgroup label="XPS Errors and Warnings" >
<view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
<view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
</viewgroup>
<viewgroup label="XPS Reports" >
<view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
<view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
<view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="SpecialCasesCheck.log" label="System Log File" />
</viewgroup>
<viewgroup label="Errors and Warnings" >
<view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
<view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
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<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
<toc-item title="HDL Compilation" target=" HDL Compilation " />
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
<toc-item title="HDL Analysis" target=" HDL Analysis " />
<toc-item title="HDL Parsing" target=" HDL Parsing " />
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
<toc-item title="HDL Synthesis" target=" HDL Synthesis " />
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<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
<toc-item title="Partition Report" target=" Partition Report " />
<toc-item title="Final Report" target=" Final Report " />
<toc-item title="Design Summary" target=" Design Summary " />
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<toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
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<toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
<toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
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<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
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<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
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<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
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<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
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<toc-item title="Device Utilization" target="Device Utilization Summary:" />
<toc-item title="Router Information" target="Starting Router" />
<toc-item title="Partition Status" target="Partition Implementation Status" />
<toc-item title="Clock Report" target="Generating Clock Report" />
<toc-item title="Timing Results" target="Timing Score:" />
<toc-item title="Final Summary" target="Peak Memory Usage:" />
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<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
<toc-item title="Timing Constraints" target="Timing constraint:" />
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
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<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
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<toc-item title="Performance Summary" target="Performance Summary:" />
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<toc-item title="Power summary" target="Power summary" />
<toc-item title="Thermal summary" target="Thermal summary" />
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<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
<toc-item title="Final Summary" target="DRC detected" />
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<toc-item title="Timing Report Description" target="Device,package,speed:" />
<toc-item title="Informational Messages" target="INFO:" />
<toc-item title="Warning Messages" target="WARNING:" />
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<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
<toc-item title="Timing Summary" target="Timing summary:" />
<toc-item title="Trace Settings" target="Trace Settings:" />
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<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="SpecialCasesCheck_pad.txt" label="Pad Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="SpecialCasesCheck.unroutes" label="Unroutes Report" >
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
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<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="SpecialCasesCheck_preroute.tsi" label="Post-Map Constraints Interaction Report" >
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<toc-item title="Component" target="Component " />
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<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
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<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Aug 17 17:02:15 2019">
<section name="Project Information" visible="false">
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<property name="ProjectCreationTimestamp" value="2019-08-17T15:21:55" type="project"/>
</section>
<section name="Project Statistics" visible="true">
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<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2019-08-17T15:21:55" type="design"/>
<property name="PROP_intWbtProjectID" value="144FE553FD2E31FF5236C06C33BACBB5" type="design"/>
<property name="PROP_intWbtProjectIteration" value="2" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_xilxPARplacerEffortLevel" value="Standard" type="process"/>
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<property name="PROP_AutoTop" value="true" type="design"/>
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V3 3
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