commit a1b9650580f028afe4071fabae4e8164bd0a3c02 Author: Luca Date: Sat Aug 17 17:41:27 2019 +0200 Initial commit diff --git a/IEEE754Adder.gise b/IEEE754Adder.gise new file mode 100644 index 0000000..47f567c --- /dev/null +++ b/IEEE754Adder.gise @@ -0,0 +1,179 @@ + + + + + + + + + + + + + + + + + + + + 11.1 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise new file mode 100644 index 0000000..44bea3f --- /dev/null +++ b/IEEE754Adder.xise @@ -0,0 +1,384 @@ + + + +
+ + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/SpecialCasesCheck.cmd_log b/SpecialCasesCheck.cmd_log new file mode 100644 index 0000000..4fe0e25 --- /dev/null +++ b/SpecialCasesCheck.cmd_log @@ -0,0 +1,4 @@ +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" diff --git a/SpecialCasesCheck.lso b/SpecialCasesCheck.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/SpecialCasesCheck.lso @@ -0,0 +1 @@ +work diff --git a/SpecialCasesCheck.prj b/SpecialCasesCheck.prj new file mode 100644 index 0000000..9c69a7e --- /dev/null +++ b/SpecialCasesCheck.prj @@ -0,0 +1 @@ +vhdl work "SpecialCasesCheck.vhd" diff --git a/SpecialCasesCheck.syr b/SpecialCasesCheck.syr new file mode 100644 index 0000000..843977d --- /dev/null +++ b/SpecialCasesCheck.syr @@ -0,0 +1,126 @@ +Release 14.7 - xst P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.04 secs + +--> +Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.04 secs + +--> +Reading design: SpecialCasesCheck.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "SpecialCasesCheck.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "SpecialCasesCheck" +Output Format : NGC +Target Device : xc3s50-5-pq208 + +---- Source Options +Top Module Name : SpecialCasesCheck +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : Yes +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : Yes +Resource Sharing : YES +Asynchronous To Synchronous : NO +Multiplier Style : Auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 8 +Register Duplication : YES +Slice Packing : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Yes +Use Synchronous Set : Yes +Use Synchronous Reset : Yes +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +Verilog 2001 : YES +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work. +Entity compiled. +Entity (Architecture ) compiled. +ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. Undefined symbol 'std_logic_vector'. +ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 49. std_logic_vector: Undefined symbol (last report in this block) +ERROR:HDLParsers:3312 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. Undefined symbol 'std_logic'. +ERROR:HDLParsers:1209 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 51. std_logic: Undefined symbol (last report in this block) +ERROR:HDLParsers:3010 - "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" Line 55. Entity SpecialCasesCheck does not exist. +--> + + +Total memory usage is 584420 kilobytes + +Number of errors : 5 ( 0 filtered) +Number of warnings : 0 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/SpecialCasesCheck.vhd b/SpecialCasesCheck.vhd new file mode 100644 index 0000000..996bb0a --- /dev/null +++ b/SpecialCasesCheck.vhd @@ -0,0 +1,59 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + +entity TypeCheck is + port( + N: in std_logic_vector(31 downto 0); + NaN, INF: out std_logic + ); +end TypeCheck; + +architecture TypeCheckArch of TypeCheck is + signal G_Bus: std_logic_vector(7 downto 0); + signal T_Bus: std_logic_vector(22 downto 0); + signal G: std_logic := '1'; + signal T: std_logic := '0'; +begin + G_Bus <= N(30 downto 23); + T_Bus <= N(22 downto 0); + + G_compute: process (G_Bus) + variable G_tmp: std_logic; + begin + G_tmp := '1'; + for i in G_Bus'range loop + G_tmp := G_tmp and G_Bus(i); + end loop; + G <= G_tmp; + end process; + + T_compute: process (T_Bus) + variable T_tmp: std_logic; + begin + T_tmp := '0'; + for i in T_Bus'range loop + T_tmp := T_tmp or T_Bus(i); + end loop; + T <= T_tmp; + end process; + + NaN <= G and T; + INF <= G and (not T); +end TypeCheckArch; + + + +--entity SpecialCasesCheck is +-- port( +-- X, Y: in std_logic_vector(31 downto 0); +-- isNan, isZero: out std_logic +-- ); +--end SpecialCasesCheck; +-- +-- +--architecture SpecialCasesCheckArch of SpecialCasesCheck is +-- +--begin +-- +--end SpecialCasesCheckArch; + diff --git a/SpecialCasesCheck.xst b/SpecialCasesCheck.xst new file mode 100644 index 0000000..4ad8c20 --- /dev/null +++ b/SpecialCasesCheck.xst @@ -0,0 +1,56 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn SpecialCasesCheck.prj +-ifmt mixed +-ofn SpecialCasesCheck +-ofmt NGC +-p xc3s50-5-pq208 +-top SpecialCasesCheck +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/SpecialCasesCheck_envsettings.html b/SpecialCasesCheck_envsettings.html new file mode 100644 index 0000000..a9b7595 --- /dev/null +++ b/SpecialCasesCheck_envsettings.html @@ -0,0 +1,382 @@ +Xilinx System Settings Report + +
System Settings

+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Environment Settings
Environment Variablexstngdbuildmappar
LD_LIBRARY_PATH/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:
/opt/Xilinx/14.7/ISE_DS/common/lib/lin64		< data not available >< data not available >< data not available >
PATH/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:
/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:
/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:
/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:
/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:
/usr/lib64/qt-3.3/bin:
/usr/local/bin:
/usr/bin:
/bin:
/usr/local/sbin:
/usr/sbin:
/sbin:
/home/Luca/bin		< data not available >< data not available >< data not available >
XILINX/opt/Xilinx/14.7/ISE_DS/ISE/< data not available >< data not available >< data not available >
XILINX_DSP/opt/Xilinx/14.7/ISE_DS/ISE< data not available >< data not available >< data not available >
XILINX_EDK/opt/Xilinx/14.7/ISE_DS/EDK< data not available >< data not available >< data not available >
XILINX_PLANAHEAD/opt/Xilinx/14.7/ISE_DS/PlanAhead< data not available >< data not available >< data not available >
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Synthesis Property Settings
Switch NameProperty NameValueDefault Value
-ifn SpecialCasesCheck.prj 
-ifmt mixedMIXED
-ofn SpecialCasesCheck 
-ofmt NGCNGC
-p xc3s50-5-pq208 
-top SpecialCasesCheck 
-opt_modeOptimization GoalSpeedSPEED
-opt_levelOptimization Effort11
-iucUse synthesis Constraints FileNONO
-keep_hierarchyKeep HierarchyNoNO
-netlist_hierarchyNetlist HierarchyAs_Optimizedas_optimized
-rtlviewGenerate RTL SchematicYesNO
-glob_optGlobal Optimization GoalAllClockNetsALLCLOCKNETS
-read_coresRead CoresYESYES
-write_timing_constraintsWrite Timing ConstraintsNONO
-cross_clock_analysisCross Clock AnalysisNONO
-bus_delimiterBus Delimiter<><>
-slice_utilization_ratioSlice Utilization Ratio100100%
-bram_utilization_ratioBRAM Utilization Ratio100100%
-verilog2001Verilog 2001YESYES
-fsm_extract YESYES
-fsm_encoding AutoAUTO
-safe_implementation NoNO
-fsm_style LUTLUT
-ram_extract YesYES
-ram_style AutoAUTO
-rom_extract YesYES
-shreg_extract YESYES
-rom_style AutoAUTO
-auto_bram_packing NONO
-resource_sharing YESYES
-async_to_sync NONO
-mult_style AutoAUTO
-iobuf YESYES
-max_fanout 500500
-bufg 88
-register_duplication YESYES
-register_balancing NoNO
-optimize_primitives NONO
-use_clock_enable YesYES
-use_sync_set YesYES
-use_sync_reset YesYES
-iob AutoAUTO
-equivalent_register_removal YESYES
-slice_utilization_ratio_maxmargin 50%
+ + 
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
Operating System Information
Operating System Informationxstngdbuildmappar
CPU Architecture/SpeedIntel Core Processor (Haswell, no TSX)/2494.222 MHz<  data not available  ><  data not available  ><  data not available  >
HostXilinx<  data not available  ><  data not available  ><  data not available  >
OS NameCentOS<  data not available  ><  data not available  ><  data not available  >
OS ReleaseCentOS release 6.10 (Final)<  data not available  ><  data not available  ><  data not available  >
+ \ No newline at end of file diff --git a/SpecialCasesCheck_summary.html b/SpecialCasesCheck_summary.html new file mode 100644 index 0000000..cc69285 --- /dev/null +++ b/SpecialCasesCheck_summary.html @@ -0,0 +1,82 @@ +Xilinx Design Summary + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
SpecialCasesCheck Project Status (08/17/2019 - 16:41:04)
Project File:IEEE754Adder.xiseParser Errors: No Errors
Module Name:SpecialCasesCheckImplementation State:Synthesized
Target Device:xc3s50-5pq208
  • Errors:
 
Product Version:ISE 14.7
  • Warnings:
 
Design Goal:Balanced
  • Routing Results:
 + 
Design Strategy:Xilinx Default (unlocked)
  • Timing Constraints:
 
Environment: + +System Settings +
  • Final Timing Score:
  
+ + + + + + + + + + + + 
+ + + + + + + + + + +
Detailed Reports [-]
Report NameStatusGeneratedErrorsWarningsInfos
Synthesis ReportCurrentSat Aug 17 16:39:00 2019   
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
+ 
+ + +
Secondary Reports [-]
Report NameStatusGenerated
+ + +
Date Generated: 08/17/2019 - 16:41:04
+ \ No newline at end of file diff --git a/SpecialCasesCheck_vhdl.prj b/SpecialCasesCheck_vhdl.prj new file mode 100644 index 0000000..470e8ae --- /dev/null +++ b/SpecialCasesCheck_vhdl.prj @@ -0,0 +1 @@ +vhdl work "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" diff --git a/SpecialCasesCheck_xst.xrpt b/SpecialCasesCheck_xst.xrpt new file mode 100644 index 0000000..2f03108 --- /dev/null +++ b/SpecialCasesCheck_xst.xrpt @@ -0,0 +1,127 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+ + + +
+ + + diff --git a/TypeCheck.bld b/TypeCheck.bld new file mode 100644 index 0000000..f96903b --- /dev/null +++ b/TypeCheck.bld @@ -0,0 +1,34 @@ +Release 14.7 ngdbuild P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Command Line: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/ngdbuild -intstyle +ise -dd _ngo -nt timestamp -i -p xc3s50-pq208-5 TypeCheck.ngc TypeCheck.ngd + +Reading NGO file "/home/Luca/ISE/IEEE754Adder/TypeCheck.ngc" ... +Gathering constraint information from source properties... +Done. + +Resolving constraint associations... +Checking Constraint Associations... +Done... + +Checking expanded design ... + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +NGDBUILD Design Results Summary: + Number of errors: 0 + Number of warnings: 0 + +Total memory usage is 484492 kilobytes + +Writing NGD file "TypeCheck.ngd" ... +Total REAL time to NGDBUILD completion: 2 sec +Total CPU time to NGDBUILD completion: 2 sec + +Writing NGDBUILD log file "TypeCheck.bld"... diff --git a/TypeCheck.cmd_log b/TypeCheck.cmd_log new file mode 100644 index 0000000..ea733e4 --- /dev/null +++ b/TypeCheck.cmd_log @@ -0,0 +1,20 @@ +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s50-pq208-5 TypeCheck.ngc TypeCheck.ngd +map -intstyle ise -p xc3s50-pq208-5 -cm area -ir off -pr off -c 100 -o TypeCheck_map.ncd TypeCheck.ngd TypeCheck.pcf +par -w -intstyle ise -ol high -t 1 TypeCheck_map.ncd TypeCheck.ncd TypeCheck.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml TypeCheck.twx TypeCheck.ncd -o TypeCheck.twr TypeCheck.pcf +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +ngdbuild -intstyle ise -dd _ngo -nt timestamp -i -p xc3s50-pq208-5 TypeCheck.ngc TypeCheck.ngd +map -intstyle ise -p xc3s50-pq208-5 -cm area -ir off -pr off -c 100 -o TypeCheck_map.ncd TypeCheck.ngd TypeCheck.pcf +par -w -intstyle ise -ol high -t 1 TypeCheck_map.ncd TypeCheck.ncd TypeCheck.pcf +trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml TypeCheck.twx TypeCheck.ncd -o TypeCheck.twr TypeCheck.pcf +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" +xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/TypeCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/TypeCheck.syr" diff --git a/TypeCheck.lso b/TypeCheck.lso new file mode 100644 index 0000000..b8f99f5 --- /dev/null +++ b/TypeCheck.lso @@ -0,0 +1 @@ +work diff --git a/TypeCheck.ncd b/TypeCheck.ncd new file mode 100644 index 0000000..de6c70b --- /dev/null +++ b/TypeCheck.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###3168:XlxV32DM 18c0 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All rights reserved. + +Sat Aug 17 16:41:02 2019 + + +# NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +INPUT FILE: TypeCheck_map.ncd +OUTPUT FILE: TypeCheck.pad +PART TYPE: xc3s50 +SPEED GRADE: -5 +PACKAGE: pq208 + +Pinout by Pin Number: + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| +Pin Number|Signal Name|Pin Usage|Pin Name|Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage|Constraint|IO Register|Signal Integrity| +P1|||GND|||||||||||| +P2||DIFFM|IO_L01P_7/VRN_7|UNUSED||7||||||||| +P3||DIFFS|IO_L01N_7/VRP_7|UNUSED||7||||||||| +P4|||NC|||||||||||| +P5|||NC|||||||||||| +P6|||VCCO_7|||7|||||any******|||| +P7||DIFFM|IO_L19P_7|UNUSED||7||||||||| +P8|||GND|||||||||||| +P9||DIFFS|IO_L19N_7/VREF_7|UNUSED||7||||||||| +P10||DIFFM|IO_L20P_7|UNUSED||7||||||||| +P11||DIFFS|IO_L20N_7|UNUSED||7||||||||| +P12||DIFFM|IO_L21P_7|UNUSED||7||||||||| +P13||DIFFS|IO_L21N_7|UNUSED||7||||||||| +P14|||GND|||||||||||| +P15||DIFFM|IO_L22P_7|UNUSED||7||||||||| +P16||DIFFS|IO_L22N_7|UNUSED||7||||||||| +P17|||VCCAUX||||||||2.5|||| +P18||DIFFM|IO_L23P_7|UNUSED||7||||||||| +P19||DIFFS|IO_L23N_7|UNUSED||7||||||||| +P20||DIFFM|IO_L24P_7|UNUSED||7||||||||| +P21||DIFFS|IO_L24N_7|UNUSED||7||||||||| +P22|||NC|||||||||||| +P23|||VCCO_7|||7|||||any******|||| +P24|||NC|||||||||||| +P25|||GND|||||||||||| +P26||DIFFM|IO_L40P_7|UNUSED||7||||||||| +P27||DIFFS|IO_L40N_7/VREF_7|UNUSED||7||||||||| +P28||DIFFM|IO_L40P_6/VREF_6|UNUSED||6||||||||| +P29||DIFFS|IO_L40N_6|UNUSED||6||||||||| +P30|||GND|||||||||||| +P31|||NC|||||||||||| +P32|||VCCO_6|||6|||||any******|||| +P33|||NC|||||||||||| +P34||DIFFM|IO_L24P_6|UNUSED||6||||||||| +P35||DIFFS|IO_L24N_6/VREF_6|UNUSED||6||||||||| +P36||DIFFM|IO_L23P_6|UNUSED||6||||||||| +P37||DIFFS|IO_L23N_6|UNUSED||6||||||||| +P38|||VCCAUX||||||||2.5|||| +P39||DIFFM|IO_L22P_6|UNUSED||6||||||||| +P40||DIFFS|IO_L22N_6|UNUSED||6||||||||| +P41|||GND|||||||||||| +P42||DIFFM|IO_L21P_6|UNUSED||6||||||||| +P43||DIFFS|IO_L21N_6|UNUSED||6||||||||| +P44||DIFFM|IO_L20P_6|UNUSED||6||||||||| +P45||DIFFS|IO_L20N_6|UNUSED||6||||||||| +P46||DIFFM|IO_L19P_6|UNUSED||6||||||||| +P47|||GND|||||||||||| +P48||DIFFS|IO_L19N_6|UNUSED||6||||||||| +P49|||VCCO_6|||6|||||any******|||| +P50|||NC|||||||||||| +P51||DIFFM|IO_L01P_6/VRN_6|UNUSED||6||||||||| +P52||DIFFS|IO_L01N_6/VRP_6|UNUSED||6||||||||| +P53|||GND|||||||||||| +P54|||M1|||||||||||| +P55|||M0|||||||||||| +P56|||M2|||||||||||| +P57||DIFFM|IO_L01P_5/CS_B|UNUSED||5||||||||| +P58||DIFFS|IO_L01N_5/RDWR_B|UNUSED||5||||||||| +P59|||GND|||||||||||| +P60|||VCCO_5|||5|||||any******|||| +P61||DIFFM|IO_L10P_5/VRN_5|UNUSED||5||||||||| +P62||DIFFS|IO_L10N_5/VRP_5|UNUSED||5||||||||| +P63||IOB|IO|UNUSED||5||||||||| +P64||DIFFM|IO_L27P_5|UNUSED||5||||||||| +P65||DIFFS|IO_L27N_5/VREF_5|UNUSED||5||||||||| +P66|||GND|||||||||||| +P67||DIFFM|IO_L28P_5/D7|UNUSED||5||||||||| +P68||DIFFS|IO_L28N_5/D6|UNUSED||5||||||||| +P69|||VCCAUX||||||||2.5|||| +P70|||VCCINT||||||||1.2|||| +P71||IOB|IO|UNUSED||5||||||||| +P72||DIFFM|IO_L31P_5/D5|UNUSED||5||||||||| +P73|||VCCO_5|||5|||||any******|||| +P74||DIFFS|IO_L31N_5/D4|UNUSED||5||||||||| +P75|||GND|||||||||||| +P76||DIFFM|IO_L32P_5/GCLK2|UNUSED||5||||||||| +P77||DIFFS|IO_L32N_5/GCLK3|UNUSED||5||||||||| +P78||IOB|IO/VREF_5|UNUSED||5||||||||| +P79||DIFFM|IO_L32P_4/GCLK0|UNUSED||4||||||||| +P80||DIFFS|IO_L32N_4/GCLK1|UNUSED||4||||||||| +P81||DIFFM|IO_L31P_4/DOUT/BUSY|UNUSED||4||||||||| +P82|||GND|||||||||||| +P83||DIFFS|IO_L31N_4/INIT_B|UNUSED||4||||||||| +P84|||VCCO_4|||4|||||any******|||| +P85||IOB|IO/VREF_4|UNUSED||4||||||||| +P86||DIFFM|IO_L30P_4/D3|UNUSED||4||||||||| +P87||DIFFS|IO_L30N_4/D2|UNUSED||4||||||||| +P88|||VCCINT||||||||1.2|||| +P89|||VCCAUX||||||||2.5|||| +P90||DIFFM|IO_L27P_4/D1|UNUSED||4||||||||| +P91|||GND|||||||||||| +P92||DIFFS|IO_L27N_4/DIN/D0|UNUSED||4||||||||| +P93||IOB|IO|UNUSED||4||||||||| +P94||DIFFM|IO_L25P_4|UNUSED||4||||||||| +P95||DIFFS|IO_L25N_4|UNUSED||4||||||||| +P96|||NC|||||||||||| +P97|||NC|||||||||||| +P98|||VCCO_4|||4|||||any******|||| +P99|||GND|||||||||||| +P100||DIFFM|IO_L01P_4/VRN_4|UNUSED||4||||||||| +P101||DIFFS|IO_L01N_4/VRP_4|UNUSED||4||||||||| +P102||IOB|IO/VREF_4|UNUSED||4||||||||| +P103|||DONE|||||||||||| +P104|||CCLK|||||||||||| +P105|||GND|||||||||||| +P106||DIFFM|IO_L01P_3/VRN_3|UNUSED||3||||||||| +P107||DIFFS|IO_L01N_3/VRP_3|UNUSED||3||||||||| +P108|||NC|||||||||||| +P109|||NC|||||||||||| +P110|||VCCO_3|||3|||||any******|||| +P111||DIFFM|IO_L19P_3|UNUSED||3||||||||| +P112|||GND|||||||||||| +P113||DIFFS|IO_L19N_3|UNUSED||3||||||||| +P114||DIFFM|IO_L20P_3|UNUSED||3||||||||| +P115||DIFFS|IO_L20N_3|UNUSED||3||||||||| +P116||DIFFM|IO_L21P_3|UNUSED||3||||||||| +P117||DIFFS|IO_L21N_3|UNUSED||3||||||||| +P118|||GND|||||||||||| +P119||DIFFM|IO_L22P_3|UNUSED||3||||||||| +P120||DIFFS|IO_L22N_3|UNUSED||3||||||||| +P121|||VCCAUX||||||||2.5|||| +P122||DIFFM|IO_L23P_3/VREF_3|UNUSED||3||||||||| +P123||DIFFS|IO_L23N_3|UNUSED||3||||||||| +P124||DIFFM|IO_L24P_3|UNUSED||3||||||||| +P125||DIFFS|IO_L24N_3|UNUSED||3||||||||| +P126|||NC|||||||||||| +P127|||VCCO_3|||3|||||any******|||| +P128|||NC|||||||||||| +P129|||GND|||||||||||| +P130||DIFFM|IO_L40P_3|UNUSED||3||||||||| +P131||DIFFS|IO_L40N_3/VREF_3|UNUSED||3||||||||| +P132||DIFFM|IO_L40P_2/VREF_2|UNUSED||2||||||||| +P133||DIFFS|IO_L40N_2|UNUSED||2||||||||| +P134|||GND|||||||||||| +P135|||NC|||||||||||| +P136|||VCCO_2|||2|||||any******|||| +P137|||NC|||||||||||| +P138||DIFFM|IO_L24P_2|UNUSED||2||||||||| +P139||DIFFS|IO_L24N_2|UNUSED||2||||||||| +P140||DIFFM|IO_L23P_2|UNUSED||2||||||||| +P141||DIFFS|IO_L23N_2/VREF_2|UNUSED||2||||||||| +P142|||VCCAUX||||||||2.5|||| +P143||DIFFM|IO_L22P_2|UNUSED||2||||||||| +P144||DIFFS|IO_L22N_2|UNUSED||2||||||||| +P145|||GND|||||||||||| +P146||DIFFM|IO_L21P_2|UNUSED||2||||||||| +P147||DIFFS|IO_L21N_2|UNUSED||2||||||||| +P148||DIFFM|IO_L20P_2|UNUSED||2||||||||| +P149||DIFFS|IO_L20N_2|UNUSED||2||||||||| +P150||DIFFM|IO_L19P_2|UNUSED||2||||||||| +P151|||GND|||||||||||| +P152||DIFFS|IO_L19N_2|UNUSED||2||||||||| +P153|||VCCO_2|||2|||||any******|||| +P154|||NC|||||||||||| +P155||DIFFM|IO_L01P_2/VRN_2|UNUSED||2||||||||| +P156||DIFFS|IO_L01N_2/VRP_2|UNUSED||2||||||||| +P157|||GND|||||||||||| +P158|||TDO|||||||||||| +P159|||TCK|||||||||||| +P160|||TMS|||||||||||| +P161||DIFFM|IO_L01P_1/VRN_1|UNUSED||1||||||||| +P162||DIFFS|IO_L01N_1/VRP_1|UNUSED||1||||||||| +P163|||GND|||||||||||| +P164|||VCCO_1|||1|||||any******|||| +P165||DIFFM|IO_L10P_1|UNUSED||1||||||||| +P166||DIFFS|IO_L10N_1/VREF_1|UNUSED||1||||||||| +P167||IOB|IO|UNUSED||1||||||||| +P168||DIFFM|IO_L27P_1|UNUSED||1||||||||| +P169||DIFFS|IO_L27N_1|UNUSED||1||||||||| +P170|||GND|||||||||||| +P171||DIFFM|IO_L28P_1|UNUSED||1||||||||| +P172||DIFFS|IO_L28N_1|UNUSED||1||||||||| +P173|||VCCAUX||||||||2.5|||| +P174|||VCCINT||||||||1.2|||| +P175||IOB|IO|UNUSED||1||||||||| +P176||DIFFM|IO_L31P_1|UNUSED||1||||||||| +P177|||VCCO_1|||1|||||any******|||| +P178||DIFFS|IO_L31N_1/VREF_1|UNUSED||1||||||||| +P179|||GND|||||||||||| +P180||DIFFM|IO_L32P_1/GCLK4|UNUSED||1||||||||| +P181||DIFFS|IO_L32N_1/GCLK5|UNUSED||1||||||||| +P182||IOB|IO|UNUSED||1||||||||| +P183|NaN|IOB|IO_L32P_0/GCLK6|OUTPUT|LVCMOS25*|0|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P184|N<0>|IOB|IO_L32N_0/GCLK7|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE| +P185|N<23>|IOB|IO_L31P_0/VREF_0|INPUT|LVCMOS25*|0||||NONE||UNLOCATED|NO|NONE| +P186|||GND|||||||||||| +P187|INF|IOB|IO_L31N_0|OUTPUT|LVCMOS25*|0|12|SLOW|NONE**|||UNLOCATED|NO|NONE| +P188|||VCCO_0|||0|||||2.50|||| +P189||IOB|IO|UNUSED||0||||||||| +P190||DIFFM|IO_L30P_0|UNUSED||0||||||||| +P191||DIFFS|IO_L30N_0|UNUSED||0||||||||| +P192|||VCCINT||||||||1.2|||| +P193|||VCCAUX||||||||2.5|||| +P194||DIFFM|IO_L27P_0|UNUSED||0||||||||| +P195|||GND|||||||||||| +P196||DIFFS|IO_L27N_0|UNUSED||0||||||||| +P197||IOB|IO|UNUSED||0||||||||| +P198||DIFFM|IO_L25P_0|UNUSED||0||||||||| +P199||DIFFS|IO_L25N_0|UNUSED||0||||||||| +P200|||NC|||||||||||| +P201|||VCCO_0|||0|||||2.50|||| +P202|||GND|||||||||||| +P203||DIFFM|IO_L01P_0/VRN_0|UNUSED||0||||||||| +P204||DIFFS|IO_L01N_0/VRP_0|UNUSED||0||||||||| +P205||IOB|IO/VREF_0|UNUSED||0||||||||| +P206|||HSWAP_EN|||||||||||| +P207|||PROG_B|||||||||||| +P208|||TDI|||||||||||| + +-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----|-----| + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + diff --git a/TypeCheck.par b/TypeCheck.par new file mode 100644 index 0000000..14cb430 --- /dev/null +++ b/TypeCheck.par @@ -0,0 +1,148 @@ +Release 14.7 par P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Xilinx:: Sat Aug 17 16:41:01 2019 + +par -w -intstyle ise -ol high -t 1 TypeCheck_map.ncd TypeCheck.ncd +TypeCheck.pcf + + +Constraints file: TypeCheck.pcf. +Loading device for application Rf_Device from file '3s50.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/. + "TypeCheck" is an NCD, version 3.2, device xc3s50, package pq208, speed -5 + +Initializing temperature to 85.000 Celsius. (default - Range: 0.000 to 85.000 Celsius) +Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.260 Volts) + +INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par + -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all + internal clocks in this design. Because there are not defined timing requirements, a timing score will not be + reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. + Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". + +Device speed data version: "PRODUCTION 1.39 2013-10-13". + + +Device Utilization Summary: + + Number of External IOBs 4 out of 124 3% + Number of LOCed IOBs 0 out of 4 0% + + Number of Slices 2 out of 768 1% + Number of SLICEMs 0 out of 384 0% + + + +Overall effort level (-ol): High +Placer effort level (-pl): High +Placer cost table entry (-t): 1 +Router effort level (-rl): High + +Starting initial Timing Analysis. REAL time: 0 secs +Finished initial Timing Analysis. REAL time: 0 secs + + +Starting Placer +Total REAL time at the beginning of Placer: 0 secs +Total CPU time at the beginning of Placer: 0 secs + +Phase 1.1 Initial Placement Analysis +Phase 1.1 Initial Placement Analysis (Checksum:14) REAL time: 0 secs + +Phase 2.7 Design Feasibility Check +Phase 2.7 Design Feasibility Check (Checksum:14) REAL time: 0 secs + +Phase 3.31 Local Placement Optimization +Phase 3.31 Local Placement Optimization (Checksum:14) REAL time: 0 secs + +Phase 4.2 Initial Clock and IO Placement +... +Phase 4.2 Initial Clock and IO Placement (Checksum:14) REAL time: 0 secs + +Phase 5.36 Local Placement Optimization +Phase 5.36 Local Placement Optimization (Checksum:14) REAL time: 0 secs + +Phase 6.3 Local Placement Optimization +... +Phase 6.3 Local Placement Optimization (Checksum:2a817b) REAL time: 0 secs + +Phase 7.5 Local Placement Optimization +Phase 7.5 Local Placement Optimization (Checksum:2a817b) REAL time: 0 secs + +Phase 8.8 Global Placement +.. +Phase 8.8 Global Placement (Checksum:78ce46) REAL time: 0 secs + +Phase 9.5 Local Placement Optimization +Phase 9.5 Local Placement Optimization (Checksum:78ce46) REAL time: 0 secs + +Phase 10.18 Placement Optimization +Phase 10.18 Placement Optimization (Checksum:78ce46) REAL time: 0 secs + +Phase 11.5 Local Placement Optimization +Phase 11.5 Local Placement Optimization (Checksum:78ce46) REAL time: 0 secs + +Total REAL time to Placer completion: 0 secs +Total CPU time to Placer completion: 0 secs +Writing design to file TypeCheck.ncd + + + +Starting Router + + +Phase 1 : 10 unrouted; REAL time: 0 secs + +Phase 2 : 10 unrouted; REAL time: 0 secs + +Phase 3 : 2 unrouted; REAL time: 0 secs + +Phase 4 : 2 unrouted; (Par is working to improve performance) REAL time: 1 secs + +Phase 5 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs + +Updating file: TypeCheck.ncd with current fully routed design. + +Phase 6 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs + +Phase 7 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs + +Phase 8 : 0 unrouted; (Par is working to improve performance) REAL time: 1 secs + +Total REAL time to Router completion: 1 secs +Total CPU time to Router completion: 1 secs + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Generating "PAR" statistics. + +Timing Score: 0 (Setup: 0, Hold: 0) + + + +Generating Pad Report. + +All signals are completely routed. + +Total REAL time to PAR completion: 1 secs +Total CPU time to PAR completion: 1 secs + +Peak Memory Usage: 600 MB + +Placement: Completed - No errors found. +Routing: Completed - No errors found. + +Number of error messages: 0 +Number of warning messages: 0 +Number of info messages: 1 + +Writing design to file TypeCheck.ncd + + + +PAR done! diff --git a/TypeCheck.pcf b/TypeCheck.pcf new file mode 100644 index 0000000..1e7c8e2 --- /dev/null +++ b/TypeCheck.pcf @@ -0,0 +1,4 @@ +//! ************************************************************************** +// Written by: Map P.20131013 on Sat Aug 17 16:40:58 2019 +//! ************************************************************************** + diff --git a/TypeCheck.prj b/TypeCheck.prj new file mode 100644 index 0000000..9c69a7e --- /dev/null +++ b/TypeCheck.prj @@ -0,0 +1 @@ +vhdl work "SpecialCasesCheck.vhd" diff --git a/TypeCheck.ptwx b/TypeCheck.ptwx new file mode 100644 index 0000000..925a3b4 --- /dev/null +++ b/TypeCheck.ptwx @@ -0,0 +1,332 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> + diff --git a/TypeCheck.stx b/TypeCheck.stx new file mode 100644 index 0000000..e69de29 diff --git a/TypeCheck.syr b/TypeCheck.syr new file mode 100644 index 0000000..812e344 --- /dev/null +++ b/TypeCheck.syr @@ -0,0 +1,296 @@ +Release 14.7 - xst P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +--> +Parameter TMPDIR set to xst/projnav.tmp + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.05 secs + +--> +Parameter xsthdpdir set to xst + + +Total REAL time to Xst completion: 0.00 secs +Total CPU time to Xst completion: 0.05 secs + +--> +Reading design: TypeCheck.prj + +TABLE OF CONTENTS + 1) Synthesis Options Summary + 2) HDL Compilation + 3) Design Hierarchy Analysis + 4) HDL Analysis + 5) HDL Synthesis + 5.1) HDL Synthesis Report + 6) Advanced HDL Synthesis + 6.1) Advanced HDL Synthesis Report + 7) Low Level Synthesis + 8) Partition Report + 9) Final Report + 9.1) Device utilization summary + 9.2) Partition Resource Summary + 9.3) TIMING REPORT + + +========================================================================= +* Synthesis Options Summary * +========================================================================= +---- Source Parameters +Input File Name : "TypeCheck.prj" +Input Format : mixed +Ignore Synthesis Constraint File : NO + +---- Target Parameters +Output File Name : "TypeCheck" +Output Format : NGC +Target Device : xc3s50-5-pq208 + +---- Source Options +Top Module Name : TypeCheck +Automatic FSM Extraction : YES +FSM Encoding Algorithm : Auto +Safe Implementation : No +FSM Style : LUT +RAM Extraction : Yes +RAM Style : Auto +ROM Extraction : Yes +Mux Style : Auto +Decoder Extraction : YES +Priority Encoder Extraction : Yes +Shift Register Extraction : YES +Logical Shifter Extraction : YES +XOR Collapsing : YES +ROM Style : Auto +Mux Extraction : Yes +Resource Sharing : YES +Asynchronous To Synchronous : NO +Multiplier Style : Auto +Automatic Register Balancing : No + +---- Target Options +Add IO Buffers : YES +Global Maximum Fanout : 500 +Add Generic Clock Buffer(BUFG) : 8 +Register Duplication : YES +Slice Packing : YES +Optimize Instantiated Primitives : NO +Use Clock Enable : Yes +Use Synchronous Set : Yes +Use Synchronous Reset : Yes +Pack IO Registers into IOBs : Auto +Equivalent register Removal : YES + +---- General Options +Optimization Goal : Speed +Optimization Effort : 1 +Keep Hierarchy : No +Netlist Hierarchy : As_Optimized +RTL Output : Yes +Global Optimization : AllClockNets +Read Cores : YES +Write Timing Constraints : NO +Cross Clock Analysis : NO +Hierarchy Separator : / +Bus Delimiter : <> +Case Specifier : Maintain +Slice Utilization Ratio : 100 +BRAM Utilization Ratio : 100 +Verilog 2001 : YES +Auto BRAM Packing : NO +Slice Utilization Ratio Delta : 5 + +========================================================================= + + +========================================================================= +* HDL Compilation * +========================================================================= +Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work. +Architecture typecheckarch of Entity typecheck is up to date. + +========================================================================= +* Design Hierarchy Analysis * +========================================================================= +Analyzing hierarchy for entity in library (architecture ). + + +========================================================================= +* HDL Analysis * +========================================================================= +Analyzing Entity in library (Architecture ). +Entity analyzed. Unit generated. + + +========================================================================= +* HDL Synthesis * +========================================================================= + +Performing bidirectional port resolution... + +Synthesizing Unit . + Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd". +WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. +Unit synthesized. + + +========================================================================= +HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Advanced HDL Synthesis * +========================================================================= + + +========================================================================= +Advanced HDL Synthesis Report + +Found no macro +========================================================================= + +========================================================================= +* Low Level Synthesis * +========================================================================= + +Optimizing unit ... + +Mapping all equations... +Building and optimizing final netlist ... +Found area constraint ratio of 100 (+ 5) on block TypeCheck, actual ratio is 0. + +Final Macro Processing ... + +========================================================================= +Final Register Report + +Found no macro +========================================================================= + +========================================================================= +* Partition Report * +========================================================================= + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +========================================================================= +* Final Report * +========================================================================= +Final Results +RTL Top Level Output File Name : TypeCheck.ngr +Top Level Output File Name : TypeCheck +Output Format : NGC +Optimization Goal : Speed +Keep Hierarchy : No + +Design Statistics +# IOs : 34 + +Cell Usage : +# BELS : 18 +# GND : 1 +# LUT3 : 3 +# LUT4 : 7 +# MUXCY : 6 +# VCC : 1 +# IO Buffers : 33 +# IBUF : 31 +# OBUF : 2 +========================================================================= + +Device utilization summary: +--------------------------- + +Selected Device : 3s50pq208-5 + + Number of Slices: 5 out of 768 0% + Number of 4 input LUTs: 10 out of 1536 0% + Number of IOs: 34 + Number of bonded IOBs: 33 out of 124 26% + +--------------------------- +Partition Resource Summary: +--------------------------- + + No Partitions were found in this design. + +--------------------------- + + +========================================================================= +TIMING REPORT + +NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. + FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT + GENERATED AFTER PLACE-and-ROUTE. + +Clock Information: +------------------ +No clock signals found in this design + +Asynchronous Control Signals Information: +---------------------------------------- +No asynchronous control signals found in this design + +Timing Summary: +--------------- +Speed Grade: -5 + + Minimum period: No path found + Minimum input arrival time before clock: No path found + Maximum output required time after clock: No path found + Maximum combinational path delay: 9.965ns + +Timing Detail: +-------------- +All values displayed in nanoseconds (ns) + +========================================================================= +Timing constraint: Default path analysis + Total number of paths / destination ports: 62 / 2 +------------------------------------------------------------------------- +Delay: 9.965ns (Levels of Logic = 10) + Source: N<3> (PAD) + Destination: NaN (PAD) + + Data Path: N<3> to NaN + Gate Net + Cell:in->out fanout Delay Delay Logical Name (Net Name) + ---------------------------------------- ------------ + IBUF:I->O 1 0.715 0.976 N_3_IBUF (N_3_IBUF) + LUT3:I0->O 1 0.479 0.000 T_wg_lut<0> (T_wg_lut<0>) + MUXCY:S->O 1 0.435 0.000 T_wg_cy<0> (T_wg_cy<0>) + MUXCY:CI->O 1 0.056 0.000 T_wg_cy<1> (T_wg_cy<1>) + MUXCY:CI->O 1 0.056 0.000 T_wg_cy<2> (T_wg_cy<2>) + MUXCY:CI->O 1 0.056 0.000 T_wg_cy<3> (T_wg_cy<3>) + MUXCY:CI->O 1 0.056 0.000 T_wg_cy<4> (T_wg_cy<4>) + MUXCY:CI->O 2 0.265 0.804 T_wg_cy<5> (T) + LUT3:I2->O 1 0.479 0.681 NaN1 (NaN_OBUF) + OBUF:I->O 4.909 NaN_OBUF (NaN) + ---------------------------------------- + Total 9.965ns (7.503ns logic, 2.461ns route) + (75.3% logic, 24.7% route) + +========================================================================= + + +Total REAL time to Xst completion: 3.00 secs +Total CPU time to Xst completion: 3.06 secs + +--> + + +Total memory usage is 605836 kilobytes + +Number of errors : 0 ( 0 filtered) +Number of warnings : 1 ( 0 filtered) +Number of infos : 0 ( 0 filtered) + diff --git a/TypeCheck.twr b/TypeCheck.twr new file mode 100644 index 0000000..a242a72 --- /dev/null +++ b/TypeCheck.twr @@ -0,0 +1,63 @@ +-------------------------------------------------------------------------------- +Release 14.7 Trace (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 5 -n +3 -fastpaths -xml TypeCheck.twx TypeCheck.ncd -o TypeCheck.twr TypeCheck.pcf + +Design file: TypeCheck.ncd +Physical constraint file: TypeCheck.pcf +Device,package,speed: xc3s50,pq208,-5 (PRODUCTION 1.39 2013-10-13) +Report level: verbose report + +Environment Variable Effect +-------------------- ------ +NONE No environment variables were set +-------------------------------------------------------------------------------- + +INFO:Timing:2698 - No timing constraints found, doing default enumeration. +INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612). +INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths + option. All paths that are not constrained will be reported in the + unconstrained paths section(s) of the report. +INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on + a 50 Ohm transmission line loading model. For the details of this model, + and for more information on accounting for different loading conditions, + please see the device datasheet. +INFO:Timing:3390 - This architecture does not support a default System Jitter + value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock + Uncertainty calculation. +INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and + 'Phase Error' calculations, these terms will be zero in the Clock + Uncertainty calculation. Please make appropriate modification to + SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase + Error. + + + +Data Sheet report: +----------------- +All values displayed in nanoseconds (ns) + +Pad to Pad +---------------+---------------+---------+ +Source Pad |Destination Pad| Delay | +---------------+---------------+---------+ +N<0> |INF | 7.509| +N<0> |NaN | 7.466| +N<23> |INF | 7.017| +N<23> |NaN | 7.274| +---------------+---------------+---------+ + + +Analysis completed Sat Aug 17 16:41:03 2019 +-------------------------------------------------------------------------------- + +Trace Settings: +------------------------- +Trace Settings + +Peak Memory Usage: 309 MB + + + diff --git a/TypeCheck.twx b/TypeCheck.twx new file mode 100644 index 0000000..dc2aaef --- /dev/null +++ b/TypeCheck.twx @@ -0,0 +1,338 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +]> +Release 14.7 Trace (lin64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved./opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 5 -n +3 -fastpaths -xml TypeCheck.twx TypeCheck.ncd -o TypeCheck.twr TypeCheck.pcf + +TypeCheck.ncdTypeCheck.ncdTypeCheck.pcfTypeCheck.pcfxc3s50-5PRODUCTION 1.39 2013-10-133INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.N<0>INF7.509N<0>NaN7.466N<23>INF7.017N<23>NaN7.274Sat Aug 17 16:41:03 2019 TraceTrace Settings + +Peak Memory Usage: 309 MB + diff --git a/TypeCheck.unroutes b/TypeCheck.unroutes new file mode 100644 index 0000000..e36dc87 --- /dev/null +++ b/TypeCheck.unroutes @@ -0,0 +1,9 @@ +Release 14.7 - par P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Sat Aug 17 16:41:02 2019 + +All signals are completely routed. + + + diff --git a/TypeCheck.xpi b/TypeCheck.xpi new file mode 100644 index 0000000..d043f7f --- /dev/null +++ b/TypeCheck.xpi @@ -0,0 +1,3 @@ +PROGRAM=PAR +STATE=ROUTED +TIMESPECS_MET=OFF diff --git a/TypeCheck.xst b/TypeCheck.xst new file mode 100644 index 0000000..6b00448 --- /dev/null +++ b/TypeCheck.xst @@ -0,0 +1,56 @@ +set -tmpdir "xst/projnav.tmp" +set -xsthdpdir "xst" +run +-ifn TypeCheck.prj +-ifmt mixed +-ofn TypeCheck +-ofmt NGC +-p xc3s50-5-pq208 +-top TypeCheck +-opt_mode Speed +-opt_level 1 +-iuc NO +-keep_hierarchy No +-netlist_hierarchy As_Optimized +-rtlview Yes +-glob_opt AllClockNets +-read_cores YES +-write_timing_constraints NO +-cross_clock_analysis NO +-hierarchy_separator / +-bus_delimiter <> +-case Maintain +-slice_utilization_ratio 100 +-bram_utilization_ratio 100 +-verilog2001 YES +-fsm_extract YES -fsm_encoding Auto +-safe_implementation No +-fsm_style LUT +-ram_extract Yes +-ram_style Auto +-rom_extract Yes +-mux_style Auto +-decoder_extract YES +-priority_extract Yes +-shreg_extract YES +-shift_extract YES +-xor_collapse YES +-rom_style Auto +-auto_bram_packing NO +-mux_extract Yes +-resource_sharing YES +-async_to_sync NO +-mult_style Auto +-iobuf YES +-max_fanout 500 +-bufg 8 +-register_duplication YES +-register_balancing No +-slice_packing YES +-optimize_primitives NO +-use_clock_enable Yes +-use_sync_set Yes +-use_sync_reset Yes +-iob Auto +-equivalent_register_removal YES +-slice_utilization_ratio_maxmargin 5 diff --git a/TypeCheck_guide.ncd b/TypeCheck_guide.ncd new file mode 100644 index 0000000..de6c70b --- /dev/null +++ b/TypeCheck_guide.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###3168:XlxV32DM 18c0 c48eNqNV2t32joW/St84MPM3JXEkizZsm67QsChXgVDwUnT+6Fexo+WmQby6H10Eea3zzmSbWxDbidZSDpbR0dbW9IR9JNiRyzVX+R/rJ/X243XI+d2r0/VGYdPyuBzL9XZevP9+fuPb7lDDu3e+jnvnT30/krZM7fOHh6p5Z7xHgzoJU950jtbP/W2RQEuZZ32iGX1zra96MdDPvyap/+J75OH802aHZDzzZem9ZAWPeCwfoJi+w2Khyeg9d3O1NmfvQ6T7bfe1/WXr72z7z3y91Ok3SmEupgPRoSWNStru6x5pi6Wk2Dox3eEfGIkrU0JFlOwLKbYOcGCgpqMekE4v4m88FdGPOstVQMCH+y6ugkmozgaLMY+FMN3LiDLOAivZ6m6yr8996xzBvRnuba8YHYFnVc318XBnt1EAKQHAChmxtKsJvF12xzDvMPBKL4N/I/xrb9YBrNQquFsOg2iyB85arjwB9DI1HB7/1BTkMbEKdKyaQISNaLqGlZ0TYkaUzWG5pi6ahw/JCA4qVvQHVAVhAw+1zYW0AdlPIMFSAWBL/TiEt0063J0G5Yk1GQ2GPmwG2o6mMfD6WgShH48m0dAf5locDob3Uz8TLejYOovo8F0vtJmuU4YnDzYKvzVesuhJGVFTEVNxUxlm4qbSpjKMZVrKvkWY5nR1MSipWViUROLmljUxKImFjWxqIlFTSwzjFlvHVWeFm0T3cl0aeuS61Lo0tGlq0uJI/3o42zx3lVhbMWBFjeMKdNNpsIktLEA8aHU4lM1A11B8UTNz6lFGLHw1M8Hw/f+iCl9CaBcdGUnXM1Hy/hqMhu+j8fhKL4KwlEQjok8jccL/xoj1X3zyWDoT/0wKhrgzXIw9luhb4fDk6EbuA7dHYNTT8cLstL4aBZGsTnc8U14s/RH8TwIl2Zq0CxegAIQKq2B6NPcT4w1HsXByLjOR9PqPMFR10gQxoPlMhiHMRy2kgaC/l3kh3BqdSRiAut71xTl1h9q9uTQjdMtP4XD5pDmYqshvNFtGMWYRkqNW/gC7hVSggQTjO5WVTscTH1iq/n7eOTrBYTjabyc3SyGfoEomPVVcpW58RdwoKqWXYPjGsRNqpr00LRXqspIF4ODMb4YkKZBm4ZNVJSrqN5V1LHQdklXC2t3EThD/gI2x8C3mJzxMMO5KtrYIspawBSSY8Nezn1IOQZCwYLpHKgFkYkStQ5CVCmuCUyCq6WrojoHli2Qo35rYMM779KXe6LuSKbuArhld2d3oyvIvqS3jG5MY7AcBoFQd9kqDjKgdZfdx9Pk39un2/wJn+sKWm8OkPrkqHhjwR8pGwT0wifZUel99m29yW2FLyVT8G4yBW8zUw/JE1f6CXfVMxjfkw3kA/O000K9jBbBLdyjaHE1u/MIvG+zypjcDqezJeXwOPgfoZh9fHmBY/py7PHykqqXl9GbfwzIvwb0ny9Zbf0XzbrzF7QYWC/7y8sHmarLy7+k8K494ZHdkhKPJZ6wPcJsIgTxKKOrZLeRK4+ojUw9ofoy8aRU+yW1TvjCaWPcS7hnNeGcK3T/f2HxGpwBU8BeZ6r67spzU9Unjgc7smGuxzPuElJI1Wca6zMJw1TfyTzpqD8iwU1IL3k9qKSwLeqD48LM+w8OSrXvOwzcYKYC+/puoYO7uZe4UGVeglJZKJuTVyQS9cNJPJa7UEtdT5jwxK6fEI+rPsxCgJ+XwHdG20sguPASoOpiuX/nOOo3yTy6o+Aovf07UaiJcDymxwNNWB+FXYI59yutFDhChN2jyNSjkOqdyNVvBBdBbG+/5QW4vJNE/e5wj1pKbWkXWXMbkL6TepzBQlaexmgbI4hZbYwCZhdtjCGWtzEbsayNccTSNiYQW7UxB7GkjbmqRd+W7W6JmNvGEsScNrZCjLexFLGOHBlirI3liHUkKhAjHdk0wY5uBMVkHeEIqsk6yhGUk3WkI6gn62hHUFDeEY+goryjHkFJeUczSLcAdkQjqCTvqEZQSi46IGrJO1oSFJN3BdFqdoejnKxLvmht80r3U/zf9d0Ebi3cnAQ2Z0tRH/WLwKBqxTPtBpLvsJ/BZXEopjQYA9zXFCVWW4EbCldIRyUHd1u7wz0TcGgSMyqtgu+ftTvbvYFZaK7egCmE+gyf/bOZWHcJpj7TTO33K33Zjkiv1FrQJmn82tokzTQL17DIDYvVEXcd/Ii7NKPkEXftDtxhMiD4Bsyau5lfd8GyPguK3PW1O+KeHgmenxKcvya4jnpEevWa4NodBc+14GAeBM9LwfOG4Pyk4HlXcHFScOcngvOTgqevCc5LwYURnDcEF6Xgoim43gUBtIThbmvukELW1FwY23Mxn1C8klDJCsSEQJPKgkSyla4mLjNzvDABsZq3U2jetuGdGt6ZWhNehcBkQvQqtpSbtcu8FcMlOgY1MVYmRt6M4VYxtCVUHareOAgJGeozTfBwrg4YB0wiltYYBUzCBj+7sjyplhnroJ97wHBs60RbZqyLAouTAhc/1Zf9RF9xUl/W0uan+han9CUmRnZCX+d1fctMBCFrfaV9wCp9Ja+xI33FCX1FQ9/6ADf0NQee7j7zojrtZdYBDL4DlymnvNSA2Ul1o8vMChhbVWn1sBCw4Xbry5I09hbDUYVJC6evjxVERG9WeldMufEWpbdelG1SnjDe0sQqZxKVGqWTY+CykiYS5pyNq7+G7UzK/t2BXgWgU4PyALo1KA6grEHnAJq8Z86AAW8c4EJ3zGbJyiqyAv6I61j6dwr5ezu3ihTtXAp5yqbS+OeWsE/ZjlXkTRsXvaoJ8gZBCgQpSwoL/uGPu4LrCVe5NIREccpmpX9qGRsnSOsJ2LEC1YDMFTkOkEQTfNUWlrGrFXftRJZ2ucKuXS2oqUBWE7SPFagkqxQoSsmzcsKuXW2paxnCOAEeaL4zefYwgQMTOCzJsoLjAFiL09yzxG2voLKrFXT7i05/ZXfjVQvqxnPKBXbn6/J7bb5qfNcfBShqAaxjAeA51gNIRwDZWUDeWUDeEUB2CHXHy874yu7O341X+VcL7Pq/xr/it8e/y8vhDn6MuwkTae7YYF/t6E6k5osI/OLL1X4n3KYJPvPdB7ielvoAfkQ9EguNR0K0JfHJe5T4gwVc/wfWHr9z \ No newline at end of file diff --git a/TypeCheck_map.map b/TypeCheck_map.map new file mode 100644 index 0000000..043dfe7 --- /dev/null +++ b/TypeCheck_map.map @@ -0,0 +1,61 @@ +Release 14.7 Map P.20131013 (lin64) +Xilinx Map Application Log File for Design 'TypeCheck' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc3s50-pq208-5 -cm area -ir off -pr off -c +100 -o TypeCheck_map.ncd TypeCheck.ngd TypeCheck.pcf +Target Device : xc3s50 +Target Package : pq208 +Target Speed : -5 +Mapper Version : spartan3 -- $Revision: 1.55 $ +Mapped Date : Sat Aug 17 16:40:57 2019 + +Mapping design into LUTs... +Running directed packing... +Running delay-based LUT packing... +Running related packing... +Updating timing models... + +Design Summary +-------------- + +Design Summary: +Number of errors: 0 +Number of warnings: 0 +Logic Utilization: + Number of 4 input LUTs: 4 out of 1,536 1% +Logic Distribution: + Number of occupied Slices: 2 out of 768 1% + Number of Slices containing only related logic: 2 out of 2 100% + Number of Slices containing unrelated logic: 0 out of 2 0% + *See NOTES below for an explanation of the effects of unrelated logic. + Total Number of 4 input LUTs: 4 out of 1,536 1% + Number of bonded IOBs: 4 out of 124 3% + +Average Fanout of Non-Clock Nets: 1.67 + +Peak Memory Usage: 615 MB +Total REAL time to MAP completion: 1 secs +Total CPU time to MAP completion: 1 secs + +NOTES: + + Related logic is defined as being logic that shares connectivity - e.g. two + LUTs are "related" if they share common inputs. When assembling slices, + Map gives priority to combine logic that is related. Doing so results in + the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin packing + unrelated logic into a slice once 99% of the slices are occupied through + related logic packing. + + Note that once logic distribution reaches the 99% level through related + logic packing, this does not mean the device is completely utilized. + Unrelated logic packing will then begin, continuing until all usable LUTs + and FFs are occupied. Depending on your timing budget, increased levels of + unrelated logic packing may adversely affect the overall timing performance + of your design. + +Mapping completed. +See MAP report file "TypeCheck_map.mrp" for details. diff --git a/TypeCheck_map.mrp b/TypeCheck_map.mrp new file mode 100644 index 0000000..72b6fe0 --- /dev/null +++ b/TypeCheck_map.mrp @@ -0,0 +1,147 @@ +Release 14.7 Map P.20131013 (lin64) +Xilinx Mapping Report File for Design 'TypeCheck' + +Design Information +------------------ +Command Line : map -intstyle ise -p xc3s50-pq208-5 -cm area -ir off -pr off -c +100 -o TypeCheck_map.ncd TypeCheck.ngd TypeCheck.pcf +Target Device : xc3s50 +Target Package : pq208 +Target Speed : -5 +Mapper Version : spartan3 -- $Revision: 1.55 $ +Mapped Date : Sat Aug 17 16:40:57 2019 + +Design Summary +-------------- +Number of errors: 0 +Number of warnings: 0 +Logic Utilization: + Number of 4 input LUTs: 4 out of 1,536 1% +Logic Distribution: + Number of occupied Slices: 2 out of 768 1% + Number of Slices containing only related logic: 2 out of 2 100% + Number of Slices containing unrelated logic: 0 out of 2 0% + *See NOTES below for an explanation of the effects of unrelated logic. + Total Number of 4 input LUTs: 4 out of 1,536 1% + Number of bonded IOBs: 4 out of 124 3% + +Average Fanout of Non-Clock Nets: 1.67 + +Peak Memory Usage: 615 MB +Total REAL time to MAP completion: 1 secs +Total CPU time to MAP completion: 1 secs + +NOTES: + + Related logic is defined as being logic that shares connectivity - e.g. two + LUTs are "related" if they share common inputs. When assembling slices, + Map gives priority to combine logic that is related. Doing so results in + the best timing performance. + + Unrelated logic shares no connectivity. Map will only begin packing + unrelated logic into a slice once 99% of the slices are occupied through + related logic packing. + + Note that once logic distribution reaches the 99% level through related + logic packing, this does not mean the device is completely utilized. + Unrelated logic packing will then begin, continuing until all usable LUTs + and FFs are occupied. Depending on your timing budget, increased levels of + unrelated logic packing may adversely affect the overall timing performance + of your design. + +Table of Contents +----------------- +Section 1 - Errors +Section 2 - Warnings +Section 3 - Informational +Section 4 - Removed Logic Summary +Section 5 - Removed Logic +Section 6 - IOB Properties +Section 7 - RPMs +Section 8 - Guide Report +Section 9 - Area Group and Partition Summary +Section 10 - Timing Report +Section 11 - Configuration String Information +Section 12 - Control Set Information +Section 13 - Utilization by Hierarchy + +Section 1 - Errors +------------------ + +Section 2 - Warnings +-------------------- + +Section 3 - Informational +------------------------- +INFO:LIT:243 - Logical network N<31> has no load. +INFO:LIT:395 - The above info message is repeated 29 more times for the + following (max. 5 shown): + N<30>, + N<29>, + N<28>, + N<27>, + N<26> + To see the details of these info messages, please use the -detail switch. +INFO:MapLib:562 - No environment variables are currently set. +INFO:LIT:244 - All of the single ended outputs in this design are using slew + rate limited output drivers. The delay on speed critical single ended outputs + can be dramatically reduced by designating them as fast outputs. + +Section 4 - Removed Logic Summary +--------------------------------- + +Section 5 - Removed Logic +------------------------- + +Section 6 - IOB Properties +-------------------------- + ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB | +| | | | | Term | Strength | Rate | | | Delay | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ +| INF | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | +| N<0> | IOB | INPUT | LVCMOS25 | | | | | | | +| N<23> | IOB | INPUT | LVCMOS25 | | | | | | | +| NaN | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | | ++---------------------------------------------------------------------------------------------------------------------------------------------------------+ + +Section 7 - RPMs +---------------- + +Section 8 - Guide Report +------------------------ +Guide not run on this design. + +Section 9 - Area Group and Partition Summary +-------------------------------------------- + +Partition Implementation Status +------------------------------- + + No Partitions were found in this design. + +------------------------------- + +Area Group Information +---------------------- + + No area groups were found in this design. + +---------------------- + +Section 10 - Timing Report +-------------------------- +This design was not run using timing mode. + +Section 11 - Configuration String Details +----------------------------------------- +Use the "-detail" map option to print out Configuration Strings + +Section 12 - Control Set Information +------------------------------------ +No control set information for this architecture. + +Section 13 - Utilization by Hierarchy +------------------------------------- +Use the "-detail" map option to print out the Utilization by Hierarchy section. diff --git a/TypeCheck_map.ncd b/TypeCheck_map.ncd new file mode 100644 index 0000000..b545e1c --- /dev/null +++ b/TypeCheck_map.ncd @@ -0,0 +1,3 @@ +XILINX-XDB 0.1 STUB 0.1 ASCII +XILINX-XDM V1.6 +###2572:XlxV32DM 12b7 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+ + + + diff --git a/TypeCheck_ngdbuild.xrpt b/TypeCheck_ngdbuild.xrpt new file mode 100644 index 0000000..3646276 --- /dev/null +++ b/TypeCheck_ngdbuild.xrpt @@ -0,0 +1,95 @@ + + + + + + +
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+ + + + diff --git a/TypeCheck_pad.csv b/TypeCheck_pad.csv new file mode 100644 index 0000000..562a506 --- /dev/null +++ b/TypeCheck_pad.csv @@ -0,0 +1,239 @@ +#Release 14.7 - par P.20131013 (lin64) +#Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +#Sat Aug 17 16:41:02 2019 + +# +## NOTE: This file is designed to be imported into a spreadsheet program +# such as Microsoft Excel for viewing, printing and sorting. The | +# character is used as the data field separator. This file is also designed +# to support parsing. +# +#INPUT FILE: TypeCheck_map.ncd +#OUTPUT FILE: TypeCheck_pad.csv +#PART TYPE: xc3s50 +#SPEED GRADE: -5 +#PACKAGE: pq208 +# +# Pinout by Pin Number: +# +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +Pin Number,Signal Name,Pin Usage,Pin Name,Direction,IO Standard,IO Bank Number,Drive (mA),Slew Rate,Termination,IOB Delay,Voltage,Constraint,IO Register,Signal Integrity, +P1,,,GND,,,,,,,,,,,, +P2,,DIFFM,IO_L01P_7/VRN_7,UNUSED,,7,,,,,,,,, +P3,,DIFFS,IO_L01N_7/VRP_7,UNUSED,,7,,,,,,,,, +P4,,,NC,,,,,,,,,,,, +P5,,,NC,,,,,,,,,,,, +P6,,,VCCO_7,,,7,,,,,any******,,,, +P7,,DIFFM,IO_L19P_7,UNUSED,,7,,,,,,,,, +P8,,,GND,,,,,,,,,,,, +P9,,DIFFS,IO_L19N_7/VREF_7,UNUSED,,7,,,,,,,,, +P10,,DIFFM,IO_L20P_7,UNUSED,,7,,,,,,,,, +P11,,DIFFS,IO_L20N_7,UNUSED,,7,,,,,,,,, +P12,,DIFFM,IO_L21P_7,UNUSED,,7,,,,,,,,, +P13,,DIFFS,IO_L21N_7,UNUSED,,7,,,,,,,,, +P14,,,GND,,,,,,,,,,,, +P15,,DIFFM,IO_L22P_7,UNUSED,,7,,,,,,,,, +P16,,DIFFS,IO_L22N_7,UNUSED,,7,,,,,,,,, +P17,,,VCCAUX,,,,,,,,2.5,,,, +P18,,DIFFM,IO_L23P_7,UNUSED,,7,,,,,,,,, +P19,,DIFFS,IO_L23N_7,UNUSED,,7,,,,,,,,, +P20,,DIFFM,IO_L24P_7,UNUSED,,7,,,,,,,,, +P21,,DIFFS,IO_L24N_7,UNUSED,,7,,,,,,,,, +P22,,,NC,,,,,,,,,,,, +P23,,,VCCO_7,,,7,,,,,any******,,,, +P24,,,NC,,,,,,,,,,,, +P25,,,GND,,,,,,,,,,,, +P26,,DIFFM,IO_L40P_7,UNUSED,,7,,,,,,,,, +P27,,DIFFS,IO_L40N_7/VREF_7,UNUSED,,7,,,,,,,,, +P28,,DIFFM,IO_L40P_6/VREF_6,UNUSED,,6,,,,,,,,, +P29,,DIFFS,IO_L40N_6,UNUSED,,6,,,,,,,,, +P30,,,GND,,,,,,,,,,,, +P31,,,NC,,,,,,,,,,,, +P32,,,VCCO_6,,,6,,,,,any******,,,, +P33,,,NC,,,,,,,,,,,, +P34,,DIFFM,IO_L24P_6,UNUSED,,6,,,,,,,,, +P35,,DIFFS,IO_L24N_6/VREF_6,UNUSED,,6,,,,,,,,, +P36,,DIFFM,IO_L23P_6,UNUSED,,6,,,,,,,,, +P37,,DIFFS,IO_L23N_6,UNUSED,,6,,,,,,,,, +P38,,,VCCAUX,,,,,,,,2.5,,,, +P39,,DIFFM,IO_L22P_6,UNUSED,,6,,,,,,,,, +P40,,DIFFS,IO_L22N_6,UNUSED,,6,,,,,,,,, +P41,,,GND,,,,,,,,,,,, +P42,,DIFFM,IO_L21P_6,UNUSED,,6,,,,,,,,, +P43,,DIFFS,IO_L21N_6,UNUSED,,6,,,,,,,,, +P44,,DIFFM,IO_L20P_6,UNUSED,,6,,,,,,,,, +P45,,DIFFS,IO_L20N_6,UNUSED,,6,,,,,,,,, +P46,,DIFFM,IO_L19P_6,UNUSED,,6,,,,,,,,, +P47,,,GND,,,,,,,,,,,, +P48,,DIFFS,IO_L19N_6,UNUSED,,6,,,,,,,,, +P49,,,VCCO_6,,,6,,,,,any******,,,, +P50,,,NC,,,,,,,,,,,, +P51,,DIFFM,IO_L01P_6/VRN_6,UNUSED,,6,,,,,,,,, +P52,,DIFFS,IO_L01N_6/VRP_6,UNUSED,,6,,,,,,,,, +P53,,,GND,,,,,,,,,,,, +P54,,,M1,,,,,,,,,,,, +P55,,,M0,,,,,,,,,,,, +P56,,,M2,,,,,,,,,,,, +P57,,DIFFM,IO_L01P_5/CS_B,UNUSED,,5,,,,,,,,, +P58,,DIFFS,IO_L01N_5/RDWR_B,UNUSED,,5,,,,,,,,, +P59,,,GND,,,,,,,,,,,, +P60,,,VCCO_5,,,5,,,,,any******,,,, +P61,,DIFFM,IO_L10P_5/VRN_5,UNUSED,,5,,,,,,,,, +P62,,DIFFS,IO_L10N_5/VRP_5,UNUSED,,5,,,,,,,,, +P63,,IOB,IO,UNUSED,,5,,,,,,,,, +P64,,DIFFM,IO_L27P_5,UNUSED,,5,,,,,,,,, +P65,,DIFFS,IO_L27N_5/VREF_5,UNUSED,,5,,,,,,,,, +P66,,,GND,,,,,,,,,,,, +P67,,DIFFM,IO_L28P_5/D7,UNUSED,,5,,,,,,,,, +P68,,DIFFS,IO_L28N_5/D6,UNUSED,,5,,,,,,,,, +P69,,,VCCAUX,,,,,,,,2.5,,,, +P70,,,VCCINT,,,,,,,,1.2,,,, +P71,,IOB,IO,UNUSED,,5,,,,,,,,, +P72,,DIFFM,IO_L31P_5/D5,UNUSED,,5,,,,,,,,, +P73,,,VCCO_5,,,5,,,,,any******,,,, +P74,,DIFFS,IO_L31N_5/D4,UNUSED,,5,,,,,,,,, +P75,,,GND,,,,,,,,,,,, +P76,,DIFFM,IO_L32P_5/GCLK2,UNUSED,,5,,,,,,,,, +P77,,DIFFS,IO_L32N_5/GCLK3,UNUSED,,5,,,,,,,,, +P78,,IOB,IO/VREF_5,UNUSED,,5,,,,,,,,, +P79,,DIFFM,IO_L32P_4/GCLK0,UNUSED,,4,,,,,,,,, +P80,,DIFFS,IO_L32N_4/GCLK1,UNUSED,,4,,,,,,,,, +P81,,DIFFM,IO_L31P_4/DOUT/BUSY,UNUSED,,4,,,,,,,,, +P82,,,GND,,,,,,,,,,,, +P83,,DIFFS,IO_L31N_4/INIT_B,UNUSED,,4,,,,,,,,, +P84,,,VCCO_4,,,4,,,,,any******,,,, +P85,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,, +P86,,DIFFM,IO_L30P_4/D3,UNUSED,,4,,,,,,,,, +P87,,DIFFS,IO_L30N_4/D2,UNUSED,,4,,,,,,,,, +P88,,,VCCINT,,,,,,,,1.2,,,, +P89,,,VCCAUX,,,,,,,,2.5,,,, +P90,,DIFFM,IO_L27P_4/D1,UNUSED,,4,,,,,,,,, +P91,,,GND,,,,,,,,,,,, +P92,,DIFFS,IO_L27N_4/DIN/D0,UNUSED,,4,,,,,,,,, +P93,,IOB,IO,UNUSED,,4,,,,,,,,, +P94,,DIFFM,IO_L25P_4,UNUSED,,4,,,,,,,,, +P95,,DIFFS,IO_L25N_4,UNUSED,,4,,,,,,,,, +P96,,,NC,,,,,,,,,,,, +P97,,,NC,,,,,,,,,,,, +P98,,,VCCO_4,,,4,,,,,any******,,,, +P99,,,GND,,,,,,,,,,,, +P100,,DIFFM,IO_L01P_4/VRN_4,UNUSED,,4,,,,,,,,, +P101,,DIFFS,IO_L01N_4/VRP_4,UNUSED,,4,,,,,,,,, +P102,,IOB,IO/VREF_4,UNUSED,,4,,,,,,,,, +P103,,,DONE,,,,,,,,,,,, +P104,,,CCLK,,,,,,,,,,,, +P105,,,GND,,,,,,,,,,,, +P106,,DIFFM,IO_L01P_3/VRN_3,UNUSED,,3,,,,,,,,, +P107,,DIFFS,IO_L01N_3/VRP_3,UNUSED,,3,,,,,,,,, +P108,,,NC,,,,,,,,,,,, +P109,,,NC,,,,,,,,,,,, +P110,,,VCCO_3,,,3,,,,,any******,,,, +P111,,DIFFM,IO_L19P_3,UNUSED,,3,,,,,,,,, +P112,,,GND,,,,,,,,,,,, +P113,,DIFFS,IO_L19N_3,UNUSED,,3,,,,,,,,, +P114,,DIFFM,IO_L20P_3,UNUSED,,3,,,,,,,,, +P115,,DIFFS,IO_L20N_3,UNUSED,,3,,,,,,,,, +P116,,DIFFM,IO_L21P_3,UNUSED,,3,,,,,,,,, +P117,,DIFFS,IO_L21N_3,UNUSED,,3,,,,,,,,, +P118,,,GND,,,,,,,,,,,, +P119,,DIFFM,IO_L22P_3,UNUSED,,3,,,,,,,,, +P120,,DIFFS,IO_L22N_3,UNUSED,,3,,,,,,,,, +P121,,,VCCAUX,,,,,,,,2.5,,,, +P122,,DIFFM,IO_L23P_3/VREF_3,UNUSED,,3,,,,,,,,, +P123,,DIFFS,IO_L23N_3,UNUSED,,3,,,,,,,,, +P124,,DIFFM,IO_L24P_3,UNUSED,,3,,,,,,,,, +P125,,DIFFS,IO_L24N_3,UNUSED,,3,,,,,,,,, +P126,,,NC,,,,,,,,,,,, +P127,,,VCCO_3,,,3,,,,,any******,,,, +P128,,,NC,,,,,,,,,,,, +P129,,,GND,,,,,,,,,,,, +P130,,DIFFM,IO_L40P_3,UNUSED,,3,,,,,,,,, +P131,,DIFFS,IO_L40N_3/VREF_3,UNUSED,,3,,,,,,,,, +P132,,DIFFM,IO_L40P_2/VREF_2,UNUSED,,2,,,,,,,,, +P133,,DIFFS,IO_L40N_2,UNUSED,,2,,,,,,,,, +P134,,,GND,,,,,,,,,,,, +P135,,,NC,,,,,,,,,,,, +P136,,,VCCO_2,,,2,,,,,any******,,,, +P137,,,NC,,,,,,,,,,,, +P138,,DIFFM,IO_L24P_2,UNUSED,,2,,,,,,,,, +P139,,DIFFS,IO_L24N_2,UNUSED,,2,,,,,,,,, +P140,,DIFFM,IO_L23P_2,UNUSED,,2,,,,,,,,, +P141,,DIFFS,IO_L23N_2/VREF_2,UNUSED,,2,,,,,,,,, +P142,,,VCCAUX,,,,,,,,2.5,,,, +P143,,DIFFM,IO_L22P_2,UNUSED,,2,,,,,,,,, +P144,,DIFFS,IO_L22N_2,UNUSED,,2,,,,,,,,, +P145,,,GND,,,,,,,,,,,, +P146,,DIFFM,IO_L21P_2,UNUSED,,2,,,,,,,,, +P147,,DIFFS,IO_L21N_2,UNUSED,,2,,,,,,,,, +P148,,DIFFM,IO_L20P_2,UNUSED,,2,,,,,,,,, +P149,,DIFFS,IO_L20N_2,UNUSED,,2,,,,,,,,, +P150,,DIFFM,IO_L19P_2,UNUSED,,2,,,,,,,,, +P151,,,GND,,,,,,,,,,,, +P152,,DIFFS,IO_L19N_2,UNUSED,,2,,,,,,,,, +P153,,,VCCO_2,,,2,,,,,any******,,,, +P154,,,NC,,,,,,,,,,,, +P155,,DIFFM,IO_L01P_2/VRN_2,UNUSED,,2,,,,,,,,, +P156,,DIFFS,IO_L01N_2/VRP_2,UNUSED,,2,,,,,,,,, +P157,,,GND,,,,,,,,,,,, +P158,,,TDO,,,,,,,,,,,, +P159,,,TCK,,,,,,,,,,,, +P160,,,TMS,,,,,,,,,,,, +P161,,DIFFM,IO_L01P_1/VRN_1,UNUSED,,1,,,,,,,,, +P162,,DIFFS,IO_L01N_1/VRP_1,UNUSED,,1,,,,,,,,, +P163,,,GND,,,,,,,,,,,, +P164,,,VCCO_1,,,1,,,,,any******,,,, +P165,,DIFFM,IO_L10P_1,UNUSED,,1,,,,,,,,, +P166,,DIFFS,IO_L10N_1/VREF_1,UNUSED,,1,,,,,,,,, +P167,,IOB,IO,UNUSED,,1,,,,,,,,, +P168,,DIFFM,IO_L27P_1,UNUSED,,1,,,,,,,,, +P169,,DIFFS,IO_L27N_1,UNUSED,,1,,,,,,,,, +P170,,,GND,,,,,,,,,,,, +P171,,DIFFM,IO_L28P_1,UNUSED,,1,,,,,,,,, +P172,,DIFFS,IO_L28N_1,UNUSED,,1,,,,,,,,, +P173,,,VCCAUX,,,,,,,,2.5,,,, +P174,,,VCCINT,,,,,,,,1.2,,,, +P175,,IOB,IO,UNUSED,,1,,,,,,,,, +P176,,DIFFM,IO_L31P_1,UNUSED,,1,,,,,,,,, +P177,,,VCCO_1,,,1,,,,,any******,,,, +P178,,DIFFS,IO_L31N_1/VREF_1,UNUSED,,1,,,,,,,,, +P179,,,GND,,,,,,,,,,,, +P180,,DIFFM,IO_L32P_1/GCLK4,UNUSED,,1,,,,,,,,, +P181,,DIFFS,IO_L32N_1/GCLK5,UNUSED,,1,,,,,,,,, +P182,,IOB,IO,UNUSED,,1,,,,,,,,, +P183,NaN,IOB,IO_L32P_0/GCLK6,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, +P184,N<0>,IOB,IO_L32N_0/GCLK7,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE, +P185,N<23>,IOB,IO_L31P_0/VREF_0,INPUT,LVCMOS25*,0,,,,NONE,,UNLOCATED,NO,NONE, +P186,,,GND,,,,,,,,,,,, +P187,INF,IOB,IO_L31N_0,OUTPUT,LVCMOS25*,0,12,SLOW,NONE**,,,UNLOCATED,NO,NONE, +P188,,,VCCO_0,,,0,,,,,2.50,,,, +P189,,IOB,IO,UNUSED,,0,,,,,,,,, +P190,,DIFFM,IO_L30P_0,UNUSED,,0,,,,,,,,, +P191,,DIFFS,IO_L30N_0,UNUSED,,0,,,,,,,,, +P192,,,VCCINT,,,,,,,,1.2,,,, +P193,,,VCCAUX,,,,,,,,2.5,,,, +P194,,DIFFM,IO_L27P_0,UNUSED,,0,,,,,,,,, +P195,,,GND,,,,,,,,,,,, +P196,,DIFFS,IO_L27N_0,UNUSED,,0,,,,,,,,, +P197,,IOB,IO,UNUSED,,0,,,,,,,,, +P198,,DIFFM,IO_L25P_0,UNUSED,,0,,,,,,,,, +P199,,DIFFS,IO_L25N_0,UNUSED,,0,,,,,,,,, +P200,,,NC,,,,,,,,,,,, +P201,,,VCCO_0,,,0,,,,,2.50,,,, +P202,,,GND,,,,,,,,,,,, +P203,,DIFFM,IO_L01P_0/VRN_0,UNUSED,,0,,,,,,,,, +P204,,DIFFS,IO_L01N_0/VRP_0,UNUSED,,0,,,,,,,,, +P205,,IOB,IO/VREF_0,UNUSED,,0,,,,,,,,, +P206,,,HSWAP_EN,,,,,,,,,,,, +P207,,,PROG_B,,,,,,,,,,,, +P208,,,TDI,,,,,,,,,,,, + +# -----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----,-----, +# +#* Default value. +#** This default Pullup/Pulldown value can be overridden in Bitgen. +#****** Special VCCO requirements may apply. Please consult the device +# family datasheet for specific guideline on VCCO requirements. +# +# +# \ No newline at end of file diff --git a/TypeCheck_pad.txt b/TypeCheck_pad.txt new file mode 100644 index 0000000..88d6681 --- /dev/null +++ b/TypeCheck_pad.txt @@ -0,0 +1,238 @@ +Release 14.7 - par P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Sat Aug 17 16:41:02 2019 + + +INFO: The IO information is provided in three file formats as part of the Place and Route (PAR) process. These formats are: +1. The _pad.txt file (this file) designed to provide information on IO usage in a human readable ASCII text format viewable through common text editors. +2. The _pad.csv file for use with spreadsheet programs such as MS Excel. This file can also be read by PACE to communicate post PAR IO information. +3. The .pad file designed for parsing by customers. It uses the "|" as a data field separator. + +INPUT FILE: TypeCheck_map.ncd +OUTPUT FILE: TypeCheck_pad.txt +PART TYPE: xc3s50 +SPEED GRADE: -5 +PACKAGE: pq208 + +Pinout by Pin Number: + ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|Pin Number|Signal Name|Pin Usage|Pin Name |Direction|IO Standard|IO Bank Number|Drive (mA)|Slew Rate|Termination|IOB Delay|Voltage |Constraint|IO Register|Signal Integrity| ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ +|P1 | | |GND | | | | | | | | | | | | +|P2 | |DIFFM |IO_L01P_7/VRN_7 |UNUSED | |7 | | | | | | | | | +|P3 | |DIFFS |IO_L01N_7/VRP_7 |UNUSED | |7 | | | | | | | | | +|P4 | | |NC | | | | | | | | | | | | +|P5 | | |NC | | | | | | | | | | | | +|P6 | | |VCCO_7 | | |7 | | | | |any******| | | | +|P7 | |DIFFM |IO_L19P_7 |UNUSED | |7 | | | | | | | | | +|P8 | | |GND | | | | | | | | | | | | +|P9 | |DIFFS |IO_L19N_7/VREF_7 |UNUSED | |7 | | | | | | | | | +|P10 | |DIFFM |IO_L20P_7 |UNUSED | |7 | | | | | | | | | +|P11 | |DIFFS |IO_L20N_7 |UNUSED | |7 | | | | | | | | | +|P12 | |DIFFM |IO_L21P_7 |UNUSED | |7 | | | | | | | | | +|P13 | |DIFFS |IO_L21N_7 |UNUSED | |7 | | | | | | | | | +|P14 | | |GND | | | | | | | | | | | | +|P15 | |DIFFM |IO_L22P_7 |UNUSED | |7 | | | | | | | | | +|P16 | |DIFFS |IO_L22N_7 |UNUSED | |7 | | | | | | | | | +|P17 | | |VCCAUX | | | | | | | |2.5 | | | | +|P18 | |DIFFM |IO_L23P_7 |UNUSED | |7 | | | | | | | | | +|P19 | |DIFFS |IO_L23N_7 |UNUSED | |7 | | | | | | | | | +|P20 | |DIFFM |IO_L24P_7 |UNUSED | |7 | | | | | | | | | +|P21 | |DIFFS |IO_L24N_7 |UNUSED | |7 | | | | | | | | | +|P22 | | |NC | | | | | | | | | | | | +|P23 | | |VCCO_7 | | |7 | | | | |any******| | | | +|P24 | | |NC | | | | | | | | | | | | +|P25 | | |GND | | | | | | | | | | | | +|P26 | |DIFFM |IO_L40P_7 |UNUSED | |7 | | | | | | | | | +|P27 | |DIFFS |IO_L40N_7/VREF_7 |UNUSED | |7 | | | | | | | | | +|P28 | |DIFFM |IO_L40P_6/VREF_6 |UNUSED | |6 | | | | | | | | | +|P29 | |DIFFS |IO_L40N_6 |UNUSED | |6 | | | | | | | | | +|P30 | | |GND | | | | | | | | | | | | +|P31 | | |NC | | | | | | | | | | | | +|P32 | | |VCCO_6 | | |6 | | | | |any******| | | | +|P33 | | |NC | | | | | | | | | | | | +|P34 | |DIFFM |IO_L24P_6 |UNUSED | |6 | | | | | | | | | +|P35 | |DIFFS |IO_L24N_6/VREF_6 |UNUSED | |6 | | | | | | | | | +|P36 | |DIFFM |IO_L23P_6 |UNUSED | |6 | | | | | | | | | +|P37 | |DIFFS |IO_L23N_6 |UNUSED | |6 | | | | | | | | | +|P38 | | |VCCAUX | | | | | | | |2.5 | | | | +|P39 | |DIFFM |IO_L22P_6 |UNUSED | |6 | | | | | | | | | +|P40 | |DIFFS |IO_L22N_6 |UNUSED | |6 | | | | | | | | | +|P41 | | |GND | | | | | | | | | | | | +|P42 | |DIFFM |IO_L21P_6 |UNUSED | |6 | | | | | | | | | +|P43 | |DIFFS |IO_L21N_6 |UNUSED | |6 | | | | | | | | | +|P44 | |DIFFM |IO_L20P_6 |UNUSED | |6 | | | | | | | | | +|P45 | |DIFFS |IO_L20N_6 |UNUSED | |6 | | | | | | | | | +|P46 | |DIFFM |IO_L19P_6 |UNUSED | |6 | | | | | | | | | +|P47 | | |GND | | | | | | | | | | | | +|P48 | |DIFFS |IO_L19N_6 |UNUSED | |6 | | | | | | | | | +|P49 | | |VCCO_6 | | |6 | | | | |any******| | | | +|P50 | | |NC | | | | | | | | | | | | +|P51 | |DIFFM |IO_L01P_6/VRN_6 |UNUSED | |6 | | | | | | | | | +|P52 | |DIFFS |IO_L01N_6/VRP_6 |UNUSED | |6 | | | | | | | | | +|P53 | | |GND | | | | | | | | | | | | +|P54 | | |M1 | | | | | | | | | | | | +|P55 | | |M0 | | | | | | | | | | | | +|P56 | | |M2 | | | | | | | | | | | | +|P57 | |DIFFM |IO_L01P_5/CS_B |UNUSED | |5 | | | | | | | | | +|P58 | |DIFFS |IO_L01N_5/RDWR_B |UNUSED | |5 | | | | | | | | | +|P59 | | |GND | | | | | | | | | | | | +|P60 | | |VCCO_5 | | |5 | | | | |any******| | | | +|P61 | |DIFFM |IO_L10P_5/VRN_5 |UNUSED | |5 | | | | | | | | | +|P62 | |DIFFS |IO_L10N_5/VRP_5 |UNUSED | |5 | | | | | | | | | +|P63 | |IOB |IO |UNUSED | |5 | | | | | | | | | +|P64 | |DIFFM |IO_L27P_5 |UNUSED | |5 | | | | | | | | | +|P65 | |DIFFS |IO_L27N_5/VREF_5 |UNUSED | |5 | | | | | | | | | +|P66 | | |GND | | | | | | | | | | | | +|P67 | |DIFFM |IO_L28P_5/D7 |UNUSED | |5 | | | | | | | | | +|P68 | |DIFFS |IO_L28N_5/D6 |UNUSED | |5 | | | | | | | | | +|P69 | | |VCCAUX | | | | | | | |2.5 | | | | +|P70 | | |VCCINT | | | | | | | |1.2 | | | | +|P71 | |IOB |IO |UNUSED | |5 | | | | | | | | | +|P72 | |DIFFM |IO_L31P_5/D5 |UNUSED | |5 | | | | | | | | | +|P73 | | |VCCO_5 | | |5 | | | | |any******| | | | +|P74 | |DIFFS |IO_L31N_5/D4 |UNUSED | |5 | | | | | | | | | +|P75 | | |GND | | | | | | | | | | | | +|P76 | |DIFFM |IO_L32P_5/GCLK2 |UNUSED | |5 | | | | | | | | | +|P77 | |DIFFS |IO_L32N_5/GCLK3 |UNUSED | |5 | | | | | | | | | +|P78 | |IOB |IO/VREF_5 |UNUSED | |5 | | | | | | | | | +|P79 | |DIFFM |IO_L32P_4/GCLK0 |UNUSED | |4 | | | | | | | | | +|P80 | |DIFFS |IO_L32N_4/GCLK1 |UNUSED | |4 | | | | | | | | | +|P81 | |DIFFM |IO_L31P_4/DOUT/BUSY|UNUSED | |4 | | | | | | | | | +|P82 | | |GND | | | | | | | | | | | | +|P83 | |DIFFS |IO_L31N_4/INIT_B |UNUSED | |4 | | | | | | | | | +|P84 | | |VCCO_4 | | |4 | | | | |any******| | | | +|P85 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | +|P86 | |DIFFM |IO_L30P_4/D3 |UNUSED | |4 | | | | | | | | | +|P87 | |DIFFS |IO_L30N_4/D2 |UNUSED | |4 | | | | | | | | | +|P88 | | |VCCINT | | | | | | | |1.2 | | | | +|P89 | | |VCCAUX | | | | | | | |2.5 | | | | +|P90 | |DIFFM |IO_L27P_4/D1 |UNUSED | |4 | | | | | | | | | +|P91 | | |GND | | | | | | | | | | | | +|P92 | |DIFFS |IO_L27N_4/DIN/D0 |UNUSED | |4 | | | | | | | | | +|P93 | |IOB |IO |UNUSED | |4 | | | | | | | | | +|P94 | |DIFFM |IO_L25P_4 |UNUSED | |4 | | | | | | | | | +|P95 | |DIFFS |IO_L25N_4 |UNUSED | |4 | | | | | | | | | +|P96 | | |NC | | | | | | | | | | | | +|P97 | | |NC | | | | | | | | | | | | +|P98 | | |VCCO_4 | | |4 | | | | |any******| | | | +|P99 | | |GND | | | | | | | | | | | | +|P100 | |DIFFM |IO_L01P_4/VRN_4 |UNUSED | |4 | | | | | | | | | +|P101 | |DIFFS |IO_L01N_4/VRP_4 |UNUSED | |4 | | | | | | | | | +|P102 | |IOB |IO/VREF_4 |UNUSED | |4 | | | | | | | | | +|P103 | | |DONE | | | | | | | | | | | | +|P104 | | |CCLK | | | | | | | | | | | | +|P105 | | |GND | | | | | | | | | | | | +|P106 | |DIFFM |IO_L01P_3/VRN_3 |UNUSED | |3 | | | | | | | | | +|P107 | |DIFFS |IO_L01N_3/VRP_3 |UNUSED | |3 | | | | | | | | | +|P108 | | |NC | | | | | | | | | | | | +|P109 | | |NC | | | | | | | | | | | | +|P110 | | |VCCO_3 | | |3 | | | | |any******| | | | +|P111 | |DIFFM |IO_L19P_3 |UNUSED | |3 | | | | | | | | | +|P112 | | |GND | | | | | | | | | | | | +|P113 | |DIFFS |IO_L19N_3 |UNUSED | |3 | | | | | | | | | +|P114 | |DIFFM |IO_L20P_3 |UNUSED | |3 | | | | | | | | | +|P115 | |DIFFS |IO_L20N_3 |UNUSED | |3 | | | | | | | | | +|P116 | |DIFFM |IO_L21P_3 |UNUSED | |3 | | | | | | | | | +|P117 | |DIFFS |IO_L21N_3 |UNUSED | |3 | | | | | | | | | +|P118 | | |GND | | | | | | | | | | | | +|P119 | |DIFFM |IO_L22P_3 |UNUSED | |3 | | | | | | | | | +|P120 | |DIFFS |IO_L22N_3 |UNUSED | |3 | | | | | | | | | +|P121 | | |VCCAUX | | | | | | | |2.5 | | | | +|P122 | |DIFFM |IO_L23P_3/VREF_3 |UNUSED | |3 | | | | | | | | | +|P123 | |DIFFS |IO_L23N_3 |UNUSED | |3 | | | | | | | | | +|P124 | |DIFFM |IO_L24P_3 |UNUSED | |3 | | | | | | | | | +|P125 | |DIFFS |IO_L24N_3 |UNUSED | |3 | | | | | | | | | +|P126 | | |NC | | | | | | | | | | | | +|P127 | | |VCCO_3 | | |3 | | | | |any******| | | | +|P128 | | |NC | | | | | | | | | | | | +|P129 | | |GND | | | | | | | | | | | | +|P130 | |DIFFM |IO_L40P_3 |UNUSED | |3 | | | | | | | | | +|P131 | |DIFFS |IO_L40N_3/VREF_3 |UNUSED | |3 | | | | | | | | | +|P132 | |DIFFM |IO_L40P_2/VREF_2 |UNUSED | |2 | | | | | | | | | +|P133 | |DIFFS |IO_L40N_2 |UNUSED | |2 | | | | | | | | | +|P134 | | |GND | | | | | | | | | | | | +|P135 | | |NC | | | | | | | | | | | | +|P136 | | |VCCO_2 | | |2 | | | | |any******| | | | +|P137 | | |NC | | | | | | | | | | | | +|P138 | |DIFFM |IO_L24P_2 |UNUSED | |2 | | | | | | | | | +|P139 | |DIFFS |IO_L24N_2 |UNUSED | |2 | | | | | | | | | +|P140 | |DIFFM |IO_L23P_2 |UNUSED | |2 | | | | | | | | | +|P141 | |DIFFS |IO_L23N_2/VREF_2 |UNUSED | |2 | | | | | | | | | +|P142 | | |VCCAUX | | | | | | | |2.5 | | | | +|P143 | |DIFFM |IO_L22P_2 |UNUSED | |2 | | | | | | | | | +|P144 | |DIFFS |IO_L22N_2 |UNUSED | |2 | | | | | | | | | +|P145 | | |GND | | | | | | | | | | | | +|P146 | |DIFFM |IO_L21P_2 |UNUSED | |2 | | | | | | | | | +|P147 | |DIFFS |IO_L21N_2 |UNUSED | |2 | | | | | | | | | +|P148 | |DIFFM |IO_L20P_2 |UNUSED | |2 | | | | | | | | | +|P149 | |DIFFS |IO_L20N_2 |UNUSED | |2 | | | | | | | | | +|P150 | |DIFFM |IO_L19P_2 |UNUSED | |2 | | | | | | | | | +|P151 | | |GND | | | | | | | | | | | | +|P152 | |DIFFS |IO_L19N_2 |UNUSED | |2 | | | | | | | | | +|P153 | | |VCCO_2 | | |2 | | | | |any******| | | | +|P154 | | |NC | | | | | | | | | | | | +|P155 | |DIFFM |IO_L01P_2/VRN_2 |UNUSED | |2 | | | | | | | | | +|P156 | |DIFFS |IO_L01N_2/VRP_2 |UNUSED | |2 | | | | | | | | | +|P157 | | |GND | | | | | | | | | | | | +|P158 | | |TDO | | | | | | | | | | | | +|P159 | | |TCK | | | | | | | | | | | | +|P160 | | |TMS | | | | | | | | | | | | +|P161 | |DIFFM |IO_L01P_1/VRN_1 |UNUSED | |1 | | | | | | | | | +|P162 | |DIFFS |IO_L01N_1/VRP_1 |UNUSED | |1 | | | | | | | | | +|P163 | | |GND | | | | | | | | | | | | +|P164 | | |VCCO_1 | | |1 | | | | |any******| | | | +|P165 | |DIFFM |IO_L10P_1 |UNUSED | |1 | | | | | | | | | +|P166 | |DIFFS |IO_L10N_1/VREF_1 |UNUSED | |1 | | | | | | | | | +|P167 | |IOB |IO |UNUSED | |1 | | | | | | | | | +|P168 | |DIFFM |IO_L27P_1 |UNUSED | |1 | | | | | | | | | +|P169 | |DIFFS |IO_L27N_1 |UNUSED | |1 | | | | | | | | | +|P170 | | |GND | | | | | | | | | | | | +|P171 | |DIFFM |IO_L28P_1 |UNUSED | |1 | | | | | | | | | +|P172 | |DIFFS |IO_L28N_1 |UNUSED | |1 | | | | | | | | | +|P173 | | |VCCAUX | | | | | | | |2.5 | | | | +|P174 | | |VCCINT | | | | | | | |1.2 | | | | +|P175 | |IOB |IO |UNUSED | |1 | | | | | | | | | +|P176 | |DIFFM |IO_L31P_1 |UNUSED | |1 | | | | | | | | | +|P177 | | |VCCO_1 | | |1 | | | | |any******| | | | +|P178 | |DIFFS |IO_L31N_1/VREF_1 |UNUSED | |1 | | | | | | | | | +|P179 | | |GND | | | | | | | | | | | | +|P180 | |DIFFM |IO_L32P_1/GCLK4 |UNUSED | |1 | | | | | | | | | +|P181 | |DIFFS |IO_L32N_1/GCLK5 |UNUSED | |1 | | | | | | | | | +|P182 | |IOB |IO |UNUSED | |1 | | | | | | | | | +|P183 |NaN |IOB |IO_L32P_0/GCLK6 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | +|P184 |N<0> |IOB |IO_L32N_0/GCLK7 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE | +|P185 |N<23> |IOB |IO_L31P_0/VREF_0 |INPUT |LVCMOS25* |0 | | | |NONE | |UNLOCATED |NO |NONE | +|P186 | | |GND | | | | | | | | | | | | +|P187 |INF |IOB |IO_L31N_0 |OUTPUT |LVCMOS25* |0 |12 |SLOW |NONE** | | |UNLOCATED |NO |NONE | +|P188 | | |VCCO_0 | | |0 | | | | |2.50 | | | | +|P189 | |IOB |IO |UNUSED | |0 | | | | | | | | | +|P190 | |DIFFM |IO_L30P_0 |UNUSED | |0 | | | | | | | | | +|P191 | |DIFFS |IO_L30N_0 |UNUSED | |0 | | | | | | | | | +|P192 | | |VCCINT | | | | | | | |1.2 | | | | +|P193 | | |VCCAUX | | | | | | | |2.5 | | | | +|P194 | |DIFFM |IO_L27P_0 |UNUSED | |0 | | | | | | | | | +|P195 | | |GND | | | | | | | | | | | | +|P196 | |DIFFS |IO_L27N_0 |UNUSED | |0 | | | | | | | | | +|P197 | |IOB |IO |UNUSED | |0 | | | | | | | | | +|P198 | |DIFFM |IO_L25P_0 |UNUSED | |0 | | | | | | | | | +|P199 | |DIFFS |IO_L25N_0 |UNUSED | |0 | | | | | | | | | +|P200 | | |NC | | | | | | | | | | | | +|P201 | | |VCCO_0 | | |0 | | | | |2.50 | | | | +|P202 | | |GND | | | | | | | | | | | | +|P203 | |DIFFM |IO_L01P_0/VRN_0 |UNUSED | |0 | | | | | | | | | +|P204 | |DIFFS |IO_L01N_0/VRP_0 |UNUSED | |0 | | | | | | | | | +|P205 | |IOB |IO/VREF_0 |UNUSED | |0 | | | | | | | | | +|P206 | | |HSWAP_EN | | | | | | | | | | | | +|P207 | | |PROG_B | | | | | | | | | | | | +|P208 | | |TDI | | | | | | | | | | | | ++--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ + +* Default value. +** This default Pullup/Pulldown value can be overridden in Bitgen. +****** Special VCCO requirements may apply. Please consult the device + family datasheet for specific guideline on VCCO requirements. + + diff --git a/TypeCheck_par.xrpt b/TypeCheck_par.xrpt new file mode 100644 index 0000000..8e0ab45 --- /dev/null +++ b/TypeCheck_par.xrpt @@ -0,0 +1,1400 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
+
+ +
+ + + + +
+ + +
+ + + + +
+ + +
+ + + + + + +
+ + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + +
+
+
+ + + +
+ + + + diff --git a/TypeCheck_summary.xml b/TypeCheck_summary.xml new file mode 100644 index 0000000..313f272 --- /dev/null +++ b/TypeCheck_summary.xml @@ -0,0 +1,10 @@ + + + + + + diff --git a/TypeCheck_usage.xml b/TypeCheck_usage.xml new file mode 100644 index 0000000..0aaa6e7 --- /dev/null +++ b/TypeCheck_usage.xml @@ -0,0 +1,25 @@ + + + + + + + + + + + + + + + + + + + + + diff --git a/TypeCheck_xst.xrpt b/TypeCheck_xst.xrpt new file mode 100644 index 0000000..fdb01f3 --- /dev/null +++ b/TypeCheck_xst.xrpt @@ -0,0 +1,169 @@ + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + + + + +
+ + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
+
+
+
+
+
+
+
+
+
+ + + + + +
+
+ +
+
+ + + + + + + + + + + +
+
+
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+
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+
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+ + + +
+ + + diff --git a/_ngo/netlist.lst b/_ngo/netlist.lst new file mode 100644 index 0000000..1f3721f --- /dev/null +++ b/_ngo/netlist.lst @@ -0,0 +1,2 @@ +/home/Luca/ISE/IEEE754Adder/TypeCheck.ngc 1566052852 +OK diff --git a/_xmsgs/map.xmsgs b/_xmsgs/map.xmsgs new file mode 100644 index 0000000..56dac93 --- /dev/null +++ b/_xmsgs/map.xmsgs @@ -0,0 +1,27 @@ + + + +Logical network N<31> has no load. + + +The above info message is repeated 29 more times for the following (max. 5 shown): +N<30>, +N<29>, +N<28>, +N<27>, +N<26> +To see the details of these info messages, please use the -detail switch. + + +No environment variables are currently set. + + +All of the single ended outputs in this design are using slew rate limited output drivers. The delay on speed critical single ended outputs can be dramatically reduced by designating them as fast outputs. + + + + diff --git a/_xmsgs/ngdbuild.xmsgs b/_xmsgs/ngdbuild.xmsgs new file mode 100644 index 0000000..f84336a --- /dev/null +++ b/_xmsgs/ngdbuild.xmsgs @@ -0,0 +1,9 @@ + + + + + diff --git a/_xmsgs/par.xmsgs b/_xmsgs/par.xmsgs new file mode 100644 index 0000000..97326ca --- /dev/null +++ b/_xmsgs/par.xmsgs @@ -0,0 +1,12 @@ + + + +No user timing constraints were detected or you have set the option to ignore timing constraints ("par -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all internal clocks in this design. Because there are not defined timing requirements, a timing score will not be reported in the PAR report in this mode. The PAR timing summary will list the performance achieved for each clock. Note: For the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". + + + + diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs new file mode 100644 index 0000000..c57b568 --- /dev/null +++ b/_xmsgs/pn_parser.xmsgs @@ -0,0 +1,15 @@ + + + + + + + + + + +Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" into library work + + + + diff --git a/_xmsgs/trce.xmsgs b/_xmsgs/trce.xmsgs new file mode 100644 index 0000000..d69208e --- /dev/null +++ b/_xmsgs/trce.xmsgs @@ -0,0 +1,21 @@ + + + +No timing constraints found, doing default enumeration. + +To improve timing, see the Timing Closure User Guide (UG612). + +To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. + +The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. + +This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation. + +This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error. + + + diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs new file mode 100644 index 0000000..7f18513 --- /dev/null +++ b/_xmsgs/xst.xmsgs @@ -0,0 +1,12 @@ + + + +Input <N<31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. + + + + diff --git a/iseconfig/SpecialCasesCheck.xreport b/iseconfig/SpecialCasesCheck.xreport new file mode 100644 index 0000000..0aa7809 --- /dev/null +++ b/iseconfig/SpecialCasesCheck.xreport @@ -0,0 +1,215 @@ + + +
+ 2019-08-17T15:26:24 + SpecialCasesCheck + Unknown + /home/Luca/ISE/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport + /home/Luca/ISE/IEEE754Adder + 2019-08-17T15:26:24 + false +
+ + + + + + + + + + + + + + + + + + + + + + + + diff --git a/webtalk_pn.xml b/webtalk_pn.xml new file mode 100644 index 0000000..4c615a1 --- /dev/null +++ b/webtalk_pn.xml @@ -0,0 +1,46 @@ + + + + +
+ + + + +
+
+ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +
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