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Luca
2019-08-17 17:41:27 +02:00
commit a1b9650580
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webtalk_pn.xml Normal file
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<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Aug 17 17:02:15 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="144FE553FD2E31FF5236C06C33BACBB5" type="project"/>
<property name="ProjectIteration" value="2" type="project"/>
<property name="ProjectFile" value="/home/Luca/ISE/IEEE754Adder/IEEE754Adder.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2019-08-17T15:21:55" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Minimum Runtime" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Runtime Strategy 1;/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserBrowsedStrategyFiles" value="/opt/Xilinx/14.7/ISE_DS/ISE/data/default.xds" type="process"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2019-08-17T15:21:55" type="design"/>
<property name="PROP_intWbtProjectID" value="144FE553FD2E31FF5236C06C33BACBB5" type="design"/>
<property name="PROP_intWbtProjectIteration" value="2" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_xilxPARplacerEffortLevel" value="Standard" type="process"/>
<property name="PROP_xilxPARrouterEffortLevel" value="Standard" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="Spartan3" type="design"/>
<property name="PROP_MapEffortLevel" value="Standard" type="process"/>
<property name="PROP_xilxPAReffortLevel" value="Standard" type="process"/>
<property name="PROP_DevDevice" value="xc3s50" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3" type="design"/>
<property name="PROP_DevPackage" value="pq208" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-5" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="1" type="source"/>
</section>
</application>
</document>