Initial commit
This commit is contained in:
Luca
147
TypeCheck_map.mrp
Normal file
147
TypeCheck_map.mrp
Normal file
@@ -0,0 +1,147 @@
|
||||
Release 14.7 Map P.20131013 (lin64)
|
||||
Xilinx Mapping Report File for Design 'TypeCheck'
|
||||
|
||||
Design Information
|
||||
------------------
|
||||
Command Line : map -intstyle ise -p xc3s50-pq208-5 -cm area -ir off -pr off -c
|
||||
100 -o TypeCheck_map.ncd TypeCheck.ngd TypeCheck.pcf
|
||||
Target Device : xc3s50
|
||||
Target Package : pq208
|
||||
Target Speed : -5
|
||||
Mapper Version : spartan3 -- $Revision: 1.55 $
|
||||
Mapped Date : Sat Aug 17 16:40:57 2019
|
||||
|
||||
Design Summary
|
||||
--------------
|
||||
Number of errors: 0
|
||||
Number of warnings: 0
|
||||
Logic Utilization:
|
||||
Number of 4 input LUTs: 4 out of 1,536 1%
|
||||
Logic Distribution:
|
||||
Number of occupied Slices: 2 out of 768 1%
|
||||
Number of Slices containing only related logic: 2 out of 2 100%
|
||||
Number of Slices containing unrelated logic: 0 out of 2 0%
|
||||
*See NOTES below for an explanation of the effects of unrelated logic.
|
||||
Total Number of 4 input LUTs: 4 out of 1,536 1%
|
||||
Number of bonded IOBs: 4 out of 124 3%
|
||||
|
||||
Average Fanout of Non-Clock Nets: 1.67
|
||||
|
||||
Peak Memory Usage: 615 MB
|
||||
Total REAL time to MAP completion: 1 secs
|
||||
Total CPU time to MAP completion: 1 secs
|
||||
|
||||
NOTES:
|
||||
|
||||
Related logic is defined as being logic that shares connectivity - e.g. two
|
||||
LUTs are "related" if they share common inputs. When assembling slices,
|
||||
Map gives priority to combine logic that is related. Doing so results in
|
||||
the best timing performance.
|
||||
|
||||
Unrelated logic shares no connectivity. Map will only begin packing
|
||||
unrelated logic into a slice once 99% of the slices are occupied through
|
||||
related logic packing.
|
||||
|
||||
Note that once logic distribution reaches the 99% level through related
|
||||
logic packing, this does not mean the device is completely utilized.
|
||||
Unrelated logic packing will then begin, continuing until all usable LUTs
|
||||
and FFs are occupied. Depending on your timing budget, increased levels of
|
||||
unrelated logic packing may adversely affect the overall timing performance
|
||||
of your design.
|
||||
|
||||
Table of Contents
|
||||
-----------------
|
||||
Section 1 - Errors
|
||||
Section 2 - Warnings
|
||||
Section 3 - Informational
|
||||
Section 4 - Removed Logic Summary
|
||||
Section 5 - Removed Logic
|
||||
Section 6 - IOB Properties
|
||||
Section 7 - RPMs
|
||||
Section 8 - Guide Report
|
||||
Section 9 - Area Group and Partition Summary
|
||||
Section 10 - Timing Report
|
||||
Section 11 - Configuration String Information
|
||||
Section 12 - Control Set Information
|
||||
Section 13 - Utilization by Hierarchy
|
||||
|
||||
Section 1 - Errors
|
||||
------------------
|
||||
|
||||
Section 2 - Warnings
|
||||
--------------------
|
||||
|
||||
Section 3 - Informational
|
||||
-------------------------
|
||||
INFO:LIT:243 - Logical network N<31> has no load.
|
||||
INFO:LIT:395 - The above info message is repeated 29 more times for the
|
||||
following (max. 5 shown):
|
||||
N<30>,
|
||||
N<29>,
|
||||
N<28>,
|
||||
N<27>,
|
||||
N<26>
|
||||
To see the details of these info messages, please use the -detail switch.
|
||||
INFO:MapLib:562 - No environment variables are currently set.
|
||||
INFO:LIT:244 - All of the single ended outputs in this design are using slew
|
||||
rate limited output drivers. The delay on speed critical single ended outputs
|
||||
can be dramatically reduced by designating them as fast outputs.
|
||||
|
||||
Section 4 - Removed Logic Summary
|
||||
---------------------------------
|
||||
|
||||
Section 5 - Removed Logic
|
||||
-------------------------
|
||||
|
||||
Section 6 - IOB Properties
|
||||
--------------------------
|
||||
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
|
||||
| | | | | Term | Strength | Rate | | | Delay |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
| INF | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
||||
| N<0> | IOB | INPUT | LVCMOS25 | | | | | | |
|
||||
| N<23> | IOB | INPUT | LVCMOS25 | | | | | | |
|
||||
| NaN | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
|
||||
+---------------------------------------------------------------------------------------------------------------------------------------------------------+
|
||||
|
||||
Section 7 - RPMs
|
||||
----------------
|
||||
|
||||
Section 8 - Guide Report
|
||||
------------------------
|
||||
Guide not run on this design.
|
||||
|
||||
Section 9 - Area Group and Partition Summary
|
||||
--------------------------------------------
|
||||
|
||||
Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
No Partitions were found in this design.
|
||||
|
||||
-------------------------------
|
||||
|
||||
Area Group Information
|
||||
----------------------
|
||||
|
||||
No area groups were found in this design.
|
||||
|
||||
----------------------
|
||||
|
||||
Section 10 - Timing Report
|
||||
--------------------------
|
||||
This design was not run using timing mode.
|
||||
|
||||
Section 11 - Configuration String Details
|
||||
-----------------------------------------
|
||||
Use the "-detail" map option to print out Configuration Strings
|
||||
|
||||
Section 12 - Control Set Information
|
||||
------------------------------------
|
||||
No control set information for this architecture.
|
||||
|
||||
Section 13 - Utilization by Hierarchy
|
||||
-------------------------------------
|
||||
Use the "-detail" map option to print out the Utilization by Hierarchy section.
|
||||
Reference in New Issue
Block a user