Creazione Pipeline
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209
IEEE754Adder.vhd
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209
IEEE754Adder.vhd
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library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity IEEE754Adder is
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port(
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X, Y : in std_logic_vector(31 downto 0);
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RESET : in std_logic;
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CLK : in std_logic;
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RESULT : out std_logic_vector(31 downto 0)
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);
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end IEEE754Adder;
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architecture Behavioral of IEEE754Adder is
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component PipelineStageOne is
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port(
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X, Y : in std_logic_vector(31 downto 0);
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DIFF_EXP_ABS : out std_logic_vector(8 downto 0);
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A, B : out std_logic_vector(31 downto 0);
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IS_NAN, IS_ZERO : out std_logic
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);
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end component;
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component PipelineStageTwo is
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port(
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A, B : in std_logic_vector(31 downto 0);
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DIFF_EXP_ABS : in std_logic_vector(8 downto 0);
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IS_NAN_IN, IS_ZERO_IN : in std_logic;
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EXP : out std_logic_vector(7 downto 0);
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SUM_RESULT : out std_logic_vector(47 downto 0);
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SUM_OF : out std_logic;
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RES_SIGN : out std_logic;
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IS_NAN_OUT, IS_ZERO_OUT : out std_logic
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);
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end component;
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component PipelineStageThree is
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port(
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RES_SIGN : in std_logic;
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EXP : in std_logic_vector(7 downto 0);
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MANT : in std_logic_vector(47 downto 0);
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MANT_OF : in std_logic;
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IS_NAN, IS_ZERO : in std_logic;
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FINAL_RES : out std_logic_vector(31 downto 0)
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);
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end component;
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component FlipFlopD is
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port(
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CLK : in std_logic;
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RESET : in std_logic;
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D : in std_logic;
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Q : out std_logic
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);
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end component;
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component FlipFlopDVector is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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CLK : in std_logic;
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RESET : in std_logic;
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D : in std_logic_vector(BITCOUNT-1 downto 0);
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Q : out std_logic_vector(BITCOUNT-1 downto 0)
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);
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end component;
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signal IN_S1_X : std_logic_vector(31 downto 0);
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signal IN_S1_Y : std_logic_vector(31 downto 0);
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signal OUT_S1_DIFF_EXP_ABS : std_logic_vector(8 downto 0);
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signal OUT_S1_A : std_logic_vector(31 downto 0);
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signal OUT_S1_B : std_logic_vector(31 downto 0);
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signal OUT_S1_IS_NAN : std_logic;
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signal OUT_S1_IS_ZERO : std_logic;
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signal IN_S2_DIFF_EXP_ABS : std_logic_vector(8 downto 0);
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signal IN_S2_A : std_logic_vector(31 downto 0);
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signal IN_S2_B : std_logic_vector(31 downto 0);
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signal IN_S2_IS_NAN : std_logic;
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signal IN_S2_IS_ZERO : std_logic;
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signal OUT_S2_EXP : std_logic_vector(7 downto 0);
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signal OUT_S2_SUM_RESULT : std_logic_vector(47 downto 0);
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signal OUT_S2_SUM_OF : std_logic;
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signal OUT_S2_RES_SIGN : std_logic;
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signal OUT_S2_IS_NAN : std_logic;
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signal OUT_S2_IS_ZERO : std_logic;
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signal IN_S3_EXP : std_logic_vector(7 downto 0);
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signal IN_S3_SUM_RESULT : std_logic_vector(47 downto 0);
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signal IN_S3_SUM_OF : std_logic;
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signal IN_S3_RES_SIGN : std_logic;
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signal IN_S3_IS_NAN : std_logic;
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signal IN_S3_IS_ZERO : std_logic;
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signal OUT_S3_FINAL_RES : std_logic_vector(31 downto 0);
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begin
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DFF_INP1_X : FlipFlopDVector
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generic map (BITCOUNT => 32)
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port map ( CLK => CLK, RESET => RESET, D => X, Q => IN_S1_X);
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DFF_INP1_Y : FlipFlopDVector
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generic map (BITCOUNT => 32)
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port map ( CLK => CLK, RESET => RESET, D => Y, Q => IN_S1_Y);
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P1 : PipelineStageOne
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port map (
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X => IN_S1_X,
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Y => IN_S1_Y,
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DIFF_EXP_ABS => OUT_S1_DIFF_EXP_ABS,
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A => OUT_S1_A,
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B => OUT_S1_B,
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IS_NAN => OUT_S1_IS_NAN,
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IS_ZERO => OUT_S1_IS_ZERO
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);
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DFF_P1P2_DIFF_EXP_ABS : FlipFlopDVector
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generic map (BITCOUNT => 9)
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port map ( CLK => CLK, RESET => RESET, D => OUT_S1_DIFF_EXP_ABS, Q => IN_S2_DIFF_EXP_ABS);
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DFF_P1P2_A : FlipFlopDVector
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generic map (BITCOUNT => 32)
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port map ( CLK => CLK, RESET => RESET, D => OUT_S1_A, Q => IN_S2_A);
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DFF_P1P2_B : FlipFlopDVector
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generic map (BITCOUNT => 32)
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port map ( CLK => CLK, RESET => RESET, D => OUT_S1_B, Q => IN_S2_B);
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DFF_P1P2_IS_NAN : FlipFlopD
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port map ( CLK => CLK, RESET => RESET, D => OUT_S1_IS_NAN, Q => IN_S2_IS_NAN);
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DFF_P1P2_IS_ZERO : FlipFlopD
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port map ( CLK => CLK, RESET => RESET, D => OUT_S1_IS_ZERO, Q => IN_S2_IS_ZERO);
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P2 : PipelineStageTwo
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port map (
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A => IN_S2_A,
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B => IN_S2_B,
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DIFF_EXP_ABS => IN_S2_DIFF_EXP_ABS,
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IS_NAN_IN => IN_S2_IS_NAN,
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IS_ZERO_IN => IN_S2_IS_ZERO,
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EXP => OUT_S2_EXP,
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SUM_RESULT => OUT_S2_SUM_RESULT,
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SUM_OF => OUT_S2_SUM_OF,
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RES_SIGN => OUT_S2_RES_SIGN,
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IS_NAN_OUT => OUT_S2_IS_NAN,
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IS_ZERO_OUT => OUT_S2_IS_ZERO
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);
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DFF_P2P3_EXP : FlipFlopDVector
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generic map (BITCOUNT => 8)
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port map ( CLK => CLK, RESET => RESET, D => OUT_S2_EXP, Q => IN_S3_EXP);
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DFF_P2P3_SUM_RESULT : FlipFlopDVector
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generic map (BITCOUNT => 48)
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port map ( CLK => CLK, RESET => RESET, D => OUT_S2_SUM_RESULT, Q => IN_S3_SUM_RESULT);
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DFF_P2P3_SUM_OF : FlipFlopD
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port map ( CLK => CLK, RESET => RESET, D => OUT_S2_SUM_OF, Q => IN_S3_SUM_OF);
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DFF_P2P3_RES_SIGN : FlipFlopD
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port map ( CLK => CLK, RESET => RESET, D => OUT_S2_RES_SIGN, Q => IN_S3_RES_SIGN);
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DFF_P2P3_IS_NAN : FlipFlopD
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port map ( CLK => CLK, RESET => RESET, D => OUT_S2_IS_NAN, Q => IN_S3_IS_NAN);
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DFF_P2P3_IS_ZERO : FlipFlopD
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port map ( CLK => CLK, RESET => RESET, D => OUT_S2_IS_ZERO, Q => IN_S3_IS_ZERO);
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P3 : PipelineStageThree
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port map (
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RES_SIGN => IN_S3_RES_SIGN,
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EXP => IN_S3_EXP,
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MANT => IN_S3_SUM_RESULT,
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MANT_OF => IN_S3_SUM_OF,
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IS_NAN => IN_S3_IS_NAN,
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IS_ZERO => IN_S3_IS_ZERO,
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FINAL_RES => OUT_S3_FINAL_RES
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);
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DFF_P3OUT_RESULT : FlipFlopDVector
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generic map (BITCOUNT => 32)
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port map ( CLK => CLK, RESET => RESET, D => OUT_S3_FINAL_RES, Q => RESULT);
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end Behavioral;
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