diff --git a/FlipFlopD.vhd b/FlipFlopD.vhd
new file mode 100644
index 0000000..da37450
--- /dev/null
+++ b/FlipFlopD.vhd
@@ -0,0 +1,31 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FlipFlopD is
+
+	port(
+		CLK : in std_logic;
+		RESET : in std_logic;
+		D : in std_logic;
+		Q : out std_logic
+	);
+
+end FlipFlopD;
+
+architecture FlipFlopDArch of FlipFlopD is
+
+begin
+
+	ff: process( CLK )
+	begin
+		if( CLK'event and CLK = '0' ) then
+			if( RESET = '1' ) then
+				Q <= '0';
+			else
+				Q <= D;
+			end if;
+		end if;
+	end process;
+
+end FlipFlopDArch;
+
diff --git a/FlipFlopDVector.vhd b/FlipFlopDVector.vhd
new file mode 100644
index 0000000..8a59021
--- /dev/null
+++ b/FlipFlopDVector.vhd
@@ -0,0 +1,35 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity FlipFlopDVector is
+
+	generic(
+		BITCOUNT : integer := 8
+	);
+
+	port(
+		CLK : in std_logic;
+		RESET : in std_logic;
+		D : in std_logic_vector(BITCOUNT-1 downto 0);
+		Q : out std_logic_vector(BITCOUNT-1 downto 0)
+	);
+
+end FlipFlopDVector;
+
+architecture FlipFlopDVectorArch of FlipFlopDVector is
+
+begin
+	
+	ff: process( CLK )
+	begin
+		if( CLK'event and CLK = '0' ) then
+			if( RESET = '1' ) then
+				Q <= (BITCOUNT-1 downto 0 => '0');
+			else
+				Q <= D;
+			end if;
+		end if;
+	end process;
+
+end FlipFlopDVectorArch;
+
diff --git a/IEEE754Adder.vhd b/IEEE754Adder.vhd
new file mode 100644
index 0000000..b750cd7
--- /dev/null
+++ b/IEEE754Adder.vhd
@@ -0,0 +1,209 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity IEEE754Adder is
+
+	port(
+		X, Y : in std_logic_vector(31 downto 0);
+		RESET : in std_logic;
+		CLK : in std_logic;
+		RESULT : out std_logic_vector(31 downto 0)
+	);
+
+end IEEE754Adder;
+
+architecture Behavioral of IEEE754Adder is
+
+	component PipelineStageOne is
+
+		port(
+			X, Y : in std_logic_vector(31 downto 0);
+			DIFF_EXP_ABS : out std_logic_vector(8 downto 0);
+			A, B : out std_logic_vector(31 downto 0);
+			IS_NAN, IS_ZERO : out std_logic
+		);
+		
+	end component;
+
+	component PipelineStageTwo is
+
+		port(
+			A, B : in std_logic_vector(31 downto 0);
+			DIFF_EXP_ABS : in std_logic_vector(8 downto 0);
+			IS_NAN_IN, IS_ZERO_IN : in std_logic;
+			EXP : out std_logic_vector(7 downto 0);
+			SUM_RESULT : out std_logic_vector(47 downto 0);
+			SUM_OF : out std_logic;
+			RES_SIGN : out std_logic;
+			IS_NAN_OUT, IS_ZERO_OUT : out std_logic
+		);
+		
+	end component;
+
+	component PipelineStageThree is
+
+		port(
+			RES_SIGN : in std_logic;
+			EXP : in std_logic_vector(7 downto 0);
+			MANT : in std_logic_vector(47 downto 0);
+			MANT_OF : in std_logic;
+			IS_NAN, IS_ZERO : in std_logic;
+			FINAL_RES : out std_logic_vector(31 downto 0)
+		);
+		
+	end component;
+		
+	component FlipFlopD is
+
+		port(
+			CLK : in std_logic;
+			RESET : in std_logic;
+			D : in std_logic;
+			Q : out std_logic
+		);
+
+	end component;
+
+	component FlipFlopDVector is
+
+		generic(
+			BITCOUNT : integer := 8
+		);
+
+		port(
+			CLK : in std_logic;
+			RESET : in std_logic;
+			D : in std_logic_vector(BITCOUNT-1 downto 0);
+			Q : out std_logic_vector(BITCOUNT-1 downto 0)
+		);
+
+	end component;
+
+	signal IN_S1_X : std_logic_vector(31 downto 0);
+	signal IN_S1_Y : std_logic_vector(31 downto 0);
+	
+	signal OUT_S1_DIFF_EXP_ABS : std_logic_vector(8 downto 0);
+	signal OUT_S1_A : std_logic_vector(31 downto 0);
+	signal OUT_S1_B : std_logic_vector(31 downto 0);
+	signal OUT_S1_IS_NAN : std_logic;
+	signal OUT_S1_IS_ZERO : std_logic;
+
+	signal IN_S2_DIFF_EXP_ABS : std_logic_vector(8 downto 0);
+	signal IN_S2_A : std_logic_vector(31 downto 0);
+	signal IN_S2_B : std_logic_vector(31 downto 0);
+	signal IN_S2_IS_NAN : std_logic;
+	signal IN_S2_IS_ZERO : std_logic;
+	
+	signal OUT_S2_EXP : std_logic_vector(7 downto 0);
+	signal OUT_S2_SUM_RESULT : std_logic_vector(47 downto 0);
+	signal OUT_S2_SUM_OF : std_logic;
+	signal OUT_S2_RES_SIGN : std_logic;
+	signal OUT_S2_IS_NAN : std_logic;
+	signal OUT_S2_IS_ZERO : std_logic;
+	
+	signal IN_S3_EXP : std_logic_vector(7 downto 0);
+	signal IN_S3_SUM_RESULT : std_logic_vector(47 downto 0);
+	signal IN_S3_SUM_OF : std_logic;
+	signal IN_S3_RES_SIGN : std_logic;
+	signal IN_S3_IS_NAN : std_logic;
+	signal IN_S3_IS_ZERO : std_logic;
+	
+	signal OUT_S3_FINAL_RES : std_logic_vector(31 downto 0);
+
+begin
+
+	DFF_INP1_X : FlipFlopDVector
+		generic map (BITCOUNT => 32)
+		port map ( CLK => CLK, RESET => RESET, D => X, Q => IN_S1_X);
+
+	DFF_INP1_Y : FlipFlopDVector
+		generic map (BITCOUNT => 32)
+		port map ( CLK => CLK, RESET => RESET, D => Y, Q => IN_S1_Y);
+
+	P1 : PipelineStageOne
+		port map (
+			X => IN_S1_X,
+			Y => IN_S1_Y,
+			DIFF_EXP_ABS => OUT_S1_DIFF_EXP_ABS,
+			A => OUT_S1_A,
+			B => OUT_S1_B,
+			IS_NAN => OUT_S1_IS_NAN,
+			IS_ZERO => OUT_S1_IS_ZERO
+		);
+		
+	DFF_P1P2_DIFF_EXP_ABS : FlipFlopDVector
+		generic map (BITCOUNT => 9)
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S1_DIFF_EXP_ABS, Q => IN_S2_DIFF_EXP_ABS);
+
+	DFF_P1P2_A : FlipFlopDVector
+		generic map (BITCOUNT => 32)
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S1_A, Q => IN_S2_A);
+
+	DFF_P1P2_B : FlipFlopDVector
+		generic map (BITCOUNT => 32)
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S1_B, Q => IN_S2_B);
+
+	DFF_P1P2_IS_NAN : FlipFlopD
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S1_IS_NAN, Q => IN_S2_IS_NAN);
+
+	DFF_P1P2_IS_ZERO : FlipFlopD
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S1_IS_ZERO, Q => IN_S2_IS_ZERO);
+
+
+
+
+	P2 : PipelineStageTwo
+		port map (
+			A => IN_S2_A,
+			B => IN_S2_B,
+			DIFF_EXP_ABS => IN_S2_DIFF_EXP_ABS,
+			IS_NAN_IN => IN_S2_IS_NAN,
+			IS_ZERO_IN => IN_S2_IS_ZERO,
+			EXP => OUT_S2_EXP,
+			SUM_RESULT => OUT_S2_SUM_RESULT,
+			SUM_OF => OUT_S2_SUM_OF,
+			RES_SIGN => OUT_S2_RES_SIGN,
+			IS_NAN_OUT => OUT_S2_IS_NAN,
+			IS_ZERO_OUT => OUT_S2_IS_ZERO
+		);
+
+	DFF_P2P3_EXP : FlipFlopDVector
+		generic map (BITCOUNT => 8)
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S2_EXP, Q => IN_S3_EXP);
+
+	DFF_P2P3_SUM_RESULT : FlipFlopDVector
+		generic map (BITCOUNT => 48)
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S2_SUM_RESULT, Q => IN_S3_SUM_RESULT);
+
+	DFF_P2P3_SUM_OF : FlipFlopD
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S2_SUM_OF, Q => IN_S3_SUM_OF);
+
+	DFF_P2P3_RES_SIGN : FlipFlopD
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S2_RES_SIGN, Q => IN_S3_RES_SIGN);
+
+	DFF_P2P3_IS_NAN : FlipFlopD
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S2_IS_NAN, Q => IN_S3_IS_NAN);
+
+	DFF_P2P3_IS_ZERO : FlipFlopD
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S2_IS_ZERO, Q => IN_S3_IS_ZERO);
+
+
+
+
+	P3 : PipelineStageThree
+		port map (
+			RES_SIGN => IN_S3_RES_SIGN,
+			EXP => IN_S3_EXP,
+			MANT => IN_S3_SUM_RESULT,
+			MANT_OF => IN_S3_SUM_OF,
+			IS_NAN => IN_S3_IS_NAN,
+			IS_ZERO => IN_S3_IS_ZERO,
+			FINAL_RES => OUT_S3_FINAL_RES
+		);
+		
+	DFF_P3OUT_RESULT : FlipFlopDVector
+		generic map (BITCOUNT => 32)
+		port map ( CLK => CLK, RESET => RESET, D => OUT_S3_FINAL_RES, Q => RESULT);
+
+end Behavioral;
+
diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise
index 208cf08..ee9e06d 100644
--- a/IEEE754Adder.xise
+++ b/IEEE754Adder.xise
@@ -17,23 +17,23 @@
   <files>
     <file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="15"/>
     </file>
     <file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="9"/>
     </file>
     <file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
     </file>
     <file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -43,7 +43,7 @@
     </file>
     <file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -53,11 +53,11 @@
     </file>
     <file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="16"/>
     </file>
     <file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="13"/>
     </file>
     <file xil_pn:name="SwapTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -67,11 +67,11 @@
     </file>
     <file xil_pn:name="TwoComplement.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="12"/>
     </file>
     <file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="18"/>
     </file>
     <file xil_pn:name="TwoComplementTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -81,11 +81,11 @@
     </file>
     <file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="6"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="AddSubTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -95,19 +95,19 @@
     </file>
     <file xil_pn:name="CarryLookAhead.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="20"/>
     </file>
     <file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
     </file>
     <file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="7"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="SumDataAdapterTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -141,7 +141,7 @@
     </file>
     <file xil_pn:name="ZeroCounter.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="ZeroCounterTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
@@ -151,7 +151,7 @@
     </file>
     <file xil_pn:name="ShiftLeft.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="UTILS.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -159,7 +159,7 @@
     </file>
     <file xil_pn:name="OutputSelector.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="OutputSelectorTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
@@ -167,6 +167,30 @@
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="305"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="305"/>
     </file>
+    <file xil_pn:name="PipelineStageOne.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="318"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
+    </file>
+    <file xil_pn:name="PipelineStageTwo.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="329"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
+    </file>
+    <file xil_pn:name="PipelineStageThree.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="350"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
+    </file>
+    <file xil_pn:name="IEEE754Adder.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="362"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
+    </file>
+    <file xil_pn:name="FlipFlopD.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="363"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
+    </file>
+    <file xil_pn:name="FlipFlopDVector.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="375"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
+    </file>
   </files>
 
   <properties>
@@ -287,9 +311,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|Normalizer|NormalizerArch" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="Normalizer.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/Normalizer" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|IEEE754Adder|Behavioral" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="IEEE754Adder.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/IEEE754Adder" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -358,7 +382,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="Normalizer" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="IEEE754Adder" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -373,10 +397,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="Normalizer_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="Normalizer_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="Normalizer_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="Normalizer_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="IEEE754Adder_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="IEEE754Adder_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="IEEE754Adder_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="IEEE754Adder_translate.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
diff --git a/PipelineStageOne.vhd b/PipelineStageOne.vhd
new file mode 100644
index 0000000..dc834a9
--- /dev/null
+++ b/PipelineStageOne.vhd
@@ -0,0 +1,83 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity PipelineStageOne is
+
+	port(
+		X, Y : in std_logic_vector(31 downto 0);
+		DIFF_EXP_ABS : out std_logic_vector(8 downto 0);
+		A, B : out std_logic_vector(31 downto 0);
+		IS_NAN, IS_ZERO : out std_logic
+	);
+	
+end PipelineStageOne;
+
+architecture StageOneArch of PipelineStageOne is
+
+	component SpecialCasesCheck is
+
+		port(
+			X, Y : in std_logic_vector(31 downto 0);
+			IS_NAN, IS_ZERO : out std_logic
+		);
+		
+	end component;
+	
+	component PrepareForShift is
+
+		port(
+			X, Y : in std_logic_vector(30 downto 0);
+			DIFF_EXP : out std_logic_vector(8 downto 0);
+			NEED_SWAP : out std_logic
+		);
+		
+	end component;
+	
+	component Swap is
+
+		generic(
+			BITCOUNT : integer := 8
+		);
+		
+		port(
+			X_IN, Y_IN : in std_logic_vector((BITCOUNT-1) downto 0);
+			SW : in std_logic;
+			X_OUT, Y_OUT : out std_logic_vector((BITCOUNT-1) downto 0)
+		);
+		
+	end component;
+	
+	component TwoComplement is
+
+		generic(
+			BITCOUNT : integer := 8
+		);
+		
+		port(
+			DIFF_EXP_C2 : in std_logic_vector((BITCOUNT-1) downto 0);
+			DIFF_EXP : out std_logic_vector((BITCOUNT-1) downto 0)
+		);
+		
+	end component;
+	
+	signal DIFF_EXP_C2 : std_logic_vector(8 downto 0);
+	signal SW : std_logic;
+
+begin
+
+	SPC : SpecialCasesCheck
+		port map (X => X, Y => Y, IS_NAN => IS_NAN, IS_ZERO => IS_ZERO);
+		
+	PFS : PrepareForShift
+		port map (X => X(30 downto 0), Y => Y(30 downto 0), DIFF_EXP => DIFF_EXP_C2, NEED_SWAP => SW);
+
+	S : Swap
+		generic map (BITCOUNT => 32)
+		port map (X_IN => X, Y_IN => Y, SW => SW, X_OUT => A, Y_OUT => B);
+		
+	C2 : TwoComplement
+		generic map (BITCOUNT => 9)
+		port map (DIFF_EXP_C2 => DIFF_EXP_C2, DIFF_EXP => DIFF_EXP_ABS);
+	
+end StageOneArch;
+
diff --git a/PipelineStageThree.vhd b/PipelineStageThree.vhd
new file mode 100644
index 0000000..0b51566
--- /dev/null
+++ b/PipelineStageThree.vhd
@@ -0,0 +1,64 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity PipelineStageThree is
+
+	port(
+		RES_SIGN : in std_logic;
+		EXP : in std_logic_vector(7 downto 0);
+		MANT : in std_logic_vector(47 downto 0);
+		MANT_OF : in std_logic;
+		IS_NAN, IS_ZERO : in std_logic;
+		FINAL_RES : out std_logic_vector(31 downto 0)
+	);
+	
+end PipelineStageThree;
+
+architecture StageThreeArch of PipelineStageThree is
+
+	component Normalizer is
+
+		port(
+			SIGN : in std_logic;
+			EXP : in std_logic_vector(7 downto 0);
+			MANT : in std_logic_vector(47 downto 0);
+			SUM_OVERFLOW : in std_logic;
+			IEEE_754_SUM : out std_logic_vector(31 downto 0)
+		);
+
+	end component;
+		
+	component OutputSelector is
+		
+		port(
+			IS_NAN : in std_logic;
+			IS_ZERO : in std_logic;
+			IEEE_754_SUM : in std_logic_vector(31 downto 0);
+			RESULT : out std_logic_vector(31 downto 0)		
+		);
+		
+	end component;
+	
+	signal NORMALIZED : std_logic_vector(31 downto 0);
+
+begin
+
+	N : Normalizer
+		port map (
+			SIGN => RES_SIGN,
+			EXP => EXP,
+			MANT => MANT,
+			SUM_OVERFLOW => MANT_OF,
+			IEEE_754_SUM => NORMALIZED
+		);
+		
+	OS : OutputSelector
+		port map (
+			IS_NAN => IS_NAN,
+			IS_ZERO => IS_ZERO,
+			IEEE_754_SUM => NORMALIZED,
+			RESULT => FINAL_RES
+		);
+
+end StageThreeArch;
+
diff --git a/PipelineStageTwo.vhd b/PipelineStageTwo.vhd
new file mode 100644
index 0000000..fb430ca
--- /dev/null
+++ b/PipelineStageTwo.vhd
@@ -0,0 +1,80 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity PipelineStageTwo is
+
+	port(
+		A, B : in std_logic_vector(31 downto 0);
+		DIFF_EXP_ABS : in std_logic_vector(8 downto 0);
+		IS_NAN_IN, IS_ZERO_IN : in std_logic;
+		EXP : out std_logic_vector(7 downto 0);
+		SUM_RESULT : out std_logic_vector(47 downto 0);
+		SUM_OF : out std_logic;
+		RES_SIGN : out std_logic;
+		IS_NAN_OUT, IS_ZERO_OUT : out std_logic
+	);
+	
+end PipelineStageTwo;
+
+architecture StageTwoArch of PipelineStageTwo is
+
+	component SumDataAdapter is
+
+		port(
+			X_IN, Y_IN : in std_logic_vector(30 downto 0);
+			DIFF_EXP : in std_logic_vector(8 downto 0);
+			X_OUT, Y_OUT : out std_logic_vector(47 downto 0)
+		);
+		
+	end component;
+		
+	component CarryLookAhead is
+
+		port(
+			X, Y : in std_logic_vector(47 downto 0);
+			OP : in std_logic;
+			RESULT : out std_logic_vector(47 downto 0);
+			OVERFLOW : out std_logic
+		);
+		
+	end component;
+		
+	component OperationCheck is
+
+		port(
+			X_SIGN, Y_SIGN : in std_logic;
+			OP, RES_SIGN : out std_logic
+		);
+		
+	end component;
+	
+	signal MANT_EXT_A : std_logic_vector(47 downto 0);
+	signal MANT_EXT_B : std_logic_vector(47 downto 0);
+	signal OP : std_logic;
+
+begin
+
+	SH : SumDataAdapter
+		port map (
+			X_IN => A(30 downto 0), Y_IN => B(30 downto 0), 
+			DIFF_EXP => DIFF_EXP_ABS, X_OUT => MANT_EXT_A, Y_OUT => MANT_EXT_B
+		);
+		
+	OC : OperationCheck
+		port map (X_SIGN => A(31), Y_SIGN => B(31), OP => OP, RES_SIGN => RES_SIGN);
+		
+	CLA : CarryLookAhead
+		port map (
+			X => MANT_EXT_A, 
+			Y => MANT_EXT_B, 
+			OP => OP, 
+			RESULT => SUM_RESULT, 
+			OVERFLOW => SUM_OF
+		);
+
+	IS_NAN_OUT <= IS_NAN_IN;
+	IS_ZERO_OUT <= IS_ZERO_IN;
+	EXP <= A(30 downto 23);
+
+end StageTwoArch;
+