Fix normalizzatore + test
This commit is contained in:
@@ -30,7 +30,7 @@ ARCHITECTURE behavior OF IEEE754AdderTest IS
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signal RESULT : std_logic_vector(31 downto 0);
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-- Clock period definitions
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constant CLK_period : time := 100 ns; -- MESSA A CASO. VALUTARE IL PERIODO GIUSTO
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constant CLK_period : time := 50 ns; -- MESSA A CASO. VALUTARE IL PERIODO GIUSTO
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BEGIN
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@@ -57,7 +57,7 @@ BEGIN
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stim_proc: process
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begin
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RESET <= '1';
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wait for 400 ns;
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wait for 2*CLK_period;
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RESET <= '0';
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-- TODO: FINIRE TEST
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@@ -68,41 +68,41 @@ BEGIN
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X <= "00001000000000000000111000000000";
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Y <= "00000010000001111000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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X <= "01000000010110011001100110011010";
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Y <= "01100110010001110000110110000001";
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wait for CLK_period;
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X <= "01111111100000000000000000000000";
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Y <= "11111111100000000000000000000000";
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wait for CLK_period;
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X <= "01000000100000000000000000000000";
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Y <= "01111111100000000000000000000000";
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wait for CLK_period;
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X <= "00000000100100000000000000000000";
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Y <= "10000000011111111111111111111111";
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wait for CLK_period;
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X <= "11001100000111100111101111110100";
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Y <= "11001111111110111111011100110110";
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wait for CLK_period;
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X <= "01111111011111111111111111111111";
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Y <= "01111110011111111111111111111111";
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wait for CLK_period;
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X <= "11111111111111111111111111111111";
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Y <= "00111111100000000000000000000000";
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wait for CLK_period;
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X <= "00110110100111000010111100011010";
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Y <= "11111111111111111111000001111111";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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Y <= "10000000000000000000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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X <= "01001100111010110111100110100011";
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Y <= "11001100111010110111100110100011";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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X <= "01000010001010000000000000000000";
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Y <= "01000001101110000000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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wait for CLK_period;
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X <= "00000000000000000000000000000000";
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Y <= "00000000000000000000000000000000";
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X <= "01101000111011011000111011010101";
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Y <= "00011001001011011001100001111101";
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wait;
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end process;
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BIN
IEEE754AdderTest_isim_beh.wdb
Normal file
BIN
IEEE754AdderTest_isim_beh.wdb
Normal file
Binary file not shown.
31
IEEE754Adder_fpga_editor.log
Normal file
31
IEEE754Adder_fpga_editor.log
Normal file
@@ -0,0 +1,31 @@
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#:C0
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#Xilinx FPGA Editor Command Log File
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#Editor Version:
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#:V SPARC M2.1 P.20131013
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#Current Working Directory:
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#:D /home/Luca/ISE/IEEE754Adder
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#Host Name:
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#:H Xilinx
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#Date/Time:
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#:T Mon Sep 9 19:07:26 2019
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#------------------------------
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#Reading IEEE754Adder.ncd...
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#Loading device for application Rf_Device from file '6slx75.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
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# "IEEE754Adder" is an NCD, version 3.2, device xc6slx75, package fgg676, speed -3
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#Design creation date: 2019.09.09.17.05.24
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#Building chip graphics...
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#Loading speed info...
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#1
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setattr main edit-mode no-logic-changes
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#2
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unselect -all
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#3
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select site 'SLICE_X14Y76'
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#site "SLICE_X14Y76", type = SLICEM (RPM grid X41Y312)
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#4
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unselect -all
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#5
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select site 'SLICE_X14Y76'
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#site "SLICE_X14Y76", type = SLICEM (RPM grid X41Y312)
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#6
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post block
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@@ -73,7 +73,6 @@ architecture NormalizerArch of Normalizer is
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signal LEFT_SHIFT_AMOUNT: std_logic_vector(8 downto 0);
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signal LEFT_SHIFTED_MANT: std_logic_vector(22 downto 0);
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signal LEFT_SHIFTED_MANT_TMP: std_logic_vector(47 downto 0);
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signal RIGHT_SHIFTED_MANT: std_logic_vector(22 downto 0);
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signal FINAL_MANT: std_logic_vector(22 downto 0);
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begin
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@@ -117,13 +116,11 @@ begin
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end if;
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end process;
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RIGHT_SHIFTED_MANT <= '1' & MANT(47 downto 26);
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SL: ShiftLeft48
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port map ( N => MANT, PLACES => LEFT_SHIFT_AMOUNT, RESULT => LEFT_SHIFTED_MANT_TMP );
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LEFT_SHIFTED_MANT <= LEFT_SHIFTED_MANT_TMP(47 downto 25);
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LEFT_SHIFTED_MANT <= LEFT_SHIFTED_MANT_TMP(46 downto 24);
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final_process: process (SUM_OVERFLOW, IS_FINAL_EXP_MINIMUM, EXP_ADDSUB_RES, EXP_ADDSUB_OF, RIGHT_SHIFTED_MANT, LEFT_SHIFTED_MANT, EXP)
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final_process: process (SUM_OVERFLOW, IS_FINAL_EXP_MINIMUM, EXP_ADDSUB_RES, EXP_ADDSUB_OF, LEFT_SHIFTED_MANT, EXP, MANT)
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variable IS_INF : std_logic;
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variable IS_INF_ORIGINAL_EXP : std_logic;
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variable IS_INF_FINAL_EXP : std_logic;
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@@ -144,7 +141,7 @@ begin
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else
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if (SUM_OVERFLOW = '1') then
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FINAL_EXP <= EXP_ADDSUB_RES;
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FINAL_MANT <= RIGHT_SHIFTED_MANT;
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FINAL_MANT <= MANT(47 downto 25);
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else
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FINAL_EXP <= EXP_ADDSUB_RES;
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FINAL_MANT <= LEFT_SHIFTED_MANT;
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12
fuse.log
12
fuse.log
@@ -32,8 +32,8 @@ Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/IEEE754Adder.vhd" into library wo
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/IEEE754AdderTest.vhd" into library work
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Starting static elaboration
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Completed static elaboration
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Fuse Memory Usage: 97552 KB
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Fuse CPU Usage: 990 ms
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Fuse Memory Usage: 97548 KB
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Fuse CPU Usage: 950 ms
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Compiling package standard
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Compiling package std_logic_1164
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Compiling architecture flipflopdvectorarch of entity FlipFlopDVector [\FlipFlopDVector(32)\]
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@@ -72,9 +72,9 @@ Compiling architecture stagethreearch of entity PipelineStageThree [pipelinestag
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Compiling architecture behavioral of entity IEEE754Adder [ieee754adder_default]
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Compiling architecture behavior of entity ieee754addertest
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Time Resolution for simulation is 1ps.
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Waiting for 2 sub-compilation(s) to finish...
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Waiting for 3 sub-compilation(s) to finish...
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Compiled 68 VHDL Units
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Built simulation executable /home/Luca/ISE/IEEE754Adder/IEEE754AdderTest_isim_beh.exe
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Fuse Memory Usage: 671904 KB
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Fuse CPU Usage: 1160 ms
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GCC CPU Usage: 1140 ms
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Fuse Memory Usage: 671896 KB
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Fuse CPU Usage: 1120 ms
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GCC CPU Usage: 1130 ms
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