diff --git a/IEEE754AdderTest.vhd b/IEEE754AdderTest.vhd
index cc0d8a2..e3c8e7b 100644
--- a/IEEE754AdderTest.vhd
+++ b/IEEE754AdderTest.vhd
@@ -30,7 +30,7 @@ ARCHITECTURE behavior OF IEEE754AdderTest IS
    signal RESULT : std_logic_vector(31 downto 0);
 
    -- Clock period definitions
-   constant CLK_period : time := 100 ns; -- MESSA A CASO. VALUTARE IL PERIODO GIUSTO
+   constant CLK_period : time := 50 ns; -- MESSA A CASO. VALUTARE IL PERIODO GIUSTO
  
 BEGIN
  
@@ -57,7 +57,7 @@ BEGIN
    stim_proc: process
    begin		
       RESET <= '1';
-      wait for 400 ns;
+      wait for 2*CLK_period;
 		RESET <= '0';
 
 		-- TODO: FINIRE TEST
@@ -68,41 +68,41 @@ BEGIN
 		X <= "00001000000000000000111000000000";
 		Y <= "00000010000001111000000000000000";
       wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
+		X <= "01000000010110011001100110011010";
+		Y <= "01100110010001110000110110000001";
+      wait for CLK_period; 
+		X <= "01111111100000000000000000000000";
+		Y <= "11111111100000000000000000000000";
+      wait for CLK_period; 
+		X <= "01000000100000000000000000000000";
+		Y <= "01111111100000000000000000000000";
+      wait for CLK_period; 
+		X <= "00000000100100000000000000000000";
+		Y <= "10000000011111111111111111111111";
+      wait for CLK_period; 
+		X <= "11001100000111100111101111110100";
+		Y <= "11001111111110111111011100110110";
+      wait for CLK_period; 
+		X <= "01111111011111111111111111111111";
+		Y <= "01111110011111111111111111111111";
+      wait for CLK_period; 
+		X <= "11111111111111111111111111111111";
+		Y <= "00111111100000000000000000000000";
+      wait for CLK_period; 
+		X <= "00110110100111000010111100011010";
+		Y <= "11111111111111111111000001111111";
       wait for CLK_period; 
 		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
+		Y <= "10000000000000000000000000000000";
       wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
+		X <= "01001100111010110111100110100011";
+		Y <= "11001100111010110111100110100011";
       wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
+		X <= "01000010001010000000000000000000";
+		Y <= "01000001101110000000000000000000";
       wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
-      wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
-      wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
-      wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
-      wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
-      wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
-      wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
-      wait for CLK_period; 
-		X <= "00000000000000000000000000000000";
-		Y <= "00000000000000000000000000000000";
+		X <= "01101000111011011000111011010101";
+		Y <= "00011001001011011001100001111101";
       wait;
    end process;
 
diff --git a/IEEE754AdderTest_isim_beh.wdb b/IEEE754AdderTest_isim_beh.wdb
new file mode 100644
index 0000000..36d0b2a
Binary files /dev/null and b/IEEE754AdderTest_isim_beh.wdb differ
diff --git a/IEEE754Adder_fpga_editor.log b/IEEE754Adder_fpga_editor.log
new file mode 100644
index 0000000..ba274fa
--- /dev/null
+++ b/IEEE754Adder_fpga_editor.log
@@ -0,0 +1,31 @@
+#:C0     
+#Xilinx FPGA Editor Command Log File
+#Editor Version:
+#:V   SPARC M2.1 P.20131013
+#Current Working Directory:
+#:D   /home/Luca/ISE/IEEE754Adder
+#Host Name:
+#:H   Xilinx
+#Date/Time:
+#:T   Mon Sep  9 19:07:26 2019
+#------------------------------
+	#Reading IEEE754Adder.ncd...
+	#Loading device for application Rf_Device from file '6slx75.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
+	#   "IEEE754Adder" is an NCD, version 3.2, device xc6slx75, package fgg676, speed -3
+	#Design creation date: 2019.09.09.17.05.24
+	#Building chip graphics...
+	#Loading speed info...
+	#1
+setattr main edit-mode no-logic-changes
+	#2
+unselect -all
+	#3
+select site 'SLICE_X14Y76'
+	#site "SLICE_X14Y76",  type = SLICEM  (RPM grid X41Y312)
+	#4
+unselect -all
+	#5
+select site 'SLICE_X14Y76'
+	#site "SLICE_X14Y76",  type = SLICEM  (RPM grid X41Y312)
+	#6
+post block
diff --git a/Normalizer.vhd b/Normalizer.vhd
index 8d43721..f3657dd 100644
--- a/Normalizer.vhd
+++ b/Normalizer.vhd
@@ -73,7 +73,6 @@ architecture NormalizerArch of Normalizer is
 	signal LEFT_SHIFT_AMOUNT: std_logic_vector(8 downto 0);
 	signal LEFT_SHIFTED_MANT: std_logic_vector(22 downto 0);
 	signal LEFT_SHIFTED_MANT_TMP: std_logic_vector(47 downto 0);
-	signal RIGHT_SHIFTED_MANT: std_logic_vector(22 downto 0);
 	signal FINAL_MANT: std_logic_vector(22 downto 0);
 
 begin
@@ -117,13 +116,11 @@ begin
 		end if;
 	end process;
 
-
-	RIGHT_SHIFTED_MANT <= '1' & MANT(47 downto 26);
 	SL: ShiftLeft48
 		port map ( N => MANT, PLACES => LEFT_SHIFT_AMOUNT, RESULT => LEFT_SHIFTED_MANT_TMP );
-	LEFT_SHIFTED_MANT <= LEFT_SHIFTED_MANT_TMP(47 downto 25);
+	LEFT_SHIFTED_MANT <= LEFT_SHIFTED_MANT_TMP(46 downto 24);
 	
-	final_process: process (SUM_OVERFLOW, IS_FINAL_EXP_MINIMUM, EXP_ADDSUB_RES, EXP_ADDSUB_OF, RIGHT_SHIFTED_MANT, LEFT_SHIFTED_MANT, EXP)
+	final_process: process (SUM_OVERFLOW, IS_FINAL_EXP_MINIMUM, EXP_ADDSUB_RES, EXP_ADDSUB_OF, LEFT_SHIFTED_MANT, EXP, MANT)
 		variable IS_INF : std_logic;
 		variable IS_INF_ORIGINAL_EXP : std_logic;
 		variable IS_INF_FINAL_EXP : std_logic;
@@ -144,7 +141,7 @@ begin
 		else
 			if (SUM_OVERFLOW = '1') then
 				FINAL_EXP <= EXP_ADDSUB_RES;
-				FINAL_MANT <= RIGHT_SHIFTED_MANT;
+				FINAL_MANT <= MANT(47 downto 25);
 			else
 				FINAL_EXP <= EXP_ADDSUB_RES;
 				FINAL_MANT <= LEFT_SHIFTED_MANT;			
diff --git a/fuse.log b/fuse.log
index 483896c..137405f 100644
--- a/fuse.log
+++ b/fuse.log
@@ -32,8 +32,8 @@ Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/IEEE754Adder.vhd" into library wo
 Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/IEEE754AdderTest.vhd" into library work
 Starting static elaboration
 Completed static elaboration
-Fuse Memory Usage: 97552 KB
-Fuse CPU Usage: 990 ms
+Fuse Memory Usage: 97548 KB
+Fuse CPU Usage: 950 ms
 Compiling package standard
 Compiling package std_logic_1164
 Compiling architecture flipflopdvectorarch of entity FlipFlopDVector [\FlipFlopDVector(32)\]
@@ -72,9 +72,9 @@ Compiling architecture stagethreearch of entity PipelineStageThree [pipelinestag
 Compiling architecture behavioral of entity IEEE754Adder [ieee754adder_default]
 Compiling architecture behavior of entity ieee754addertest
 Time Resolution for simulation is 1ps.
-Waiting for 2 sub-compilation(s) to finish...
+Waiting for 3 sub-compilation(s) to finish...
 Compiled 68 VHDL Units
 Built simulation executable /home/Luca/ISE/IEEE754Adder/IEEE754AdderTest_isim_beh.exe
-Fuse Memory Usage: 671904 KB
-Fuse CPU Usage: 1160 ms
-GCC CPU Usage: 1140 ms
+Fuse Memory Usage: 671896 KB
+Fuse CPU Usage: 1120 ms
+GCC CPU Usage: 1130 ms