Refactoring controllo NaN
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gbeccari committed
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commit
2ecaee1b19
23 files changed
+1337
-392
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+6
-35
@@ -85,6 +85,7 @@
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</transform>
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<transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1566052458">
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||||
<status xil_pn:value="SuccessfullyRun"/>
|
||||
<status xil_pn:value="ReadyToRun"/>
|
||||
</transform>
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||||
<transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1167941000477774584" xil_pn:start_ts="1566059978">
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<status xil_pn:value="SuccessfullyRun"/>
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@@ -110,8 +111,9 @@
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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</transform>
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||||
<transform xil_pn:end_ts="1566060235" xil_pn:in_ck="-3235492353642026610" xil_pn:name="TRANEXT_xstsynthesize_spartan3" xil_pn:prop_ck="-5588158190480725594" xil_pn:start_ts="1566060230">
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<transform xil_pn:end_ts="1566062385" xil_pn:in_ck="-3915287225243783751" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4591378050783358917" xil_pn:start_ts="1566062357">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="WarningsGenerated"/>
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<status xil_pn:value="ReadyToRun"/>
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<outfile xil_pn:name="SpecialCasesCheck.lso"/>
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<outfile xil_pn:name="SpecialCasesCheck.ngc"/>
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@@ -120,23 +122,22 @@
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<outfile xil_pn:name="SpecialCasesCheck.stx"/>
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<outfile xil_pn:name="SpecialCasesCheck.syr"/>
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<outfile xil_pn:name="SpecialCasesCheck.xst"/>
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<outfile xil_pn:name="SpecialCasesCheck_vhdl.prj"/>
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<outfile xil_pn:name="SpecialCasesCheck_xst.xrpt"/>
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<outfile xil_pn:name="TypeCheck.ngr"/>
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<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
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<outfile xil_pn:name="webtalk_pn.xml"/>
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<outfile xil_pn:name="xst"/>
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</transform>
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<transform xil_pn:end_ts="1566052811" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-2497314214044977511" xil_pn:start_ts="1566052811">
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<transform xil_pn:end_ts="1566062226" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="7014160488695491189" xil_pn:start_ts="1566062226">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForProperties"/>
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</transform>
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<transform xil_pn:end_ts="1566052856" xil_pn:in_ck="-1179315243053685338" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7709254264864982892" xil_pn:start_ts="1566052852">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="AbortedRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForInputs"/>
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<status xil_pn:value="OutOfDateForProperties"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<status xil_pn:value="InputAdded"/>
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<status xil_pn:value="InputChanged"/>
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<outfile xil_pn:name="TypeCheck.bld"/>
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@@ -145,39 +146,9 @@
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<outfile xil_pn:name="_ngo"/>
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<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1566052859" xil_pn:in_ck="-1179315243053685337" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-7868858794111860816" xil_pn:start_ts="1566052856">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<outfile xil_pn:name="TypeCheck.pcf"/>
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<outfile xil_pn:name="TypeCheck_map.map"/>
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<outfile xil_pn:name="TypeCheck_map.mrp"/>
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<outfile xil_pn:name="TypeCheck_map.ncd"/>
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<outfile xil_pn:name="TypeCheck_map.ngm"/>
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<outfile xil_pn:name="TypeCheck_map.xrpt"/>
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<outfile xil_pn:name="TypeCheck_summary.xml"/>
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<outfile xil_pn:name="TypeCheck_usage.xml"/>
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<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1566052863" xil_pn:in_ck="2083081054299762752" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="3266239339701135281" xil_pn:start_ts="1566052859">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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<outfile xil_pn:name="TypeCheck.ncd"/>
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<outfile xil_pn:name="TypeCheck.pad"/>
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<outfile xil_pn:name="TypeCheck.par"/>
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<outfile xil_pn:name="TypeCheck.ptwx"/>
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<outfile xil_pn:name="TypeCheck.unroutes"/>
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<outfile xil_pn:name="TypeCheck.xpi"/>
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<outfile xil_pn:name="TypeCheck_pad.csv"/>
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<outfile xil_pn:name="TypeCheck_pad.txt"/>
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<outfile xil_pn:name="TypeCheck_par.xrpt"/>
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<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
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</transform>
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<transform xil_pn:end_ts="1566052863" xil_pn:in_ck="-1179315243053685469" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416187" xil_pn:start_ts="1566052862">
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<status xil_pn:value="SuccessfullyRun"/>
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<status xil_pn:value="ReadyToRun"/>
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<status xil_pn:value="OutOfDateForPredecessor"/>
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||||
<outfile xil_pn:name="TypeCheck.twr"/>
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<outfile xil_pn:name="TypeCheck.twx"/>
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<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
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+66
-66
@@ -17,17 +17,21 @@
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<files>
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<file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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</file>
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<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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</file>
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<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
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<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
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<association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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</file>
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</files>
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<properties>
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<property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
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<property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
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@@ -41,8 +45,6 @@
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<property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
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<property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
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<property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
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<property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
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@@ -50,8 +52,8 @@
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<property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
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<property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
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<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
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<property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
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@@ -61,64 +63,65 @@
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<property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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<property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device" xil_pn:value="xc3s50" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
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||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
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||||
<property xil_pn:name="Device" xil_pn:value="xa6slx4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -137,12 +140,10 @@
|
||||
<property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -160,7 +161,6 @@
|
||||
<property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
@@ -173,29 +173,35 @@
|
||||
<property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
@@ -216,13 +222,13 @@
|
||||
<property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Package" xil_pn:value="csg225" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place & Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
@@ -231,9 +237,8 @@
|
||||
<property xil_pn:name="Post Place & Route Simulation Model Name" xil_pn:value="SpecialCasesCheck_timesim.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SpecialCasesCheck_synthesis.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SpecialCasesCheck_translate.vhd" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
|
||||
@@ -249,10 +254,9 @@
|
||||
<property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
|
||||
@@ -266,10 +270,10 @@
|
||||
<property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset DCM if SHUTDOWN & AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
@@ -278,7 +282,6 @@
|
||||
<property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
@@ -286,9 +289,10 @@
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
|
||||
@@ -303,14 +307,13 @@
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
|
||||
@@ -318,7 +321,7 @@
|
||||
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
@@ -331,28 +334,25 @@
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
|
||||
<!-- -->
|
||||
@@ -360,17 +360,17 @@
|
||||
<!-- -->
|
||||
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="YYYY-MM-DDTHH:MM:SS" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnableToCalculate" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Unknown" xil_pn:valueState="default"/>
|
||||
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-08-17T16:51:15" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="4B48FA10A560F77F46DA66FD7F346092" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
|
||||
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
|
||||
</properties>
|
||||
|
||||
<bindings/>
|
||||
|
||||
@@ -0,0 +1,38 @@
|
||||
library IEEE;
|
||||
use IEEE.STD_LOGIC_1164.ALL;
|
||||
|
||||
entity NaNCheck is
|
||||
port(
|
||||
X, Y: in std_logic_vector(31 downto 0);
|
||||
isNan: out std_logic
|
||||
);
|
||||
end NaNCheck;
|
||||
|
||||
architecture NaNCheckArch of NaNCheck is
|
||||
component TypeCheck is
|
||||
port(
|
||||
N: in std_logic_vector(31 downto 0);
|
||||
NaN, INF: out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal xNan: std_logic;
|
||||
signal xInf: std_logic;
|
||||
signal xSign: std_logic;
|
||||
signal yNan: std_logic;
|
||||
signal yInf: std_logic;
|
||||
signal ySign: std_logic;
|
||||
|
||||
begin
|
||||
xCheck: TypeCheck
|
||||
port map (N => X, NaN => xNan, INF => xInf);
|
||||
yCheck: TypeCheck
|
||||
port map (N => Y, NaN => yNan, INF => yInf);
|
||||
|
||||
xSign <= X(31);
|
||||
ySign <= Y(31);
|
||||
|
||||
isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign);
|
||||
|
||||
end NaNCheckArch;
|
||||
|
||||
@@ -5,3 +5,6 @@ xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn
|
||||
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr"
|
||||
@@ -1,3 +1,3 @@
|
||||
XILINX-XDB 0.1 STUB 0.1 ASCII
|
||||
XILINX-XDM V1.6e
|
||||
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|
||||
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|
||||
$b1x6d=(`fgn#d}j/fkbjko(ALON;8:Ndegq+KgIKaohg#xgd218+mijm&cxi"ifaolj+LCBM>??Mijjr.QsafofdJkxi~Mgebi-rmb639;0=<>4338JJUSS2G68=7>111906?OIX\^1T1=>:1<24>552@D[YY4V<2394;g<;;0E0>?50?c877<_4:;1<3o4338Z867=87>0MCJ=6:CM@7D6>2KEH9L>4:CM@=><J\YTECH@9:ALIHOS\LN<7N\JAUGG5>A43NDOj6IPcnosqqc)OV~f|<=4G^aliussm'MTx`~30?31?L653@;87D??3:K256=N9;90E<=<;H377>O6=;1B>?5F339J07=N=;1B:?5F739J<7=N1:1BBK:4IOD20>OIA]o0GHK__IKFVDTD@P=0@BIFC@N7?K:76<1E0<>15:L?54823G6:>3;4N=30:0=I48>596@314<6?K:6>7?0B1?8>49M84>9=2D7=40;;O>2:0=I4;:596@320<6?K:5:7?0B1<<>49M8729=2D7>80:;O>12;3<F58<285A<3:=1>H;:04?7C2=>49M8669?2D7?<4?>49M8679<2D7?3:4N=6=0>H;=7>0B1814:L?3;2<F52586@39?08JF5<FhD?7CoA199MeKEomja:7B:4OS357>IU::1D^9=4OS5`?U(588<;5<=PL59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ3:PWHg=TANH^_RGAFNc8WLAXJ\YBHUl4SHE\FPUIIDOm7^AZRBG\BLJBFHGNh6]@USAF[IOIMGH:=6]ebkbhFgtmzIcine;;U[SAc=SWjef|xzj.U]wiu753]Uhc`~ztd,W[qkw494:?6ZPcnosqqc)\V~f|1>11018PZeheyi#ZPtlr?4;46;2^Tobcuug-PZrjx5:5?<84T^aliussm'^Tx`~30?]jiu?<\pznOeklk89UM@QX\PZN86V30?78\9776<1S0<?15:Z?57823Q6:?3;4X=37:0=_48?596V317<6?]:6?7?0T1?7>49[84?9<2R7=3;4X=03:0=_4;;596V323<6?]:5;7?0T1<;>49[8739=2R7>;0:;Y>13;3<P583285W<3;=0>^;:7?0T1=?>69[867=87?0T1=>>59[86833Q6?295W<4<7?]:16=1S0:0;;Y>;:1=_404:h6VFLHL[)]BE(9$:,^ZZB!2-5%GTK@C=7U][LH@4?]USWNDO=h5WSU]JIUJBELD_MYG@N^ALJVRUI@D__<>4XRV\VQJXX[E[I_ZV6:ZgfZOc991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv:?]usODeoia:4Y=2=1>_;994>7T2>1?78]9756<1R0<=15:[?51823P6:93;4Y=35:0=^48=596W319<6?\:617>0U1?15:[?65823P69=3;4Y=01:0=^4;9596W325<6?\:5=7?0U1<9>49Z8719=2S7>50:;X>1=;2<Q58596W331<4?\:493:596W330<7?\:46=1R090;;X>6:1=^4?4?7T28>59Z8=833P62285fsOcm2>otFhd::6g|Zdpl2>~D`li`86vFng30?}OinVsXej`PAOF\57Yh9=1sEchPyRkdjZGILV;9Sb?>3:zJjcY~[`meSL@K_07\k42<p@dmSt]fgo]BJAY6=Ve:86vAao33?}g1{er?!>#lsf011c=i?ygt9m|g306)60<qJbnof:4yHle0>IigwKL}<79:BC|<4=N381=v]>0;;2>02=9:>::;?528db2~h?n3;0b4>56:&;a?>>3tYm64?555827171>8095ko9;e7f>5<628qX==461;77>4539?<:6?7ia79uB0>=83;1=7>tS029=4<2<3;88<891;0:bd0<,?=1>45+548ab>d2m3:18?4=:50xH=e=9r.>97lj;|N;`?4|,<i1=6`:d;68y!3a2<o0Vh4={485>x\2138p4775}h:2>5<#=>03<6`:6;28?l1a290/9:470:l62?7<3`=o6=4+568;4>h2>3807d9l:18'12<?82d>:7=4;h5a>5<#=>03<6`:6;68?l1f290/9:470:l62?3<3`=26=4+568;4>h2>3<07d97:18'12<?82d>:794;h54>5<#=>03<6`:6;:8?l11290/9:470:l62??<3`=>6=4+568;4>h2>3k07d9;:18'12<?82d>:7l4;h51>5<#=>03<6`:6;a8?l16290/9:470:l62?b<3`=;6=4+568;4>h2>3o07d8i:18'12<?82d>:7h4;h4f>5<#=>03<6`:6;33?>o1l3:1(895819m13<6921b:n4?:%74>=6<f<<1=?54i7`94?"2?32;7c;9:018?l0f290/9:470:l62?7332c=57>5$459<5=i=?0:965f8983>!3021:0b8851798m=1=83.>;76?;o75>41<3`2=6=4+568;4>h2>3;376g75;29 01=091e9;4>9:9j<1<72-?<65>4n4495d=<a191<7*:7;:3?k3128h07d6=:18'12<?82d>:7?l;:k4a?6=,<=14=5a5782`>=n?:0;6);8:928j00=9l10e;650;&63?>73g?=6<h4;hc`>5<#=>0jn6`:6;28?lgf290/9:4nb:l62?7<3`k36=4+568bf>h2>3807do8:18'12<fj2d>:7=4;hc5>5<#=>0jn6`:6;68?lg2290/9:4nb:l62?3<3`k?6=4+568bf>h2>3<07do<:18'12<fj2d>:794;hc1>5<#=>0jn6`:6;:8?lg6290/9:4nb:l62??<3`k;6=4+568bf>h2>3k07d7i:18'12<fj2d>:7l4;h;g>5<#=>0jn6`:6;a8?l?d290/9:4nb:l62?b<3`3i6=4+568bf>h2>3o07d7n:18'12<fj2d>:7h4;h;:>5<#=>0jn6`:6;33?>o>03:1(895ac9m13<6921b5:4?:%74>dd<f<<1=?54i8494?"2?3ki7c;9:018?l?2290/9:4nb:l62?7332c287>5$459eg=i=?0:965fb283>!302hh0b8851798mg4=83.>;7om;o75>41<3`h:6=4+568bf>h2>3;376gm0;29 01=ik1e9;4>9:9jec<72-?<6ll4n4495d=<aho1<7*:7;ca?k3128h07dok:18'12<fj2d>:7?l;:kb=?6=,<=1mo5a5782`>=n1l0;6);8:``8j00=9l10e4=50;&63?ge3g?=6<h4;n`7>5<<gk<1<75m8c83>4<729q/9k4>2:J;e>i693:17pl;b;2904<22==p@5m51zJ1<>{K0m09w);l:09m1a<612w/9k4;e:Xf>7}22?0vV8752z:9=?{n080;6);8:928j00=821b;k4?:%74>=6<f<<1=65f7e83>!3021:0b8852:9j3f<72-?<65>4n4497>=n?k0;6);8:928j00=<21b;l4?:%74>=6<f<<1965f7883>!3021:0b8856:9j3=<72-?<65>4n4493>=n?>0;6);8:928j00=021b;;4?:%74>=6<f<<1565f7483>!3021:0b885a:9j31<72-?<65>4n449f>=n?;0;6);8:928j00=k21b;<4?:%74>=6<f<<1h65f7183>!3021:0b885e:9j2c<72-?<65>4n449b>=n>l0;6);8:928j00=9910e;j50;&63?>73g?=6<?4;h4`>5<#=>03<6`:6;31?>o1j3:1(895819m13<6;21b:l4?:%74>=6<f<<1=954i7;94?"2?32;7c;9:078?l>?290/9:470:l62?7132c3;7>5$459<5=i=?0:;65f8783>!3021:0b8851998m=3=83.>;76?;o75>4?<3`2?6=4+568;4>h2>3;j76g73;29 01=091e9;4>b:9j<7<72-?<65>4n4495f=<a>o1<7*:7;:3?k3128n07d9<:18'12<?82d>:7?j;:k5<?6=,<=14=5a5782b>=nij0;6);8:``8j00=821bml4?:%74>dd<f<<1=65fa983>!302hh0b8852:9je2<72-?<6ll4n4497>=ni?0;6);8:``8j00=<21bm84?:%74>dd<f<<1965fa583>!302hh0b8856:9je6<72-?<6ll4n4493>=ni;0;6);8:``8j00=021bm<4?:%74>dd<f<<1565fa183>!302hh0b885a:9j=c<72-?<6ll4n449f>=n1m0;6);8:``8j00=k21b5n4?:%74>dd<f<<1h65f9c83>!302hh0b885e:9j=d<72-?<6ll4n449b>=n100;6);8:``8j00=9910e4650;&63?ge3g?=6<?4;h;4>5<#=>0jn6`:6;31?>o>>3:1(895ac9m13<6;21b584?:%74>dd<f<<1=954i8694?"2?3ki7c;9:078?ld4290/9:4nb:l62?7132ci>7>5$459eg=i=?0:;65fb083>!302hh0b8851998mg6=83.>;7om;o75>4?<3`km6=4+568bf>h2>3;j76gne;29 01=ik1e9;4>b:9jea<72-?<6ll4n4495f=<ah31<7*:7;ca?k3128n07d7j:18'12<fj2d>:7?j;:k:7?6=,<=1mo5a5782b>=hj=0;66lm7;2967<32;9p@5m51zJ1<>{K0m09w);l:19m1a<6j2w/9k496:Xf>4}32tP>57?t7;j06<72-?<69<4n4494>=n<80;6);8:508j00=921b?k4?:%74>14<f<<1>65f3d83>!302=80b8853:9j7a<72-?<69<4n4490>=n;j0;6);8:508j00==21b?o4?:%74>14<f<<1:65f3`83>!3Line truncated
|
||||
@@ -1,2 +1,3 @@
|
||||
vhdl work "TypeCheck.vhd"
|
||||
vhdl work "NaNCheck.vhd"
|
||||
vhdl work "SpecialCasesCheck.vhd"
|
||||
+109
-96
@@ -1,37 +1,42 @@
|
||||
Release 14.7 - xst P.20131013 (lin64)
|
||||
Release 14.7 - xst P.20160913 (lin64)
|
||||
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
|
||||
-->
|
||||
Parameter TMPDIR set to xst/projnav.tmp
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.05 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
-->
|
||||
Parameter xsthdpdir set to xst
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 0.00 secs
|
||||
Total CPU time to Xst completion: 0.05 secs
|
||||
Total CPU time to Xst completion: 0.09 secs
|
||||
|
||||
-->
|
||||
Reading design: SpecialCasesCheck.prj
|
||||
|
||||
TABLE OF CONTENTS
|
||||
1) Synthesis Options Summary
|
||||
2) HDL Compilation
|
||||
3) Design Hierarchy Analysis
|
||||
4) HDL Analysis
|
||||
5) HDL Synthesis
|
||||
5.1) HDL Synthesis Report
|
||||
6) Advanced HDL Synthesis
|
||||
6.1) Advanced HDL Synthesis Report
|
||||
7) Low Level Synthesis
|
||||
8) Partition Report
|
||||
9) Final Report
|
||||
9.1) Device utilization summary
|
||||
9.2) Partition Resource Summary
|
||||
9.3) TIMING REPORT
|
||||
2) HDL Parsing
|
||||
3) HDL Elaboration
|
||||
4) HDL Synthesis
|
||||
4.1) HDL Synthesis Report
|
||||
5) Advanced HDL Synthesis
|
||||
5.1) Advanced HDL Synthesis Report
|
||||
6) Low Level Synthesis
|
||||
7) Partition Report
|
||||
8) Design Summary
|
||||
8.1) Primitive and Black Box Usage
|
||||
8.2) Device utilization summary
|
||||
8.3) Partition Resource Summary
|
||||
8.4) Timing Report
|
||||
8.4.1) Clock Information
|
||||
8.4.2) Asynchronous Control Signals Information
|
||||
8.4.3) Timing Summary
|
||||
8.4.4) Timing Details
|
||||
8.4.5) Cross Clock Domains Report
|
||||
|
||||
|
||||
=========================================================================
|
||||
@@ -39,13 +44,12 @@ TABLE OF CONTENTS
|
||||
=========================================================================
|
||||
---- Source Parameters
|
||||
Input File Name : "SpecialCasesCheck.prj"
|
||||
Input Format : mixed
|
||||
Ignore Synthesis Constraint File : NO
|
||||
|
||||
---- Target Parameters
|
||||
Output File Name : "SpecialCasesCheck"
|
||||
Output Format : NGC
|
||||
Target Device : xc3s50-5-pq208
|
||||
Target Device : xa6slx4-3-csg225
|
||||
|
||||
---- Source Options
|
||||
Top Module Name : SpecialCasesCheck
|
||||
@@ -56,25 +60,21 @@ FSM Style : LUT
|
||||
RAM Extraction : Yes
|
||||
RAM Style : Auto
|
||||
ROM Extraction : Yes
|
||||
Mux Style : Auto
|
||||
Decoder Extraction : YES
|
||||
Priority Encoder Extraction : Yes
|
||||
Shift Register Extraction : YES
|
||||
Logical Shifter Extraction : YES
|
||||
XOR Collapsing : YES
|
||||
ROM Style : Auto
|
||||
Mux Extraction : Yes
|
||||
Resource Sharing : YES
|
||||
Asynchronous To Synchronous : NO
|
||||
Multiplier Style : Auto
|
||||
Shift Register Minimum Size : 2
|
||||
Use DSP Block : Auto
|
||||
Automatic Register Balancing : No
|
||||
|
||||
---- Target Options
|
||||
LUT Combining : Auto
|
||||
Reduce Control Sets : Auto
|
||||
Add IO Buffers : YES
|
||||
Global Maximum Fanout : 500
|
||||
Add Generic Clock Buffer(BUFG) : 8
|
||||
Global Maximum Fanout : 100000
|
||||
Add Generic Clock Buffer(BUFG) : 32
|
||||
Register Duplication : YES
|
||||
Slice Packing : YES
|
||||
Optimize Instantiated Primitives : NO
|
||||
Use Clock Enable : Yes
|
||||
Use Synchronous Set : Yes
|
||||
@@ -85,6 +85,7 @@ Equivalent register Removal : YES
|
||||
---- General Options
|
||||
Optimization Goal : Speed
|
||||
Optimization Effort : 1
|
||||
Power Reduction : NO
|
||||
Keep Hierarchy : No
|
||||
Netlist Hierarchy : As_Optimized
|
||||
RTL Output : Yes
|
||||
@@ -97,7 +98,7 @@ Bus Delimiter : <>
|
||||
Case Specifier : Maintain
|
||||
Slice Utilization Ratio : 100
|
||||
BRAM Utilization Ratio : 100
|
||||
Verilog 2001 : YES
|
||||
DSP48 Utilization Ratio : 100
|
||||
Auto BRAM Packing : NO
|
||||
Slice Utilization Ratio Delta : 5
|
||||
|
||||
@@ -105,48 +106,50 @@ Slice Utilization Ratio Delta : 5
|
||||
|
||||
|
||||
=========================================================================
|
||||
* HDL Compilation *
|
||||
* HDL Parsing *
|
||||
=========================================================================
|
||||
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" in Library work.
|
||||
Architecture typecheckarch of Entity typecheck is up to date.
|
||||
Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work.
|
||||
Entity <specialcasescheck> compiled.
|
||||
Entity <specialcasescheck> (Architecture <specialcasescheckarch>) compiled.
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TypeCheck.vhd" into library work
|
||||
Parsing entity <TypeCheck>.
|
||||
Parsing architecture <TypeCheckArch> of entity <typecheck>.
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/NaNCheck.vhd" into library work
|
||||
Parsing entity <NaNCheck>.
|
||||
Parsing architecture <NaNCheckArch> of entity <nancheck>.
|
||||
Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd" into library work
|
||||
Parsing entity <SpecialCasesCheck>.
|
||||
Parsing architecture <SpecialCasesCheckArch> of entity <specialcasescheck>.
|
||||
|
||||
=========================================================================
|
||||
* Design Hierarchy Analysis *
|
||||
* HDL Elaboration *
|
||||
=========================================================================
|
||||
Analyzing hierarchy for entity <SpecialCasesCheck> in library <work> (architecture <specialcasescheckarch>).
|
||||
|
||||
Analyzing hierarchy for entity <TypeCheck> in library <work> (architecture <typecheckarch>).
|
||||
Elaborating entity <SpecialCasesCheck> (architecture <SpecialCasesCheckArch>) from library <work>.
|
||||
|
||||
Elaborating entity <NaNCheck> (architecture <NaNCheckArch>) from library <work>.
|
||||
|
||||
=========================================================================
|
||||
* HDL Analysis *
|
||||
=========================================================================
|
||||
Analyzing Entity <SpecialCasesCheck> in library <work> (Architecture <specialcasescheckarch>).
|
||||
Entity <SpecialCasesCheck> analyzed. Unit <SpecialCasesCheck> generated.
|
||||
|
||||
Analyzing Entity <TypeCheck> in library <work> (Architecture <typecheckarch>).
|
||||
Entity <TypeCheck> analyzed. Unit <TypeCheck> generated.
|
||||
|
||||
Elaborating entity <TypeCheck> (architecture <TypeCheckArch>) from library <work>.
|
||||
|
||||
=========================================================================
|
||||
* HDL Synthesis *
|
||||
=========================================================================
|
||||
|
||||
Performing bidirectional port resolution...
|
||||
|
||||
Synthesizing Unit <TypeCheck>.
|
||||
Related source file is "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd".
|
||||
WARNING:Xst:647 - Input <N<31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
Unit <TypeCheck> synthesized.
|
||||
|
||||
|
||||
Synthesizing Unit <SpecialCasesCheck>.
|
||||
Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd".
|
||||
Related source file is "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd".
|
||||
Summary:
|
||||
no macro.
|
||||
Unit <SpecialCasesCheck> synthesized.
|
||||
|
||||
Synthesizing Unit <NaNCheck>.
|
||||
Related source file is "/home/ise/gianni/IEEE754Adder/NaNCheck.vhd".
|
||||
Summary:
|
||||
no macro.
|
||||
Unit <NaNCheck> synthesized.
|
||||
|
||||
Synthesizing Unit <TypeCheck>.
|
||||
Related source file is "/home/ise/gianni/IEEE754Adder/TypeCheck.vhd".
|
||||
WARNING:Xst:647 - Input <N<31:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
Summary:
|
||||
no macro.
|
||||
Unit <TypeCheck> synthesized.
|
||||
|
||||
=========================================================================
|
||||
HDL Synthesis Report
|
||||
@@ -173,7 +176,7 @@ Optimizing unit <SpecialCasesCheck> ...
|
||||
|
||||
Mapping all equations...
|
||||
Building and optimizing final netlist ...
|
||||
Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 1.
|
||||
Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 0.
|
||||
|
||||
Final Macro Processing ...
|
||||
|
||||
@@ -195,38 +198,45 @@ Partition Implementation Status
|
||||
-------------------------------
|
||||
|
||||
=========================================================================
|
||||
* Final Report *
|
||||
* Design Summary *
|
||||
=========================================================================
|
||||
Final Results
|
||||
RTL Top Level Output File Name : SpecialCasesCheck.ngr
|
||||
Top Level Output File Name : SpecialCasesCheck
|
||||
Output Format : NGC
|
||||
Optimization Goal : Speed
|
||||
Keep Hierarchy : No
|
||||
|
||||
Design Statistics
|
||||
# IOs : 66
|
||||
Top Level Output File Name : SpecialCasesCheck.ngc
|
||||
|
||||
Cell Usage :
|
||||
# BELS : 24
|
||||
Primitive and Black Box Usage:
|
||||
------------------------------
|
||||
# BELS : 16
|
||||
# GND : 1
|
||||
# LUT2 : 1
|
||||
# LUT3 : 2
|
||||
# LUT4 : 20
|
||||
# LUT4 : 2
|
||||
# LUT5 : 2
|
||||
# LUT6 : 9
|
||||
# IO Buffers : 66
|
||||
# IBUF : 64
|
||||
# OBUF : 2
|
||||
=========================================================================
|
||||
|
||||
Device utilization summary:
|
||||
---------------------------
|
||||
|
||||
Selected Device : 3s50pq208-5
|
||||
Selected Device : xa6slx4csg225-3
|
||||
|
||||
Number of Slices: 13 out of 768 1%
|
||||
Number of 4 input LUTs: 23 out of 1536 1%
|
||||
|
||||
Slice Logic Utilization:
|
||||
Number of Slice LUTs: 15 out of 2400 0%
|
||||
Number used as Logic: 15 out of 2400 0%
|
||||
|
||||
Slice Logic Distribution:
|
||||
Number of LUT Flip Flop pairs used: 15
|
||||
Number with an unused Flip Flop: 15 out of 15 100%
|
||||
Number with an unused LUT: 0 out of 15 0%
|
||||
Number of fully used LUT-FF pairs: 0 out of 15 0%
|
||||
Number of unique control sets: 0
|
||||
|
||||
IO Utilization:
|
||||
Number of IOs: 66
|
||||
Number of bonded IOBs: 66 out of 124 53%
|
||||
Number of bonded IOBs: 66 out of 132 50%
|
||||
|
||||
Specific Feature Utilization:
|
||||
|
||||
---------------------------
|
||||
Partition Resource Summary:
|
||||
@@ -238,7 +248,7 @@ Partition Resource Summary:
|
||||
|
||||
|
||||
=========================================================================
|
||||
TIMING REPORT
|
||||
Timing Report
|
||||
|
||||
NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
|
||||
FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
|
||||
@@ -254,50 +264,53 @@ No asynchronous control signals found in this design
|
||||
|
||||
Timing Summary:
|
||||
---------------
|
||||
Speed Grade: -5
|
||||
Speed Grade: -3
|
||||
|
||||
Minimum period: No path found
|
||||
Minimum input arrival time before clock: No path found
|
||||
Maximum output required time after clock: No path found
|
||||
Maximum combinational path delay: 13.307ns
|
||||
Maximum combinational path delay: 7.532ns
|
||||
|
||||
Timing Detail:
|
||||
--------------
|
||||
Timing Details:
|
||||
---------------
|
||||
All values displayed in nanoseconds (ns)
|
||||
|
||||
=========================================================================
|
||||
Timing constraint: Default path analysis
|
||||
Total number of paths / destination ports: 72 / 1
|
||||
Total number of paths / destination ports: 64 / 1
|
||||
-------------------------------------------------------------------------
|
||||
Delay: 13.307ns (Levels of Logic = 7)
|
||||
Source: Y<8> (PAD)
|
||||
Delay: 7.532ns (Levels of Logic = 5)
|
||||
Source: Y<4> (PAD)
|
||||
Destination: isNan (PAD)
|
||||
|
||||
Data Path: Y<8> to isNan
|
||||
Data Path: Y<4> to isNan
|
||||
Gate Net
|
||||
Cell:in->out fanout Delay Delay Logical Name (Net Name)
|
||||
---------------------------------------- ------------
|
||||
IBUF:I->O 1 0.715 0.976 Y_8_IBUF (Y_8_IBUF)
|
||||
LUT4:I0->O 1 0.479 0.976 isNan35 (isNan35)
|
||||
LUT2:I0->O 1 0.479 0.704 isNan41 (isNan41)
|
||||
LUT4:I3->O 1 0.479 0.976 isNan61 (isNan61)
|
||||
LUT3:I0->O 1 0.479 0.976 isNan209_SW0 (N6)
|
||||
LUT4:I0->O 1 0.479 0.681 isNan209 (isNan_OBUF)
|
||||
OBUF:I->O 4.909 isNan_OBUF (isNan)
|
||||
IBUF:I->O 1 1.222 0.944 Y_4_IBUF (Y_4_IBUF)
|
||||
LUT6:I0->O 1 0.203 0.924 NC/isNan11 (NC/isNan10)
|
||||
LUT6:I1->O 1 0.203 0.684 NC/isNan12 (NC/isNan11)
|
||||
LUT6:I4->O 1 0.203 0.579 NC/isNan13 (isNan_OBUF)
|
||||
OBUF:I->O 2.571 isNan_OBUF (isNan)
|
||||
----------------------------------------
|
||||
Total 13.307ns (8.019ns logic, 5.288ns route)
|
||||
(60.3% logic, 39.7% route)
|
||||
Total 7.532ns (4.402ns logic, 3.130ns route)
|
||||
(58.4% logic, 41.6% route)
|
||||
|
||||
=========================================================================
|
||||
|
||||
Cross Clock Domains Report:
|
||||
--------------------------
|
||||
|
||||
=========================================================================
|
||||
|
||||
|
||||
Total REAL time to Xst completion: 3.00 secs
|
||||
Total CPU time to Xst completion: 3.05 secs
|
||||
Total REAL time to Xst completion: 22.00 secs
|
||||
Total CPU time to Xst completion: 19.75 secs
|
||||
|
||||
-->
|
||||
|
||||
|
||||
Total memory usage is 606300 kilobytes
|
||||
Total memory usage is 473740 kilobytes
|
||||
|
||||
Number of errors : 0 ( 0 filtered)
|
||||
Number of warnings : 1 ( 0 filtered)
|
||||
|
||||
+6
-13
@@ -10,33 +10,26 @@ end SpecialCasesCheck;
|
||||
|
||||
|
||||
architecture SpecialCasesCheckArch of SpecialCasesCheck is
|
||||
component TypeCheck is
|
||||
component NaNCheck is
|
||||
port(
|
||||
N: in std_logic_vector(31 downto 0);
|
||||
NaN, INF: out std_logic
|
||||
X, Y: in std_logic_vector(31 downto 0);
|
||||
isNan: out std_logic
|
||||
);
|
||||
end component;
|
||||
|
||||
signal xNan: std_logic;
|
||||
signal xInf: std_logic;
|
||||
|
||||
signal xSign: std_logic;
|
||||
signal yNan: std_logic;
|
||||
signal yInf: std_logic;
|
||||
signal ySign: std_logic;
|
||||
signal isSameAbsValue: std_logic;
|
||||
|
||||
begin
|
||||
xCheck: TypeCheck
|
||||
port map (N => X, NaN => xNan, INF => xInf);
|
||||
yCheck: TypeCheck
|
||||
port map (N => Y, NaN => yNan, INF => yInf);
|
||||
NC: NaNCheck
|
||||
port map (X => X, Y => Y, isNan => isNan);
|
||||
|
||||
xSign <= X(31);
|
||||
ySign <= Y(31);
|
||||
|
||||
isSameAbsValue <= '0'; -- TODO
|
||||
|
||||
isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign);
|
||||
isZero <= (xSign and (not ySign) and isSameAbsValue) or ((not xSign) and ySign and isSameAbsValue);
|
||||
end SpecialCasesCheckArch;
|
||||
|
||||
|
||||
+9
-13
@@ -2,13 +2,13 @@ set -tmpdir "xst/projnav.tmp"
|
||||
set -xsthdpdir "xst"
|
||||
run
|
||||
-ifn SpecialCasesCheck.prj
|
||||
-ifmt mixed
|
||||
-ofn SpecialCasesCheck
|
||||
-ofmt NGC
|
||||
-p xc3s50-5-pq208
|
||||
-p xa6slx4-3-csg225
|
||||
-top SpecialCasesCheck
|
||||
-opt_mode Speed
|
||||
-opt_level 1
|
||||
-power NO
|
||||
-iuc NO
|
||||
-keep_hierarchy No
|
||||
-netlist_hierarchy As_Optimized
|
||||
@@ -22,31 +22,27 @@ run
|
||||
-case Maintain
|
||||
-slice_utilization_ratio 100
|
||||
-bram_utilization_ratio 100
|
||||
-verilog2001 YES
|
||||
-dsp_utilization_ratio 100
|
||||
-lc Auto
|
||||
-reduce_control_sets Auto
|
||||
-fsm_extract YES -fsm_encoding Auto
|
||||
-safe_implementation No
|
||||
-fsm_style LUT
|
||||
-ram_extract Yes
|
||||
-ram_style Auto
|
||||
-rom_extract Yes
|
||||
-mux_style Auto
|
||||
-decoder_extract YES
|
||||
-priority_extract Yes
|
||||
-shreg_extract YES
|
||||
-shift_extract YES
|
||||
-xor_collapse YES
|
||||
-rom_style Auto
|
||||
-auto_bram_packing NO
|
||||
-mux_extract Yes
|
||||
-resource_sharing YES
|
||||
-async_to_sync NO
|
||||
-mult_style Auto
|
||||
-shreg_min_size 2
|
||||
-use_dsp48 Auto
|
||||
-iobuf YES
|
||||
-max_fanout 500
|
||||
-bufg 8
|
||||
-max_fanout 100000
|
||||
-bufg 32
|
||||
-register_duplication YES
|
||||
-register_balancing No
|
||||
-slice_packing YES
|
||||
-optimize_primitives NO
|
||||
-use_clock_enable Yes
|
||||
-use_sync_set Yes
|
||||
|
||||
@@ -15,14 +15,21 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td>LD_LIBRARY_PATH</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>LMC_HOME</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64</td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PATH</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/ise/bin</td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
@@ -74,12 +81,6 @@
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ifmt</td>
|
||||
<td> </td>
|
||||
<td>mixed</td>
|
||||
<td>MIXED</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofn</td>
|
||||
<td> </td>
|
||||
<td>SpecialCasesCheck</td>
|
||||
@@ -94,7 +95,7 @@
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xc3s50-5-pq208</td>
|
||||
<td>xa6slx4-3-csg225</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
@@ -107,7 +108,7 @@
|
||||
<td>-opt_mode</td>
|
||||
<td>Optimization Goal</td>
|
||||
<td>Speed</td>
|
||||
<td>SPEED</td>
|
||||
<td>Speed</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_level</td>
|
||||
@@ -116,52 +117,58 @@
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-power</td>
|
||||
<td>Power Reduction</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iuc</td>
|
||||
<td>Use synthesis Constraints File</td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-keep_hierarchy</td>
|
||||
<td>Keep Hierarchy</td>
|
||||
<td>No</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-netlist_hierarchy</td>
|
||||
<td>Netlist Hierarchy</td>
|
||||
<td>As_Optimized</td>
|
||||
<td>as_optimized</td>
|
||||
<td>As_Optimized</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rtlview</td>
|
||||
<td>Generate RTL Schematic</td>
|
||||
<td>Yes</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-glob_opt</td>
|
||||
<td>Global Optimization Goal</td>
|
||||
<td>AllClockNets</td>
|
||||
<td>ALLCLOCKNETS</td>
|
||||
<td>AllClockNets</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-read_cores</td>
|
||||
<td>Read Cores</td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-write_timing_constraints</td>
|
||||
<td>Write Timing Constraints</td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-cross_clock_analysis</td>
|
||||
<td>Cross Clock Analysis</td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bus_delimiter</td>
|
||||
@@ -173,37 +180,43 @@
|
||||
<td>-slice_utilization_ratio</td>
|
||||
<td>Slice Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100%</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bram_utilization_ratio</td>
|
||||
<td>BRAM Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100%</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-verilog2001</td>
|
||||
<td>Verilog 2001</td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
<td>-dsp_utilization_ratio</td>
|
||||
<td>DSP Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-reduce_control_sets</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_encoding</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-safe_implementation</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_style</td>
|
||||
@@ -215,127 +228,127 @@
|
||||
<td>-ram_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ram_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-shreg_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-auto_bram_packing</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-resource_sharing</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-async_to_sync</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-mult_style</td>
|
||||
<td>-use_dsp48</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iobuf</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-max_fanout</td>
|
||||
<td> </td>
|
||||
<td>500</td>
|
||||
<td>500</td>
|
||||
<td>100000</td>
|
||||
<td>100000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bufg</td>
|
||||
<td> </td>
|
||||
<td>8</td>
|
||||
<td>8</td>
|
||||
<td>32</td>
|
||||
<td>16</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_duplication</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_balancing</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-optimize_primitives</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_clock_enable</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_set</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_reset</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>YES</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iob</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>AUTO</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-equivalent_register_removal</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-slice_utilization_ratio_maxmargin</td>
|
||||
<td> </td>
|
||||
<td>5</td>
|
||||
<td>0%</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Operating System Information"></A>
|
||||
@@ -352,28 +365,28 @@
|
||||
</tr>
|
||||
<tr>
|
||||
<td>CPU Architecture/Speed</td>
|
||||
<td>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</td>
|
||||
<td>Intel(R) Core(TM) i7-5500U CPU @ 2.40GHz/2394.454 MHz</td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Host</td>
|
||||
<td>Xilinx</td>
|
||||
<td>localhost.localdomain</td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Name</td>
|
||||
<td>CentOS</td>
|
||||
<td>OracleServer</td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Release</td>
|
||||
<td>CentOS release 6.10 (Final)</td>
|
||||
<td>Oracle Linux Server release 6.4</td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
<td><font color=gray>< data not available ></font></td>
|
||||
|
||||
@@ -2,7 +2,7 @@
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>SpecialCasesCheck Project Status (08/17/2019 - 16:41:04)</B></TD></TR>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>SpecialCasesCheck Project Status (08/17/2019 - 17:19:45)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>IEEE754Adder.xise</TD>
|
||||
@@ -17,14 +17,15 @@
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD>xc3s50-5pq208</TD>
|
||||
<TD>xa6slx4-3csg225</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
<TD>
|
||||
No Errors</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/*.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
@@ -42,7 +43,7 @@
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_envsettings.html'>
|
||||
<A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/SpecialCasesCheck_envsettings.html'>
|
||||
System Settings</A>
|
||||
</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
|
||||
@@ -52,7 +53,26 @@ System Settings</A>
|
||||
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
|
||||
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
|
||||
<TD ALIGN=RIGHT>15</TD>
|
||||
<TD ALIGN=RIGHT>2400</TD>
|
||||
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>15</TD>
|
||||
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
|
||||
<TD ALIGN=RIGHT>66</TD>
|
||||
<TD ALIGN=RIGHT>132</TD>
|
||||
<TD ALIGN=RIGHT COLSPAN='2'>50%</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
@@ -64,7 +84,7 @@ System Settings</A>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 17 16:39:00 2019</TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 17 17:19:45 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/xst.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Translation Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Map Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Place and Route Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
@@ -78,5 +98,5 @@ System Settings</A>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 08/17/2019 - 16:41:04</center>
|
||||
<br><center><b>Date Generated:</b> 08/17/2019 - 17:19:45</center>
|
||||
</BODY></HTML>
|
||||
+72
-85
@@ -5,7 +5,7 @@
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
|
||||
<application stringID="Xst" timeStamp="Sat Aug 17 18:43:52 2019">
|
||||
<application stringID="Xst" timeStamp="Sat Aug 17 17:19:23 2019">
|
||||
<section stringID="User_Env">
|
||||
<table stringID="User_EnvVar">
|
||||
<column stringID="variable"/>
|
||||
@@ -16,7 +16,7 @@
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="variable" value="LD_LIBRARY_PATH"/>
|
||||
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
|
||||
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="variable" value="XILINX_EDK"/>
|
||||
@@ -24,98 +24,86 @@
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="variable" value="PATH"/>
|
||||
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/Luca/bin"/>
|
||||
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/ise/bin"/>
|
||||
</row>
|
||||
<row stringID="row" value="4">
|
||||
<item stringID="variable" value="LMC_HOME"/>
|
||||
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<item stringID="variable" value="XILINX_PLANAHEAD"/>
|
||||
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/PlanAhead"/>
|
||||
</row>
|
||||
<row stringID="row" value="5">
|
||||
<row stringID="row" value="6">
|
||||
<item stringID="variable" value="XILINX"/>
|
||||
<item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
|
||||
</row>
|
||||
</table>
|
||||
<item stringID="User_EnvOs" value="OS Information">
|
||||
<item stringID="User_EnvOsname" value="CentOS"/>
|
||||
<item stringID="User_EnvOsrelease" value="CentOS release 6.10 (Final)"/>
|
||||
<item stringID="User_EnvOsname" value="OracleServer"/>
|
||||
<item stringID="User_EnvOsrelease" value="Oracle Linux Server release 6.4"/>
|
||||
</item>
|
||||
<item stringID="User_EnvHost" value="Xilinx"/>
|
||||
<item stringID="User_EnvHost" value="localhost.localdomain"/>
|
||||
<table stringID="User_EnvCpu">
|
||||
<column stringID="arch"/>
|
||||
<column stringID="speed"/>
|
||||
<row stringID="row" value="0">
|
||||
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
|
||||
<item stringID="speed" value="2494.222 MHz"/>
|
||||
</row>
|
||||
<row stringID="row" value="1">
|
||||
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
|
||||
<item stringID="speed" value="2494.222 MHz"/>
|
||||
</row>
|
||||
<row stringID="row" value="2">
|
||||
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
|
||||
<item stringID="speed" value="2494.222 MHz"/>
|
||||
</row>
|
||||
<row stringID="row" value="3">
|
||||
<item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
|
||||
<item stringID="speed" value="2494.222 MHz"/>
|
||||
<item stringID="arch" value="Intel(R) Core(TM) i7-5500U CPU @ 2.40GHz"/>
|
||||
<item stringID="speed" value="2394.454 MHz"/>
|
||||
</row>
|
||||
</table>
|
||||
</section>
|
||||
<section stringID="XST_OPTION_SUMMARY">
|
||||
<item DEFAULT="" label="-ifn" stringID="XST_IFN" value="SpecialCasesCheck.prj"/>
|
||||
<item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
|
||||
<item DEFAULT="" label="-ofn" stringID="XST_OFN" value="SpecialCasesCheck"/>
|
||||
<item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
|
||||
<item DEFAULT="" label="-p" stringID="XST_P" value="xc3s50-5-pq208"/>
|
||||
<item DEFAULT="" label="-p" stringID="XST_P" value="xa6slx4-3-csg225"/>
|
||||
<item DEFAULT="" label="-top" stringID="XST_TOP" value="SpecialCasesCheck"/>
|
||||
<item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
|
||||
<item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
|
||||
<item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
|
||||
<item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
|
||||
<item DEFAULT="NO" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
|
||||
<item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
|
||||
<item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
|
||||
<item DEFAULT="ALLCLOCKNETS" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
|
||||
<item DEFAULT="YES" label="-read_cores" stringID="XST_READCORES" value="YES"/>
|
||||
<item DEFAULT="NO" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
|
||||
<item DEFAULT="NO" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
|
||||
<item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/>
|
||||
<item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/>
|
||||
<item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
|
||||
<item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
|
||||
<item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
|
||||
<item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
|
||||
<item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
|
||||
<item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
|
||||
<item DEFAULT="No" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
|
||||
<item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
|
||||
<item DEFAULT="<>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="<>"/>
|
||||
<item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
|
||||
<item DEFAULT="100%" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="100%" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
|
||||
<item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
|
||||
<item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
|
||||
<item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
|
||||
<item DEFAULT="Maintain" stringID="XST_CASE" value="Maintain"/>
|
||||
<item DEFAULT="100" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="100" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="100" label="-dsp_utilization_ratio" stringID="XST_DSPUTILIZATIONRATIO" value="100"/>
|
||||
<item DEFAULT="Auto" stringID="XST_LC" value="Auto"/>
|
||||
<item DEFAULT="Auto" label="-reduce_control_sets" stringID="XST_REDUCECONTROLSETS" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
|
||||
<item DEFAULT="Auto" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
|
||||
<item DEFAULT="No" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
|
||||
<item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
|
||||
<item DEFAULT="YES" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="AUTO" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="YES" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="AUTO" stringID="XST_MUXSTYLE" value="Auto"/>
|
||||
<item DEFAULT="NO" stringID="XST_DECODEREXTRACT" value="YES"/>
|
||||
<item DEFAULT="NO" stringID="XST_PRIORITYEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="YES" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
|
||||
<item DEFAULT="YES" stringID="XST_SHIFTEXTRACT" value="YES"/>
|
||||
<item DEFAULT="YES" stringID="XST_XORCOLLAPSE" value="YES"/>
|
||||
<item DEFAULT="AUTO" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="NO" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
|
||||
<item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
|
||||
<item DEFAULT="NO" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
|
||||
<item DEFAULT="AUTO" label="-mult_style" stringID="XST_MULTSTYLE" value="Auto"/>
|
||||
<item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
|
||||
<item DEFAULT="500" label="-max_fanout" stringID="XST_MAXFANOUT" value="500"/>
|
||||
<item DEFAULT="8" label="-bufg" stringID="XST_BUFG" value="8"/>
|
||||
<item DEFAULT="YES" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
|
||||
<item DEFAULT="NO" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
|
||||
<item DEFAULT="YES" stringID="XST_SLICEPACKING" value="YES"/>
|
||||
<item DEFAULT="NO" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
|
||||
<item DEFAULT="YES" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Yes"/>
|
||||
<item DEFAULT="YES" label="-use_sync_set" stringID="XST_USESYNCSET" value="Yes"/>
|
||||
<item DEFAULT="YES" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Yes"/>
|
||||
<item DEFAULT="AUTO" label="-iob" stringID="XST_IOB" value="Auto"/>
|
||||
<item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
|
||||
<item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
|
||||
<item DEFAULT="Yes" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="Auto" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
|
||||
<item DEFAULT="Yes" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
|
||||
<item DEFAULT="Auto" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
|
||||
<item DEFAULT="No" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
|
||||
<item DEFAULT="Yes" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
|
||||
<item DEFAULT="No" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
|
||||
<item DEFAULT="2" stringID="XST_SHREGMINSIZE" value="2"/>
|
||||
<item DEFAULT="Auto" label="-use_dsp48" stringID="XST_USEDSP48" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
|
||||
<item DEFAULT="100000" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
|
||||
<item DEFAULT="16" label="-bufg" stringID="XST_BUFG" value="32"/>
|
||||
<item DEFAULT="Yes" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
|
||||
<item DEFAULT="No" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
|
||||
<item DEFAULT="No" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
|
||||
<item DEFAULT="Auto" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Yes"/>
|
||||
<item DEFAULT="Auto" label="-use_sync_set" stringID="XST_USESYNCSET" value="Yes"/>
|
||||
<item DEFAULT="Auto" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Yes"/>
|
||||
<item DEFAULT="Auto" label="-iob" stringID="XST_IOB" value="Auto"/>
|
||||
<item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
|
||||
<item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
|
||||
</section>
|
||||
<section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
|
||||
<section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
|
||||
@@ -124,23 +112,17 @@
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_FINAL_REPORT">
|
||||
<section stringID="XST_FINAL_RESULTS">
|
||||
<item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck.ngr"/>
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck"/>
|
||||
<item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
|
||||
<item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
|
||||
<item stringID="XST_KEEP_HIERARCHY" value="No"/>
|
||||
<section stringID="XST_DESIGN_SUMMARY">
|
||||
<section stringID="XST_">
|
||||
<item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck.ngc"/>
|
||||
</section>
|
||||
<section stringID="XST_DESIGN_STATISTICS">
|
||||
<item stringID="XST_IOS" value="66"/>
|
||||
</section>
|
||||
<section stringID="XST_CELL_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="24">
|
||||
<section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
|
||||
<item dataType="int" stringID="XST_BELS" value="16">
|
||||
<item dataType="int" stringID="XST_GND" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT2" value="1"/>
|
||||
<item dataType="int" stringID="XST_LUT3" value="2"/>
|
||||
<item dataType="int" stringID="XST_LUT4" value="20"/>
|
||||
<item dataType="int" stringID="XST_LUT4" value="2"/>
|
||||
<item dataType="int" stringID="XST_LUT5" value="2"/>
|
||||
<item dataType="int" stringID="XST_LUT6" value="9"/>
|
||||
</item>
|
||||
<item dataType="int" stringID="XST_IO_BUFFERS" value="66">
|
||||
<item dataType="int" stringID="XST_IBUF" value="64"/>
|
||||
@@ -149,11 +131,16 @@
|
||||
</section>
|
||||
</section>
|
||||
<section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
|
||||
<item stringID="XST_SELECTED_DEVICE" value="3s50pq208-5"/>
|
||||
<item AVAILABLE="768" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="13"/>
|
||||
<item AVAILABLE="1536" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="23"/>
|
||||
<item stringID="XST_SELECTED_DEVICE" value="xa6slx4csg225-3"/>
|
||||
<item AVAILABLE="2400" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="15"/>
|
||||
<item AVAILABLE="2400" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="15"/>
|
||||
<item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="15"/>
|
||||
<item AVAILABLE="15" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="15"/>
|
||||
<item AVAILABLE="15" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
|
||||
<item AVAILABLE="15" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
|
||||
<item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="0"/>
|
||||
<item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="66"/>
|
||||
<item AVAILABLE="124" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>
|
||||
<item AVAILABLE="132" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>
|
||||
</section>
|
||||
<section stringID="XST_PARTITION_RESOURCE_SUMMARY">
|
||||
<section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
|
||||
|
||||
@@ -0,0 +1,509 @@
|
||||
<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<center><big><big><b>System Settings</b></big></big></center><br>
|
||||
<A NAME="Environment Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Environment Variable</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
<td><b>map</b></td>
|
||||
<td><b>par</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>LD_LIBRARY_PATH</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>LMC_HOME</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64</td>
|
||||
<td><font color=gray>< not set ></font></td>
|
||||
<td><font color=gray>< not set ></font></td>
|
||||
<td><font color=gray>< not set ></font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>PATH</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/ise/bin</td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE/</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE/</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE/</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_DSP</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_EDK</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/EDK</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/EDK</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/EDK</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>XILINX_PLANAHEAD</td>
|
||||
<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/PlanAhead</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/PlanAhead</font></td>
|
||||
<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/PlanAhead</font></td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Synthesis Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ifn</td>
|
||||
<td> </td>
|
||||
<td>TypeCheck.prj</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofn</td>
|
||||
<td> </td>
|
||||
<td>TypeCheck</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ofmt</td>
|
||||
<td> </td>
|
||||
<td>NGC</td>
|
||||
<td>NGC</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-p</td>
|
||||
<td> </td>
|
||||
<td>xa6slx4-3-csg225</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-top</td>
|
||||
<td> </td>
|
||||
<td>TypeCheck</td>
|
||||
<td> </td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_mode</td>
|
||||
<td>Optimization Goal</td>
|
||||
<td>Speed</td>
|
||||
<td>Speed</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-opt_level</td>
|
||||
<td>Optimization Effort</td>
|
||||
<td>1</td>
|
||||
<td>1</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-power</td>
|
||||
<td>Power Reduction</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iuc</td>
|
||||
<td>Use synthesis Constraints File</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-keep_hierarchy</td>
|
||||
<td>Keep Hierarchy</td>
|
||||
<td>No</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-netlist_hierarchy</td>
|
||||
<td>Netlist Hierarchy</td>
|
||||
<td>As_Optimized</td>
|
||||
<td>As_Optimized</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rtlview</td>
|
||||
<td>Generate RTL Schematic</td>
|
||||
<td>Yes</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-glob_opt</td>
|
||||
<td>Global Optimization Goal</td>
|
||||
<td>AllClockNets</td>
|
||||
<td>AllClockNets</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-read_cores</td>
|
||||
<td>Read Cores</td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-write_timing_constraints</td>
|
||||
<td>Write Timing Constraints</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-cross_clock_analysis</td>
|
||||
<td>Cross Clock Analysis</td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bus_delimiter</td>
|
||||
<td>Bus Delimiter</td>
|
||||
<td><></td>
|
||||
<td><></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-slice_utilization_ratio</td>
|
||||
<td>Slice Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bram_utilization_ratio</td>
|
||||
<td>BRAM Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-dsp_utilization_ratio</td>
|
||||
<td>DSP Utilization Ratio</td>
|
||||
<td>100</td>
|
||||
<td>100</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-reduce_control_sets</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_encoding</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-safe_implementation</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-fsm_style</td>
|
||||
<td> </td>
|
||||
<td>LUT</td>
|
||||
<td>LUT</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ram_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-ram_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_extract</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-shreg_extract</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-rom_style</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-auto_bram_packing</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-resource_sharing</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-async_to_sync</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_dsp48</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iobuf</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-max_fanout</td>
|
||||
<td> </td>
|
||||
<td>100000</td>
|
||||
<td>100000</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-bufg</td>
|
||||
<td> </td>
|
||||
<td>32</td>
|
||||
<td>16</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_duplication</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-register_balancing</td>
|
||||
<td> </td>
|
||||
<td>No</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-optimize_primitives</td>
|
||||
<td> </td>
|
||||
<td>NO</td>
|
||||
<td>No</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_clock_enable</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_set</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-use_sync_reset</td>
|
||||
<td> </td>
|
||||
<td>Yes</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-iob</td>
|
||||
<td> </td>
|
||||
<td>Auto</td>
|
||||
<td>Auto</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-equivalent_register_removal</td>
|
||||
<td> </td>
|
||||
<td>YES</td>
|
||||
<td>Yes</td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>-slice_utilization_ratio_maxmargin</td>
|
||||
<td> </td>
|
||||
<td>5</td>
|
||||
<td>0</td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Translation Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-intstyle</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>ise</font></td>
|
||||
<td><font color=gray>None</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-dd</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>_ngo</font></td>
|
||||
<td><font color=gray>None</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-p</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>xc3s50-pq208-5</font></td>
|
||||
<td><font color=gray>None</font></td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Map Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-ir</font></td>
|
||||
<td><font color=gray>Use RLOC Constraints</font></td>
|
||||
<td><font color=gray>OFF</font></td>
|
||||
<td><font color=gray>OFF</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-cm</font></td>
|
||||
<td><font color=gray>Optimization Strategy (Cover Mode)</font></td>
|
||||
<td><font color=gray>area</font></td>
|
||||
<td><font color=gray>area</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-intstyle</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>ise</font></td>
|
||||
<td><font color=gray>None</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-o</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>TypeCheck_map.ncd</font></td>
|
||||
<td><font color=gray>None</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-pr</font></td>
|
||||
<td><font color=gray>Pack I/O Registers/Latches into IOBs</font></td>
|
||||
<td><font color=gray>off</font></td>
|
||||
<td><font color=gray>off</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-p</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>xc3s50-pq208-5</font></td>
|
||||
<td><font color=gray>None</font></td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Place and Route Property Settings"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Switch Name</b></td>
|
||||
<td><b>Property Name</b></td>
|
||||
<td><b>Value</b></td>
|
||||
<td><b>Default Value</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-t</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>1</font></td>
|
||||
<td><font color=gray>1</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-intstyle</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>ise</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-ol</font></td>
|
||||
<td><font color=gray>Place & Route Effort Level (Overall)</font></td>
|
||||
<td><font color=gray>high</font></td>
|
||||
<td><font color=gray>std</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td><font color=gray>-w</font></td>
|
||||
<td><font color=gray> </font></td>
|
||||
<td><font color=gray>true</font></td>
|
||||
<td><font color=gray>false</font></td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
<A NAME="Operating System Information"></A>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
|
||||
</tr>
|
||||
<tr bgcolor='#ffff99'>
|
||||
<td><b>Operating System Information</b></td>
|
||||
<td><b>xst</b></td>
|
||||
<td><b>ngdbuild</b></td>
|
||||
<td><b>map</b></td>
|
||||
<td><b>par</b></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>CPU Architecture/Speed</td>
|
||||
<td>Intel(R) Core(TM) i7-5500U CPU @ 2.40GHz/2394.454 MHz</td>
|
||||
<td><font color=gray>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</font></td>
|
||||
<td><font color=gray>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</font></td>
|
||||
<td><font color=gray>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>Host</td>
|
||||
<td>localhost.localdomain</td>
|
||||
<td><font color=gray>Xilinx</font></td>
|
||||
<td><font color=gray>Xilinx</font></td>
|
||||
<td><font color=gray>Xilinx</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Name</td>
|
||||
<td>OracleServer</td>
|
||||
<td><font color=gray>CentOS</font></td>
|
||||
<td><font color=gray>CentOS</font></td>
|
||||
<td><font color=gray>CentOS</font></td>
|
||||
</tr>
|
||||
<tr>
|
||||
<td>OS Release</td>
|
||||
<td>Oracle Linux Server release 6.4</td>
|
||||
<td><font color=gray>CentOS release 6.10 (Final)</font></td>
|
||||
<td><font color=gray>CentOS release 6.10 (Final)</font></td>
|
||||
<td><font color=gray>CentOS release 6.10 (Final)</font></td>
|
||||
</tr>
|
||||
</TABLE>
|
||||
</BODY> </HTML>
|
||||
@@ -0,0 +1,102 @@
|
||||
<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
|
||||
<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
|
||||
<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
|
||||
<TD ALIGN=CENTER COLSPAN='4'><B>TypeCheck Project Status (08/17/2019 - 16:39:36)</B></TD></TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
|
||||
<TD>IEEE754Adder.xise</TD>
|
||||
<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
|
||||
<TD> No Errors </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
|
||||
<TD>TypeCheck</TD>
|
||||
<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
|
||||
<TD>Synthesized</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
|
||||
<TD>xa6slx4-3csg225</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
|
||||
<TD>
|
||||
No Errors</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
|
||||
<TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/*.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
|
||||
<TD>Balanced</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
|
||||
<TD>
|
||||
</TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
|
||||
<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
<TR ALIGN=LEFT>
|
||||
<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
|
||||
<TD>
|
||||
<A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck_envsettings.html'>
|
||||
System Settings</A>
|
||||
</TD>
|
||||
<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
|
||||
<TD> </TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
|
||||
<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
|
||||
<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
|
||||
<TD ALIGN=RIGHT>9</TD>
|
||||
<TD ALIGN=RIGHT>2400</TD>
|
||||
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
|
||||
<TD ALIGN=RIGHT>0</TD>
|
||||
<TD ALIGN=RIGHT>9</TD>
|
||||
<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
|
||||
</TR>
|
||||
<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
|
||||
<TD ALIGN=RIGHT>33</TD>
|
||||
<TD ALIGN=RIGHT>132</TD>
|
||||
<TD ALIGN=RIGHT COLSPAN='2'>25%</TD>
|
||||
</TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
|
||||
<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 17 16:39:35 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/xst.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>Sat Aug 17 16:35:26 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck_map.mrp'>Map Report</A></TD><TD>Out of Date</TD><TD>Sat Aug 17 16:35:26 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/map.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>Sat Aug 17 16:35:26 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Power Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>Sat Aug 17 16:35:26 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/trce.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
|
||||
<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD> </TD><TD> </TD><TD> </TD><TD> </TD><TD COLSPAN='2'> </TD></TR>
|
||||
</TABLE>
|
||||
<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
|
||||
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
|
||||
<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
|
||||
</TABLE>
|
||||
|
||||
|
||||
<br><center><b>Date Generated:</b> 08/17/2019 - 16:39:36</center>
|
||||
</BODY></HTML>
|
||||
@@ -8,7 +8,7 @@
|
||||
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->
|
||||
|
||||
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|
||||
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|
||||
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd" into library work</arg>
|
||||
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|
||||
|
||||
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|
||||
|
||||
+1
-1
@@ -5,7 +5,7 @@
|
||||
behavior or data corruption. It is strongly advised that
|
||||
users do not edit the contents of this file. -->
|
||||
<messages>
|
||||
<msg type="warning" file="Xst" num="647" delta="old" >Input <<arg fmt="%s" index="1">N<31></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
<msg type="warning" file="Xst" num="647" delta="new" >Input <<arg fmt="%s" index="1">N<31:31></arg>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
|
||||
</msg>
|
||||
|
||||
</messages>
|
||||
|
||||
@@ -0,0 +1,76 @@
|
||||
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|
||||
<!--This is an ISE project configuration file.-->
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||||
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||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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|
||||
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|
||||
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|
||||
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|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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||||
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||||
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||||
<report-views version="2.0" >
|
||||
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|
||||
<DateModified>2019-08-17T15:26:24</DateModified>
|
||||
<DateModified>2019-08-17T16:51:16</DateModified>
|
||||
<ModuleName>SpecialCasesCheck</ModuleName>
|
||||
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
|
||||
<SavedFilePath>/home/Luca/ISE/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport</SavedFilePath>
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||||
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||||
<SavedFilePath>/home/ise/gianni/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport</SavedFilePath>
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||||
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<?xml version='1.0' encoding='UTF-8'?>
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||||
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|
||||
<header>
|
||||
<DateModified>2019-08-17T16:37:54</DateModified>
|
||||
<ModuleName>TypeCheck</ModuleName>
|
||||
<SummaryTimeStamp>Unknown</SummaryTimeStamp>
|
||||
<SavedFilePath>/home/ise/gianni/IEEE754Adder/iseconfig/TypeCheck.xreport</SavedFilePath>
|
||||
<ImplementationReportsDirectory>/home/ise/gianni/IEEE754Adder</ImplementationReportsDirectory>
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||||
<DateInitialized>2019-08-17T16:37:53</DateInitialized>
|
||||
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||||
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||||
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||||
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|
||||
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|
||||
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|
||||
<toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary" />
|
||||
<toc-item title="Failing Constraints" target="Failing Constraints" />
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||||
<toc-item title="Detailed Reports" target="Detailed Reports" />
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||||
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<view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="TypeCheck_par.xrpt" label="Pinout Report" />
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<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="TypeCheck_html/tim/report.htm" label="CPLD Timing Report" />
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<view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
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||||
<view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="TypeCheck.log" label="System Log File" />
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|
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||||
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|
||||
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|
||||
<view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
|
||||
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|
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|
||||
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|
||||
<view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="TypeCheck.syr" label="Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
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||||
<toc-item title="Synthesis Options Summary" target=" Synthesis Options Summary " />
|
||||
<toc-item title="HDL Compilation" target=" HDL Compilation " />
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||||
<toc-item title="Design Hierarchy Analysis" target=" Design Hierarchy Analysis " />
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<toc-item title="HDL Analysis" target=" HDL Analysis " />
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<toc-item title="HDL Parsing" target=" HDL Parsing " />
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||||
<toc-item title="HDL Elaboration" target=" HDL Elaboration " />
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|
||||
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|
||||
<toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
|
||||
<toc-item title="Low Level Synthesis" target=" Low Level Synthesis " />
|
||||
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|
||||
<toc-item title="Final Report" target=" Final Report " />
|
||||
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|
||||
<toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
|
||||
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|
||||
<toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
|
||||
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|
||||
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|
||||
<toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
|
||||
<toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
|
||||
<toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
|
||||
<toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
|
||||
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|
||||
<view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="TypeCheck.srr" label="Synplify Report" />
|
||||
<view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="TypeCheck.prec_log" label="Precision Report" />
|
||||
<view inputState="Synthesized" program="ngdbuild" type="Report" file="TypeCheck.bld" label="Translation Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Command Line" target="Command Line:" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="TypeCheck_map.mrp" label="Map Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
|
||||
<toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
|
||||
<toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
|
||||
<toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
|
||||
<toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
|
||||
<toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
|
||||
<toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
|
||||
<toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
|
||||
<toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
|
||||
<toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
|
||||
<toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
|
||||
<toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
|
||||
<toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="TypeCheck.par" label="Place and Route Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Device Utilization" target="Device Utilization Summary:" />
|
||||
<toc-item title="Router Information" target="Starting Router" />
|
||||
<toc-item title="Partition Status" target="Partition Implementation Status" />
|
||||
<toc-item title="Clock Report" target="Generating Clock Report" />
|
||||
<toc-item title="Timing Results" target="Timing Score:" />
|
||||
<toc-item title="Final Summary" target="Peak Memory Usage:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="TypeCheck.twr" label="Post-PAR Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="TypeCheck.rpt" label="CPLD Fitter Report (Text)" >
|
||||
<toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
|
||||
<toc-item title="Resources Summary" target="** Mapped Resource Summary **" />
|
||||
<toc-item title="Pin Resources" target="** Pin Resources **" />
|
||||
<toc-item title="Global Resources" target="** Global Control Resources **" />
|
||||
</view>
|
||||
<view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="TypeCheck.tim" label="CPLD Timing Report (Text)" >
|
||||
<toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
|
||||
<toc-item title="Performance Summary" target="Performance Summary:" />
|
||||
</view>
|
||||
<view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="TypeCheck.pwr" label="Power Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Power summary" target="Power summary" />
|
||||
<toc-item title="Thermal summary" target="Thermal summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="TypeCheck.bgn" label="Bitgen Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
|
||||
<toc-item title="Final Summary" target="DRC detected" />
|
||||
</view>
|
||||
</viewgroup>
|
||||
<viewgroup label="Secondary Reports" >
|
||||
<view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
|
||||
<view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/TypeCheck_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/TypeCheck_translate.nlf" label="Post-Translate Simulation Model Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="TypeCheck_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
|
||||
<view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="TypeCheck_map.map" label="Map Log File" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
<toc-item title="Design Information" target="Design Information" />
|
||||
<toc-item title="Design Summary" target="Design Summary" />
|
||||
</view>
|
||||
<view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
|
||||
<view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck_preroute.twr" label="Post-Map Static Timing Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
<toc-item title="Timing Report Description" target="Device,package,speed:" />
|
||||
<toc-item title="Informational Messages" target="INFO:" />
|
||||
<toc-item title="Warning Messages" target="WARNING:" />
|
||||
<toc-item title="Timing Constraints" target="Timing constraint:" />
|
||||
<toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
|
||||
<toc-item title="Data Sheet Report" target="Data Sheet report:" />
|
||||
<toc-item title="Timing Summary" target="Timing summary:" />
|
||||
<toc-item title="Trace Settings" target="Trace Settings:" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/TypeCheck_map.nlf" label="Post-Map Simulation Model Report" />
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck_map.psr" label="Physical Synthesis Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="TypeCheck_pad.txt" label="Pad Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="TypeCheck.unroutes" label="Unroutes Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck_preroute.tsi" label="Post-Map Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.grf" label="Guide Results Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.dly" label="Asynchronous Delay Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.clk_rgn" label="Clock Region Report" />
|
||||
<view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.tsi" label="Post-Place and Route Constraints Interaction Report" >
|
||||
<toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="TypeCheck_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
|
||||
<view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/TypeCheck_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
|
||||
<view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="TypeCheck_sta.nlf" label="Primetime Netlist Report" >
|
||||
<toc-item title="Top of Report" target="Release" searchDir="Forward" />
|
||||
</view>
|
||||
<view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="TypeCheck.ibs" label="IBIS Model" >
|
||||
<toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
|
||||
<toc-item title="Component" target="Component " />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.lck" label="Back-annotate Pin Report" >
|
||||
<toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
|
||||
<toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
|
||||
</view>
|
||||
<view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.lpc" label="Locked Pin Constraints" >
|
||||
<toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
|
||||
<toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
|
||||
</view>
|
||||
<view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/TypeCheck_timesim.nlf" label="Post-Fit Simulation Model Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
|
||||
<view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
|
||||
</viewgroup>
|
||||
</body>
|
||||
</report-views>
|
||||
+22
-14
@@ -3,15 +3,16 @@
|
||||
<!--The data in this file is primarily intended for consumption by Xilinx tools.
|
||||
The structure and the elements are likely to change over the next few releases.
|
||||
This means code written to parse this file will need to be revisited each subsequent release.-->
|
||||
<application name="pn" timeStamp="Sat Aug 17 18:43:50 2019">
|
||||
<application name="pn" timeStamp="Sat Aug 17 17:19:19 2019">
|
||||
<section name="Project Information" visible="false">
|
||||
<property name="ProjectID" value="0" type="project"/>
|
||||
<property name="ProjectID" value="4B48FA10A560F77F46DA66FD7F346092" type="project"/>
|
||||
<property name="ProjectIteration" value="0" type="project"/>
|
||||
<property name="ProjectFile" value="/home/Luca/ISE/IEEE754Adder/IEEE754Adder.xise" type="project"/>
|
||||
<property name="ProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="project"/>
|
||||
<property name="ProjectFile" value="/home/ise/gianni/IEEE754Adder/IEEE754Adder.xise" type="project"/>
|
||||
<property name="ProjectCreationTimestamp" value="2019-08-17T16:51:15" type="project"/>
|
||||
</section>
|
||||
<section name="Project Statistics" visible="true">
|
||||
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
|
||||
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
|
||||
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
|
||||
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
|
||||
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
|
||||
@@ -21,19 +22,26 @@ This means code written to parse this file will need to be revisited each subseq
|
||||
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
|
||||
<property name="PROP_UseSmartGuide" value="false" type="design"/>
|
||||
<property name="PROP_UserBrowsedStrategyFiles" value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" type="process"/>
|
||||
<property name="PROP_intProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="design"/>
|
||||
<property name="PROP_intWbtProjectID" value="0" type="design"/>
|
||||
<property name="PROP_intWorkingDirLocWRTProjDir" value="UnableToCalculate" type="design"/>
|
||||
<property name="PROP_intWorkingDirUsed" value="Unknown" type="design"/>
|
||||
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
|
||||
<property name="PROP_intProjectCreationTimestamp" value="2019-08-17T16:51:15" type="design"/>
|
||||
<property name="PROP_intWbtProjectID" value="4B48FA10A560F77F46DA66FD7F346092" type="design"/>
|
||||
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
|
||||
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
|
||||
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
|
||||
<property name="PROP_xilxSynthAddBufg_spartan6" value="32" type="process"/>
|
||||
<property name="PROP_xstUseClockEnable_spartan6" value="Yes" type="process"/>
|
||||
<property name="PROP_xstUseSyncReset_spartan6" value="Yes" type="process"/>
|
||||
<property name="PROP_xstUseSyncSet_spartan6" value="Yes" type="process"/>
|
||||
<property name="PROPEXT_mapTimingMode_spartan6" value="Non Timing Driven" type="process"/>
|
||||
<property name="PROP_AutoTop" value="true" type="design"/>
|
||||
<property name="PROP_DevFamily" value="Spartan3" type="design"/>
|
||||
<property name="PROP_DevDevice" value="xc3s50" type="design"/>
|
||||
<property name="PROP_DevFamilyPMName" value="spartan3" type="design"/>
|
||||
<property name="PROP_DevPackage" value="pq208" type="design"/>
|
||||
<property name="PROP_DevFamily" value="Automotive Spartan6" type="design"/>
|
||||
<property name="PROP_DevDevice" value="xa6slx4" type="design"/>
|
||||
<property name="PROP_DevFamilyPMName" value="aspartan6" type="design"/>
|
||||
<property name="PROP_DevPackage" value="csg225" type="design"/>
|
||||
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
|
||||
<property name="PROP_DevSpeed" value="-5" type="design"/>
|
||||
<property name="PROP_DevSpeed" value="-3" type="design"/>
|
||||
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
|
||||
<property name="FILE_VHDL" value="2" type="source"/>
|
||||
<property name="FILE_VHDL" value="3" type="source"/>
|
||||
</section>
|
||||
</application>
|
||||
</document>
|
||||
Binary file not shown.
Binary file not shown.
Reference in new issue
Block a user