diff --git a/IEEE754Adder.gise b/IEEE754Adder.gise
index dce5a88..5a05a93 100644
--- a/IEEE754Adder.gise
+++ b/IEEE754Adder.gise
@@ -85,6 +85,7 @@
     </transform>
     <transform xil_pn:end_ts="1566052458" xil_pn:name="TRAN_copyInitialToXSTAbstractSynthesis" xil_pn:start_ts="1566052458">
       <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="ReadyToRun"/>
     </transform>
     <transform xil_pn:end_ts="1566059978" xil_pn:name="TRAN_schematicsToHdl" xil_pn:prop_ck="1167941000477774584" xil_pn:start_ts="1566059978">
       <status xil_pn:value="SuccessfullyRun"/>
@@ -110,8 +111,9 @@
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
     </transform>
-    <transform xil_pn:end_ts="1566060235" xil_pn:in_ck="-3235492353642026610" xil_pn:name="TRANEXT_xstsynthesize_spartan3" xil_pn:prop_ck="-5588158190480725594" xil_pn:start_ts="1566060230">
+    <transform xil_pn:end_ts="1566062385" xil_pn:in_ck="-3915287225243783751" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="4591378050783358917" xil_pn:start_ts="1566062357">
       <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="WarningsGenerated"/>
       <status xil_pn:value="ReadyToRun"/>
       <outfile xil_pn:name="SpecialCasesCheck.lso"/>
       <outfile xil_pn:name="SpecialCasesCheck.ngc"/>
@@ -120,23 +122,22 @@
       <outfile xil_pn:name="SpecialCasesCheck.stx"/>
       <outfile xil_pn:name="SpecialCasesCheck.syr"/>
       <outfile xil_pn:name="SpecialCasesCheck.xst"/>
+      <outfile xil_pn:name="SpecialCasesCheck_vhdl.prj"/>
       <outfile xil_pn:name="SpecialCasesCheck_xst.xrpt"/>
       <outfile xil_pn:name="TypeCheck.ngr"/>
       <outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
       <outfile xil_pn:name="webtalk_pn.xml"/>
       <outfile xil_pn:name="xst"/>
     </transform>
-    <transform xil_pn:end_ts="1566052811" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="-2497314214044977511" xil_pn:start_ts="1566052811">
+    <transform xil_pn:end_ts="1566062226" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="7014160488695491189" xil_pn:start_ts="1566062226">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForProperties"/>
     </transform>
     <transform xil_pn:end_ts="1566052856" xil_pn:in_ck="-1179315243053685338" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-7709254264864982892" xil_pn:start_ts="1566052852">
-      <status xil_pn:value="SuccessfullyRun"/>
+      <status xil_pn:value="AbortedRun"/>
       <status xil_pn:value="ReadyToRun"/>
       <status xil_pn:value="OutOfDateForInputs"/>
       <status xil_pn:value="OutOfDateForProperties"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
       <status xil_pn:value="InputAdded"/>
       <status xil_pn:value="InputChanged"/>
       <outfile xil_pn:name="TypeCheck.bld"/>
@@ -145,39 +146,9 @@
       <outfile xil_pn:name="_ngo"/>
       <outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
     </transform>
-    <transform xil_pn:end_ts="1566052859" xil_pn:in_ck="-1179315243053685337" xil_pn:name="TRANEXT_map_spartan3" xil_pn:prop_ck="-7868858794111860816" xil_pn:start_ts="1566052856">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-      <outfile xil_pn:name="TypeCheck.pcf"/>
-      <outfile xil_pn:name="TypeCheck_map.map"/>
-      <outfile xil_pn:name="TypeCheck_map.mrp"/>
-      <outfile xil_pn:name="TypeCheck_map.ncd"/>
-      <outfile xil_pn:name="TypeCheck_map.ngm"/>
-      <outfile xil_pn:name="TypeCheck_map.xrpt"/>
-      <outfile xil_pn:name="TypeCheck_summary.xml"/>
-      <outfile xil_pn:name="TypeCheck_usage.xml"/>
-      <outfile xil_pn:name="_xmsgs/map.xmsgs"/>
-    </transform>
-    <transform xil_pn:end_ts="1566052863" xil_pn:in_ck="2083081054299762752" xil_pn:name="TRANEXT_par_spartan3" xil_pn:prop_ck="3266239339701135281" xil_pn:start_ts="1566052859">
-      <status xil_pn:value="SuccessfullyRun"/>
-      <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
-      <outfile xil_pn:name="TypeCheck.ncd"/>
-      <outfile xil_pn:name="TypeCheck.pad"/>
-      <outfile xil_pn:name="TypeCheck.par"/>
-      <outfile xil_pn:name="TypeCheck.ptwx"/>
-      <outfile xil_pn:name="TypeCheck.unroutes"/>
-      <outfile xil_pn:name="TypeCheck.xpi"/>
-      <outfile xil_pn:name="TypeCheck_pad.csv"/>
-      <outfile xil_pn:name="TypeCheck_pad.txt"/>
-      <outfile xil_pn:name="TypeCheck_par.xrpt"/>
-      <outfile xil_pn:name="_xmsgs/par.xmsgs"/>
-    </transform>
     <transform xil_pn:end_ts="1566052863" xil_pn:in_ck="-1179315243053685469" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416187" xil_pn:start_ts="1566052862">
       <status xil_pn:value="SuccessfullyRun"/>
       <status xil_pn:value="ReadyToRun"/>
-      <status xil_pn:value="OutOfDateForPredecessor"/>
       <outfile xil_pn:name="TypeCheck.twr"/>
       <outfile xil_pn:name="TypeCheck.twx"/>
       <outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise
index e2972ab..c37b586 100644
--- a/IEEE754Adder.xise
+++ b/IEEE754Adder.xise
@@ -17,17 +17,21 @@
   <files>
     <file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="53"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
+    <file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="57"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
+    </file>
   </files>
 
   <properties>
-    <property xil_pn:name="AES Initial Vector virtex6" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="AES Key (Hex String) virtex6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Initial Vector spartan6" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="AES Key (Hex String) spartan6" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Add I/O Buffers" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow Logic Optimization Across Hierarchy" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Allow SelectMAP Pins to Persist" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -41,8 +45,6 @@
     <property xil_pn:name="Automatic BRAM Packing" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Insert glbl Module in the Netlist" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Automatically Run Generate Target PROM/ACE File" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Reads Per Page" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="BPI Sync Mode" xil_pn:value="Disable" xil_pn:valueState="default"/>
     <property xil_pn:name="BRAM Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Bring Out Global Set/Reset Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Bring Out Global Tristate Net as a Port" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -50,8 +52,8 @@
     <property xil_pn:name="CLB Pack Factor Percentage" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Case" xil_pn:value="Maintain" xil_pn:valueState="default"/>
     <property xil_pn:name="Case Implementation Style" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To" xil_pn:value="-3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Change Device Speed To Post Trace" xil_pn:value="-3" xil_pn:valueState="default"/>
     <property xil_pn:name="Combinatorial Logic Optimization" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile EDK Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Compile SIMPRIM (Timing) Simulation Library" xil_pn:value="true" xil_pn:valueState="default"/>
@@ -61,64 +63,65 @@
     <property xil_pn:name="Configuration Clk (Configuration Pins)" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin Done" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin HSWAPEN" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Pin Init" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin M0" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin M1" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin M2" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="Configuration Pin Program" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Configuration Rate virtex5" xil_pn:value="3" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Configuration Rate spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
     <property xil_pn:name="Correlate Output to Input Design" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create ASCII Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Binary Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Bit File" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Create I/O Pads from Ports" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Create IEEE 1532 Configuration File" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Create IEEE 1532 Configuration File spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Logic Allocation File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create Mask File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Create ReadBack Data Files" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Cross Clock Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Cycles for First BPI Page Read" xil_pn:value="1" xil_pn:valueState="default"/>
-    <property xil_pn:name="DCI Update Mode" xil_pn:value="As Required" xil_pn:valueState="default"/>
     <property xil_pn:name="DSP Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Decoder Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Delay Values To Be Read from SDF" xil_pn:value="Setup Time" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device" xil_pn:value="xc3s50" xil_pn:valueState="default"/>
-    <property xil_pn:name="Device Family" xil_pn:value="Spartan3" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-5" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device" xil_pn:value="xa6slx4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="default"/>
+    <property xil_pn:name="Device Speed Grade/Select ABS Minimum" xil_pn:value="-3" xil_pn:valueState="default"/>
     <property xil_pn:name="Disable Detailed Package Model Insertion" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Disable JTAG Connection" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Do Not Escape Signal and Instance Names in Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Done (Output Events)" xil_pn:value="Default (4)" xil_pn:valueState="default"/>
+    <property xil_pn:name="Drive Awake Pin During Suspend/Wake Sequence spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Drive Done Pin High" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable BitStream Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC)" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Cyclic Redundancy Checking (CRC) spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable External Master Clock" xil_pn:value="Disable" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Enable Multi-Threading par virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Multi-Threading par spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Enable Outputs (Output Events)" xil_pn:value="Default (5)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Bitstream virtex6" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Encrypt Key Select virtex6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Enable Suspend/Wake Global Set/Reset spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Encrypt Key Select spartan6" xil_pn:value="BBRAM" xil_pn:valueState="default"/>
+    <property xil_pn:name="Equivalent Register Removal Map" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Equivalent Register Removal XST" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Essential Bits" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Evaluation Development Board" xil_pn:value="None Specified" xil_pn:valueState="default"/>
     <property xil_pn:name="Exclude Compilation of Deprecated EDK Cores" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Exclude Compilation of EDK Sub-Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Cost Tables Map virtex6" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="Extra Effort" xil_pn:value="None" xil_pn:valueState="default"/>
+    <property xil_pn:name="Extra Cost Tables Map" xil_pn:value="0" xil_pn:valueState="default"/>
     <property xil_pn:name="Extra Effort (Highest PAR level only)" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="FPGA Start-Up Clock" xil_pn:value="CCLK" xil_pn:valueState="default"/>
     <property xil_pn:name="FSM Encoding Algorithm" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="FSM Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Fallback Reconfiguration virtex7" xil_pn:value="Disable" xil_pn:valueState="default"/>
     <property xil_pn:name="Filter Files From Compile Order" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Flatten Output Netlist" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language ArchWiz" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language Coregen" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Functional Model Target Language Schematic" xil_pn:value="VHDL" xil_pn:valueState="default"/>
+    <property xil_pn:name="GTS Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="GWE Cycle During Suspend/Wakeup Sequence spartan6" xil_pn:value="5" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Architecture Only (No Entity Declaration)" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Asynchronous Delay Report" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generate Clock Region Report" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -137,12 +140,10 @@
     <property xil_pn:name="Generate Timegroups Section Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Generics, Parameters" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Optimization Goal" xil_pn:value="AllClockNets" xil_pn:valueState="default"/>
-    <property xil_pn:name="Global Optimization map virtex5" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Global Optimization map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Set/Reset Port Name" xil_pn:value="GSR_PORT" xil_pn:valueState="default"/>
     <property xil_pn:name="Global Tristate Port Name" xil_pn:value="GTS_PORT" xil_pn:valueState="default"/>
-    <property xil_pn:name="HMAC Key (Hex String)" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Hierarchy Separator" xil_pn:value="/" xil_pn:valueState="default"/>
-    <property xil_pn:name="ICAP Select" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -160,7 +161,6 @@
     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-    <property xil_pn:name="JTAG to XADC Connection" xil_pn:value="Enable" xil_pn:valueState="default"/>
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
@@ -173,29 +173,35 @@
     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Map Effort Level" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
     <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
     <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile virtex7" xil_pn:value="Enable" xil_pn:valueState="default"/>
-    <property xil_pn:name="Multiplier Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
+    <property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
     <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
     <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="default"/>
+    <property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-    <property xil_pn:name="Optimization Effort virtex6" xil_pn:value="Normal" xil_pn:valueState="default"/>
+    <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
+    <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
@@ -216,13 +222,13 @@
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Package" xil_pn:value="pq208" xil_pn:valueState="default"/>
+    <property xil_pn:name="Package" xil_pn:value="csg225" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-    <property xil_pn:name="Place MultiBoot Settings into Bitstream virtex7" xil_pn:value="false" xil_pn:valueState="default"/>
+    <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
@@ -231,9 +237,8 @@
     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="SpecialCasesCheck_timesim.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SpecialCasesCheck_synthesis.vhd" xil_pn:valueState="default"/>
     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SpecialCasesCheck_translate.vhd" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Down Device if Over Safe Temperature" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Power Reduction Map virtex6" xil_pn:value="Off" xil_pn:valueState="default"/>
+    <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
@@ -249,10 +254,9 @@
     <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Duplication" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Register Ordering virtex6" xil_pn:value="4" xil_pn:valueState="default"/>
+    <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
@@ -266,10 +270,10 @@
     <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Reset DCM if SHUTDOWN &amp; AGHIGH performed" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
+    <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
     <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
     <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
@@ -278,7 +282,6 @@
     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="SPI 32-bit Addressing" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
@@ -286,9 +289,10 @@
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-    <property xil_pn:name="Set SPI Configuration Bus Width" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Shift Register Minimum Size virtex6" xil_pn:value="2" xil_pn:valueState="default"/>
+    <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
@@ -303,14 +307,13 @@
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Speed Grade" xil_pn:value="-5" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Address for Fallback Configuration virtex7" xil_pn:value="None" xil_pn:valueState="default"/>
-    <property xil_pn:name="Starting Placer Cost Table (1-100)" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
+    <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="default"/>
+    <property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
@@ -318,7 +321,7 @@
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -331,28 +334,25 @@
     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use DSP Block" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use SPI Falling Edge" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="default"/>
-    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="default"/>
+    <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-    <property xil_pn:name="User Access Register Value" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" xil_pn:valueState="non-default"/>
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex2" xil_pn:value="Auto" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for DCI Match (Output Events) virtex5" xil_pn:value="Auto" xil_pn:valueState="default"/>
+    <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
     <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-    <property xil_pn:name="Wait for PLL Lock (Output Events) virtex6" xil_pn:value="No Wait" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Mode 7-series" xil_pn:value="Off" xil_pn:valueState="default"/>
-    <property xil_pn:name="Watchdog Timer Value 7-series" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="default"/>
+    <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
+    <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
+    <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
     <!--                                                                                  -->
@@ -360,17 +360,17 @@
     <!--                                                                                  -->
     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan3" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="YYYY-MM-DDTHH:MM:SS" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="0" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="UnableToCalculate" xil_pn:valueState="default"/>
-    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="Unknown" xil_pn:valueState="default"/>
+    <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-08-17T16:51:15" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="4B48FA10A560F77F46DA66FD7F346092" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
   </properties>
 
   <bindings/>
diff --git a/NaNCheck.vhd b/NaNCheck.vhd
new file mode 100644
index 0000000..1ba7ed4
--- /dev/null
+++ b/NaNCheck.vhd
@@ -0,0 +1,38 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity NaNCheck is
+	port(
+		X, Y: in std_logic_vector(31 downto 0);
+		isNan: out std_logic
+	);
+end NaNCheck;
+
+architecture NaNCheckArch of NaNCheck is
+	component TypeCheck is
+		port(
+			N: in std_logic_vector(31 downto 0);
+			NaN, INF: out std_logic
+		);
+	end component;
+	
+	signal xNan: std_logic;
+	signal xInf: std_logic;
+	signal xSign: std_logic;
+	signal yNan: std_logic;
+	signal yInf: std_logic;
+	signal ySign: std_logic;
+	
+begin
+	xCheck: TypeCheck
+		port map (N => X, NaN => xNan, INF => xInf);
+	yCheck: TypeCheck
+		port map (N => Y, NaN => yNan, INF => yInf);
+
+	xSign <= X(31);
+	ySign <= Y(31);
+	
+	isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign);
+	
+end NaNCheckArch;
+
diff --git a/SpecialCasesCheck.cmd_log b/SpecialCasesCheck.cmd_log
index 1168b5f..727d9bb 100644
--- a/SpecialCasesCheck.cmd_log
+++ b/SpecialCasesCheck.cmd_log
@@ -5,3 +5,6 @@ xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn
 xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" 
 xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" 
 xst -intstyle ise -ifn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr" 
+xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr" 
+xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr" 
+xst -intstyle ise -ifn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.xst" -ofn "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr" 
diff --git a/SpecialCasesCheck.ngc b/SpecialCasesCheck.ngc
index 129b4db..35a11a9 100644
--- a/SpecialCasesCheck.ngc
+++ b/SpecialCasesCheck.ngc
@@ -1,3 +1,3 @@
 XILINX-XDB 0.1 STUB 0.1 ASCII
 XILINX-XDM V1.6e
-$bfx55=4:3CE\XZ5X=12>58682996D@_UU8Z867=87>0:=>?2::30>>78920NX]PIODL=>EHEDC_XHJ8;BPFEQCC92O?7HONA39EA1=ANOO:7J=4GOF2?L4<A980E<<4I308M62<AK_M56GAIUQWEQC03EELENOC4:NVP72<D\^886BZT508J74<F=80B;94NDVTKWM63F>0CO[Ic:R-657499;8SA:4P@PWe>VNFVH^_DJWb:RJJZDR[GKFI;5\OTP@A47<[yohelbLargpGmcdc=1_U]Kl;TQFVZPN[@HGI45YIDU\P\VB<2R7<3;4X=33:0=_48;596V313<6?]:6;7?0T1?;>49[8439=2R7=;0:;Y>23;3<P5;3285W<0;=0>^;97?0T1<?>49[8779=2R7>?0:;Y>17;3<P58?285W<37=1>^;:?4>7U2=7?78\94?6<1S0?714:Z?6;3<P59;2:5W<2394;3<P59:295W<2<7?]:36=1S080;;Y>5:1=_4>4?7U27>59[8<86l2RB@D@W-YFA$5(6(Z^^N->!1!CPGLO13QY_@DL8;YQW[BHC02RT<RGMUG;8\Z77W@H^J45W_03\MGSA12RT=?QFBTD:?]Y6;VCIYK74X^37[LDRN01SS<;PICWE=>^X9?UBNXH6;Y]23ZOE]O30TR?7_H@VB<=_W83TEO[I8:Z\5ZOE]O30TR<?_H@VB<=_W;;TEO[I9:Z\67YNJ\L27UQ=3^KAQC?<PV8?SDLZF89[[73XAK_M56VP27]JFP@>3QU9;RGMUG;8\Z4?W@H^J45W_3;\MGSA02RT>RGMUG;8\Z57W@H^J45W_23\MGSA02RT?RGMUG:8\Z2XAK_M46VP5^KAQC><PV<TEO[I8:Z\3ZOE]O20TR6PICWE<>^X1VCIYK84Xe`\Ma773QnfS@oeosTfvvohf8:0TicPMhllvScu{`ee?6V|t59Z85823P6:<3;4Y=32:0=^488596W312<6?\:6<7?0U1?:>49Z8409=2S7=:0:;X>2<;3<Q5;2295V<0<6?\:587?0U1<>>49Z8749=2S7>>0:;X>10;3<Q58>285V<34=1>_;:>4>7T2=8?78]94>6=1R0?0:;X>04;1<Q59:6=0:;X>05;2<Q59586W34?68]939<2S7:3:4Y=5=0>_;07>0U1718:[\4ZOE]O30UR??_H@VB<=^W8;TEO[I9:[\57YNJ\L27TQ>3^KAQC?<QV;?SDLZF89Z[43XAK_M56WP17]JFP@>3PU:;RGMUG;8]Z7?W@H^J45V_0;\MGSA02ST=RGMUG;8]Z47W@H^J45V_33\MGSA12ST>?QFBTD:?\Y5;VCIYK74Y^07[LDRN01RS?;PICWE=>_X:?UBNXH6;X]13ZOE]O30UR<7_H@VB<=^W;3TEO[I8:[\6ZOE]O30UR=?_H@VB<=^W:;TEO[I8:[\7ZOE]O20UR:PICWE<>_X=VCIYK64Y^4\MGSA02ST;RGMUG:8]Z>XAK_M46WP9^KAQC3<azDjb55fsOcm556?3`yEmc??599jwKgi98<37d}Aao315==n{Gke=>?7;hqMek708j1bCoa162\WR6?3`yEmc?7399jwKgi91237d}Aao03=f=n{Gke>=7PSV24?luIig8=n6g|N`l12ZUP8>1bCoa3448mvHff==0e~@nn524?luIig>:;6g|N`l552=n{Gke4884irLbj<1<azDjb4>n;hqMekYHJ\L=7d}Uesma?lu]m{eTCO[Ie:z`7v37%<'{}?>79:{@l`el'N>27tMgebi,C<{GHy8ho6NOx369B?4=9rY<6;h51g827171>8094?>>{o4g>4=i>l0=7)8l:5;8yV0=>o0:j7?<40455?4?:990h?:50;395~U02?l1=k4>353524<50;::7{Z=3;295?7=1hqX;78i:0d95626>?;1>5<?1:&13?723-8;6no4b3694?252<k15luG279'60<5<2P>6?u?:08~kg7=831do54?::k75?6=,;818=5a2083?>o4n3:1(?<5419m64<632c8h7>5$30905=i:80976g<c;29 74=<91e><4<;:k0f?6=,;818=5a2087?>o4i3:1(?<5419m64<232c857>5$30905=i:80=76g<8;29 74=<91e><48;:k03?6=,;818=5a208;?>o4>3:1(?<5419m64<>32c897>5$30905=i:80j76g<4;29 74=<91e><4m;:k06?6=,;818=5a208`?>o493:1(?<5419m64<c32c8<7>5$30905=i:80n76g=f;29 74=<91e><4i;:k1a?6=,;818=5a20824>=n:m0;6)<=:528j77=9810e?m50;&16?273g8:6<<4;h0a>5<#:;0?<6`=1;30?>o5i3:1(?<5419m64<6<21b>44?:%01>16<f;;1=854i5:94?"5:3>;7c<>:048?l20290/>?4;0:l15?7032c?:7>5$30905=i:80:465f4483>!452=:0b??51898m12=83.9>7:?;o02>4g<3`>86=4+23874>h593;i76g;2;29 74=<91e><4>c:9j7`<72-8969>4n3395a=<a:91<7*=2;63?k4628o07d<7:18'67<382d9=7?i;:k;=?6=,;81455a2083?>o??3:1(?<5899m64<632c397>5$309<==i:80976g74;29 74=011e><4<;:k;7?6=,;81455a2087?>o?:3:1(?<5899m64<232c3=7>5$309<==i:80=76g70;29 74=011e><48;:k4b?6=,;81455a208;?>o0m3:1(?<5899m64<>32c<h7>5$309<==i:80j76g8c;29 74=011e><4m;:k4e?6=,;81455a208`?>o013:1(?<5899m64<c32c<47>5$309<==i:80n76g87;29 74=011e><4i;:k42?6=,;81455a20824>=n?<0;6)<=:9:8j77=9810e::50;&16?>?3g8:6<<4;h50>5<#:;0346`=1;30?>o0:3:1(?<5899m64<6<21b;<4?:%01>=><f;;1=854i8294?"5:3237c<>:048?l>a290/>?478:l15?7032c3i7>5$309<==i:80:465f8e83>!452120b??51898m=e=83.9>767;o02>4g<3`2i6=4+238;<>h593;i76g7a;29 74=011e><4>c:9j<3<72-896564n3395a=<a>h1<7*=2;:;?k4628o07d9?:18'67<?02d9=7?i;:`7f?6=93:1<v*=5;f8L1g<@;<0cn4?::agg<72<0;6=u+2482<>N3i2B9:6*>4;68mc<722c:<7>5;h32>5<<a881<75`1e83>>{ekj0;684?:1y'60<602B?m6F=6:&20?2<ao0;66g>0;29?l762900e<<50;9l5a<722wio=4?:483>5}#:<0:46F;a:J12>"6<3h0ek4?::k24?6=3`;:6=44i0094?=h9m0;66smc483>0<729q/>84>8:J7e>N5>2.:87l4ig83>>o683:17d?>:188m44=831d=i4?::afc<72<0;6=u+2482<>N3i2B9:6*>4;`8mc<722c:<7>5;h32>5<<a881<75`1e83>>{ek80;684?:1y'60<602B?m6F=6:&20?d<ao0;66g>0;29?l762900e<<50;9l5a<722wio?4?:283>5}#:<0::6F;a:J12>"6<320ek4?::k24?6=3f;o6=44}ca0>5<2290;w)<::0:8L1g<@;<0(<:5b:ke>5<<a8:1<75f1083>>o6:3:17b?k:188yge3290>6=4?{%06>4><@=k0D?84$069f>oa2900e<>50;9j54<722c:>7>5;n3g>5<<uki=6=4::183!422820D9o4H348 42=j2cm6=44i0294?=n980;66g>2;29?j7c2900qol=:187>5<7s-8>6<94H5c8L70<,8>1m6gi:188m46=831b=<4?::m2`?6=3thi?7>55;294~"5=3;37E:n;I05?!732k1bj7>5;h33>5<<a8;1<75f1383>>i6l3:17plm4;291?6=8r.997?7;I6b?M413-;?6o5ff;29?l772900e<?50;9j57<722e:h7>5;|`a1?6==3:1<v*=5;3;?M2f3A8=7)?;:c9jb?6=3`;;6=44i0394?=n9;0;66a>d;29?xde>3:197>50z&11?7?3A>j7E<9;%37>g=nn3:17d??:188m47=831b=?4?::m2`?6=3thi57>55;294~"5=3;37E:n;I05?!732=1bj7>5;h33>5<<a8;1<75f1383>>i6l3:17plma;291?6=8r.997?7;I6b?M413-;?695ff;29?l772900e<?50;9j57<722e:h7>5;|`50?6=:3:1<v*=5;30?M2f3A8=7dk50;9l5a<722wi:>4?:383>5}#:<0:?6F;a:J12>ob2900c<j50;9~f37=8381<7>t$37956=O<h1C>;5fe;29?j7c2900qo8?:181>5<7s-8>6<=4H5c8L70<al0;66a>d;29?xd2n3:1>7>50z&11?743A>j7E<9;hg94?=h9m0;66sm5d83>7<729q/>84>3:J7e>N5>2cn6=44o0f94?=zj<n1<7<50;2x 73=9:1C8l5G279ja?6=3f;o6=44}c7`>5<5290;w)<::018L1g<@;<0eh4?::m2`?6=3th>n7>52;294~"5=3;87E:n;I05?lc=831d=i4?::a1d<72;0;6=u+24827>N3i2B9:6gj:188k4b=831vn8750;094?6|,;?1=>5G4`9K63=nm3:17b?k:188yg3?29096=4?{%06>45<@=k0D?84id83>>i6l3:17pl:6;296?6=8r.997?<;I6b?M413`o1<75`1e83>>{e=<0;6?4?:1y'60<6;2B?m6F=6:kf>5<<g8n1<75rb4694?4=83:p(?;5129K0d=O:?1bi7>5;n3g>5<<uk?86=4=:183!422890D9o4H348m`<722e:h7>5;|`66?6=:3:1<v*=5;30?M2f3A8=7dk50;9l5a<722wi9<4?:383>5}#:<0:?6F;a:J12>ob2900c<j50;9~f06=8381<7>t$37956=O<h1C>;5fe;29?j7c2900qo:i:181>5<7s-8>6<=4H5c8L70<al0;66a>d;29?xd3m3:1>7>50z&11?743A>j7E<9;hg94?=h9m0;66sm4e83>7<729q/>84>3:J7e>N5>2cn6=44o0f94?=zj?h1<7<50;2x 73=9:1C8l5G279ja?6=3f;o6=44}c4b>5<5290;w)<::018L1g<@;<0eh4?::m2`?6=3th=57>52;294~"5=3;87E:n;I05?lc=831d=i4?::a2=<72;0;6=u+24827>N3i2B9:6gj:188k4b=831vn;950;094?6|,;?1=>5G4`9K63=nm3:17b?k:188yg0129096=4?{%06>45<@=k0D?84id83>>i6l3:17pl95;296?6=8r.997?<;I6b?M413`o1<75`1e83>>{e>;0;6?4?:1y'60<6;2B?m6F=6:kf>5<<g8n1<75rb4594?4=83:p(?;5129K0d=O:?1bi7>5;n3g>5<<uk>h6=4=:183!422890D9o4H348m`<722e:h7>5;|`b=?6=:3:1<v*=5;30?M2f3A8=7dk50;9l5a<722wim54?:383>5}#:<0:?6F;a:J12>ob2900c<j50;9~fd0=8381<7>t$37956=O<h1C>;5fe;29?j7c2900qoo::181>5<7s-8>6<=4H5c8L70<al0;66a>d;29?xdf<3:1>7>50z&11?743A>j7E<9;hg94?=h9m0;66sma283>7<729q/>84>3:J7e>N5>2cn6=44o0f94?=zjh81<7<50;2x 73=9:1C8l5G279ja?6=3f;o6=44}cc2>5<5290;w)<::018L1g<@;<0eh4?::m2`?6=3thj<7>52;294~"5=3;87E:n;I05?lc=831d=i4?::a=c<72;0;6=u+24827>N3i2B9:6gj:188k4b=831vn4k50;094?6|,;?1=>5G4`9K63=nm3:17b?k:188yg?c29096=4?{%06>45<@=k0D?84id83>>i6l3:17pl6b;296?6=8r.997?<;I6b?M413`o1<75`1e83>>{e1h0;6?4?:1y'60<6;2B?m6F=6:kf>5<<g8n1<75rb8;94?4=83:p(?;5129K0d=O:?1bi7>5;n3g>5<<uk336=4=:183!422890D9o4H348m`<722e:h7>5;|`:3?6=:3:1<v*=5;30?M2f3A8=7dk50;9l5a<722wi5;4?:383>5}#:<0:?6F;a:J12>ob2900c<j50;9~f<3=8381<7>t$37956=O<h1C>;5fe;29?j7c2900qo7;:181>5<7s-8>6<=4H5c8L70<al0;66a>d;29?xd>;3:1>7>50z&11?743A>j7E<9;hg94?=h9m0;66sm9383>7<729q/>84>3:J7e>N5>2cn6=44o0f94?=zjk:1<7<50;2x 73=9:1C8l5G279ja?6=3f;o6=44}cce>5<5290;w)<::018L1g<@;<0eh4?::m2`?6=3thji7>52;294~"5=3;87E:n;I05?lc=831d=i4?::aea<72;0;6=u+24827>N3i2B9:6gj:188k4b=831vnlm50;094?6|,;?1=>5G4`9K63=nm3:17b?k:188ygge29096=4?{%06>45<@=k0D?84id83>>i6l3:17plna;296?6=8r.997?<;I6b?M413`o1<75`1e83>>{ei>0;6?4?:1y'60<6;2B?m6F=6:kf>5<<g8n1<75rb8a94?4=83:p(?;5129K0d=O:?1bi7>5;n3g>5<<uk3:6=4=:183!422890D9o4H348m`<722e:h7>5;|``3?6=:3:1<v*=5;3f?M2f3A8=7dk50;9l5a<722wio44?:383>5}#:<0:i6F;a:J12>ob2900c<j50;9~fgc=83?1<7>t$3795==O<h1C>;5+158a?l`=831b==4?::k25?6=3`;96=44o0f94?=zjkn1<7;50;2x 73=911C8l5G279'51<e3`l1<75f1183>>o693:17d?=:188k4b=831vno650;794?6|,;?1=55G4`9K63=#9=097dh50;9j55<722c:=7>5;h31>5<<g8n1<75rbc594?3=83:p(?;5199K0d=O:?1/=94m;hd94?=n990;66g>1;29?l752900c<j50;9~fge=83>1<7>t$37952=O<h1C>;5+1580?l`=831b==4?::k25?6=3f;o6=44}c`a>5<2290;w)<::0:8L1g<@;<0(<:59:ke>5<<a8:1<75f1083>>o6:3:17b?k:188yv7>2909w0lj:0f89gb=9;1v<o50;0x9g>=9m16n:4>2:p5g<72;q6nn4>d:?af?`<uz836=4={_0;?82d2l1v?750;0xZ7?<5=n1i6s|2`83>7}Y:h168h4j;|q1f?6=:rT9n63;f;g8yv4d2909wS<l;<73>`=z{;n1<7<t^3f8907=m2wx>h4?:3y]6`=:=;0n7p}=f;296~X5n27>?7k4}r13>5<5sW9;70;;:d9~w67=838pR>?4=479a>{t;;0;6?uQ339>13<b3ty8?7>52z\07>;2?3o0q~=;:181[5334?36h5rs2794?4|V:?01875e:p73<72;qU?;525`8f?xu4?3:1>vP<7:?6f?c<uz936=4={_1;?83d2l1v>750;0xZ6?<5<n1i6s|3`83>7}Y;h169h4j;|q0f?6=:rT8n63:f;g8yv5d2909wS=l;<43>`=z{:n1<7<t^2f8937=m2wx?h4?:3y]7`=:>;0n7p}<f;296~X4n27=?7k4}r62>5<5sW>:708;:d9~w14=838pR9<4=779a>{t<:0;6?uQ429>23<b3ty?87>52z\70>;1?3o0q~:::181[2234<36h5rs5494?4|V=<01;75e:p02<72;qU8:526`8f?xu303:1>vP;8:?5f?c<uz>h6=4={<`1>47<5=i1=i5rs5f94?4|5k81==524e82`>{t<l0;6?u2b2826>;3m3;o7p};f;296~;d>3;;70:i:0f8yv372909w0m9:g9>15<6l2wx9<4?:3y>g1<6:27>=7?k;|q66?6=:r7h87?>;<71>4b<uz?86=4={<a7>46<5<91=i5rs4694?4|5j>1j63:4;3g?xu2=3:1>v3m2;d8903=9m1v8850;0x9g3=98169;4>d:p12<72;q6o;4>1:?63?7c3ty>47>52z?a1?7734?36<j4}r7:>5<5s4h>6k525882`>{t=h0;6?u2b5826>;2i3;o7p}:b;296~;ei3;970;m:0f8yv3d2909w0ln:03890e=9m1v8j50;0x9gg=99169i4>d:p1`<72;q6nl4i;<7f>4b<uz?m6=4={<`:>44<5<l1=i5rs7294?4|5k31=<526182`>{t>80;6?u2b8824>;193;o7p}92;296~;e<3;:708=:0f8yv042909w0l6:g9>26<6l2wx:94?:3y>21<6l27i47h4}r46>5<5s4h?6<>4=7795a=z{?<1<7<t=c69b>;1>3;o7p}97;296~;d>3;97088:0f8yv0?2909w0l<:03893>=9m1v;750;0x9g5=9916:44>d:p2d<72;q6n>4i;<4b>4b<uz<i6=4={<`6>44<5?h1=i5rs6294?4|V>:014?5e:p34<72;qU;<52938f?xu0:3:1>vP82:?:7?c<uz=86=4={_50?8?32l1v::50;0xZ22<50?1i6s|7483>7}Y?<165;4j;|q42?6=:rT<:6367;g8yv102909wS98;<;;>`=z{>21<7<t^6:89<?=m2wx;44?:3y]3<=:1h0n7p}8a;296~X0i272n7k4}r5a>5<5sW=i707l:d9~w2e=838pR:m4=8f9a>{t?m0;6?uQ7e9>=`<b3ty<i7>52z\4a>;>n3o0q~9i:181[1a34k;6h5rs9294?4|V1:01l?5e:p<4<72;qU4<52a38f?xu?:3:1>vP72:?b7?c<uz286=4={_:0?8g32l1v5:50;0xZ=2<5h?1i6s|8483>7}Y0<16m;4j;|q;2?6=:rT3:63n7;g8yv>02909wS68;<c;>`=z{131<7<t^9;89d?=m2wx4l4?:3y]<d=:ih0n7p}7b;296~X?j27jn7k4}r:`>5<5sW2h70ol:d9~w=b=838pR5j4=`f9a>{t0l0;6?uQ8d9>e`<b3ty3j7>52z\;b>;fn3o0q~7?:181[?734h;6h5rs8394?4|5j;1==529082`>{t1;0;6?u2c08e?8?528n0q~7<:1818da288014=51e9~w<2=838p14:51e9>fa<a3ty297>52z?:1?7c34ho6<>4}r;5>5<5s43=6<j4=cf954=z{0=1<7<t=8595a=:jl0m7p}68;296~;>03;o70lj:028yv?>2909w0m>:0089<?=9m1v4o50;0x9f7=98165l4>d:p=g<72;q6o84>1:?:f?7c3ty2o7>52z?:g?7c34hn6<?4}r;g>5<5s4i>6<>4=8f95a=z{0o1<7<t=b79b>;>m3;o7p}6f;296~;d83;9707i:0f8yvg72909w0ml:g9>e5<6l2wxm<4?:3y>gf<6827j=7?k;|qb6?6=:r7ho7?>;<c1>4b<uzk86=4={<a`>44<5h91=i5rs`694?4|5jh1j63n4;3g?xuf=3:1>v3lb;33?8g228n0q~o9:1818ee28;01l851e9~wd1=838p1n>5109>e2<6l2wxm54?:3y>gg<6:27j47?k;|qb=?6=:r7j57?k;<`;>46<uzkj6=4={<a3>46<5hk1=i5rs``94?4|5j:1j63nb;3g?xufk3:1>v3nc;3g?8db2880q~ok:1818da28;01lj51e9~wdc=838p1oh5119>e`<6l2wxmk4?:3y>fc<a34km6<j4}r`3>5<5s4i>6<<4=c295a=z{k;1<7<t^c389f1=9m1vo<50;0x9g4=9m16n;4i;|qa7?6=:r7i?7?k;<`5>46<uzh?6=4={<`7>4b<5k<1=<5rsc794?4|5k?1=i52b7826>{tj?0;6?u2b782`>;e?3l0q~l8:1818d028n01ol5119~wg?=838p1o751e9>fg<692wxnl4?:3y>fd<6l27in7?=;|qa`?6=:r7h?7?>;<`g>4b<uzhm6=4={<`e>4b<5j81j6s|c183>7}:k90:h63l3;d8yve62909w0m>:0f89f4=991vn<50;0x9f4=9m16o>4>2:pg6<72;q6o>4>d:?ag?`<uzi?6=4={<a7>4b<5k=1==5rsb794?4|5j?1=i52c2824>{tk?0;6?u2c782`>;e?3;:7p}l7;296~;d?3o01ol51e9~wf>=838pRn64=b;95a=z{j31<7<t=5`9g>;d13o0q~mm:1808ee28n01o65109>ff<682wxon4?:2y>gf<6l27i47?=;<``>47<utd:554?:0yK63=zf8326=4>{I05?xh61h0;6<uG279~j4?e290:wE<9;|l2=f<728qC>;5rn0;g>5<6sA8=7p`>9d83>4}O:?1vb<7i:182M413td:m=4?:0yK63=zf8k:6=4>{I05?xh6i;0;6<uG279~j4g4290:wE<9;|l2e1<728qC>;5rn0c6>5<6sA8=7p`>a783>4}O:?1vb<o8:182M413td:m54?:0yK63=zf8k26=4>{I05?xh6ih0;6<uG279~j4ge290:wE<9;|l2ef<728qC>;5rn0cg>5<6sA8=7p`>ad83>4}O:?1vb<oi:182M413td:n=4?:0yK63=zf8h:6=4>{I05?xh6j;0;6<uG279~j4d4290:wE<9;|l2f1<728qC>;5rn0`6>5<6sA8=7p`>b783>4}O:?1vb<l8:182M413td:n54?:0yK63=zf8h26=4>{I05?xh6jh0;6<uG279~j4de290:wE<9;|l2ff<728qC>;5rn0`g>5<6sA8=7p`>bd83>4}O:?1vb<li:182M413td:o=4?:0yK63=zf8i:6=4>{I05?xh6k;0;6<uG279~j4e4290:wE<9;|l2g1<728qC>;5rn0a6>5<6sA8=7p`>c783>4}O:?1vb<m8:182M413td:o54?:0yK63=zf8i26=4>{I05?xh6kh0;6<uG279~j4ee290:wE<9;|l2gf<728qC>;5rn0ag>5<6sA8=7p`>cd83>4}O:?1vb<mi:182M413td:h=4?:0yK63=zf8n:6=4>{I05?xh6l;0;6<uG279~j4b4290:wE<9;|l2`1<728qC>;5rn0f6>5<6sA8=7p`>d783>4}O:?1vb<j8:182M413td:h54?:0yK63=zf8n26=4>{I05?xh6lh0;6<uG279~j4be290:wE<9;|l2`f<728qC>;5rn0fg>5<6sA8=7p`>dd83>4}O:?1vb<ji:182M413td:i=4?:0yK63=zf8o:6=4>{I05?xh6m;0;6<uG279~j4c4290:wE<9;|l2a1<728qC>;5rn0g6>5<6sA8=7p`>e783>4}O:?1vb<k8:182M413td:i54?:0yK63=zf8o26=4>{I05?xh6mh0;6<uG279~j4ce290:wE<9;|l2af<728qC>;5rn0gg>5<6sA8=7p`>ed83>4}O:?1vb<ki:182M413td:j=4?:0yK63=zf8l:6=4>{I05?xh6n;0;6<uG279~j4`4290:wE<9;|l2b1<728qC>;5rn0d6>5<6sA8=7p`>f783>4}O:?1vb<h8:182M413td:j54?:0yK63=zf8l26=4>{I05?xh6nh0;6<uG279~j4`e290:wE<9;|l2bf<728qC>;5rn0dg>5<6sA8=7p`>fd83>4}O:?1vb<hi:182M413td9<=4?:0yK63=zf;::6=4>{I05?xh58;0;6<uG279~j764290:wE<9;|l141<728qC>;5rn326>5<6sA8=7p`=0783>4}O:?1vb?>8:182M413td9<54?:0yK63=zf;:26=4>{I05?xh58h0;6<uG279~j76e290:wE<9;|l14f<728qC>;5rn32g>5<6sA8=7p`=0d83>4}O:?1vb?>i:182M413td9==4?:0yK63=zf;;:6=4>{I05?xh59;0;6<uG279~j774290:wE<9;|l151<728qC>;5rn336>5<6sA8=7p`=1783>4}O:?1vb??8:182M413td9=54?:0yK63=zf;;26=4>{I05?xh59h0;6<uG279~j77e290:wE<9;|l15f<728qC>;5rn33g>5<6sA8=7p`=1d83>4}O:?1vb??i:182M413td9>=4?:0yK63=zf;8:6=4>{I05?xh5:;0;6<uG279~j744290:wE<9;|l161<728qC>;5rn306>5<6sA8=7p`=2783>4}O:?1vb?<8:182M413td9>54?:0yK63=zf;826=4>{I05?xh5:h0;6<uG279~j74e290:wE<9;|l16f<728qC>;5rn30g>5<6sA8=7p`=2d83>4}O:?1vb?<i:182M413td9?=4?:0yK63=zf;9:6=4>{I05?x{zuIJHw?ml:b2;27>4;tJKNv>r@ARxyEF
\ No newline at end of file
+$d0x5>4682996D@_UU8[867=87;;7><5IORVP?_;;80;2?570028<56789:;<=>?0123<>DR[VCEJB:4CMI32>EKC82;:6MCK3531>EKC;R37NBD2Y3;40=DDB3;96MCK@34?FJLI8N9;6MCK@3G02=DDBK:H5;4CMIA50=DDBI:96MCKE36?FJLL_i0OAEKV^FJRLBB=2IGGKV7;BNHB]7?801HC@CFTUGG3>EUMH^NH<>4EDGFGFEDIHKJ<56?4:DEB@><NOLMJKHJ119EBC@ANOLMJKHIFGG2?B5<OGN:7D<4I108M44<A;80E><4I508M02<AK_M56GAIUQWEQC13EEHGHJ8;MMDMFGK<2F^X>:4LTV70>JR\<>0@XZ92:L1<>HD'`yEmc74NB-jwKgi9h1EO"g|N`l24d=IK&cxBl`>1`9MG*otFhd:>l5AC.kpJdh6;01EO"g|N`l1=>HD'`yEmc=6;OA,mvHff=30BN!fsOcm1<=IK&cxBl`99:L@+luIig=27CM irLbj=?<FJ%bCoa90;8JF)~Kaohg"IPcnosqqc)OV~f|<m4NB-zGmcdc&MTobcuug-CZrjx5:5>=5AC.{@l`el'NUhc`~ztd,D[qkw494T_Z>8;OGWSJTL02DjBNfjcj38K1=HJ\Lh7] =0043=45XD=1[M_Zn;QKM[GSTAMRi7]GA_CWPJDKB>2ZXHB@J109PLWC@WLR_^LM[_OE@a>UOZLMTAD@PSHXF2>UH][IN:6][AUWP54=TxlibmaMnsdq@l`el<2^R\H74TxrfGmcdcj1^_H\PVHQJFIC>3_CN[RZVPD68\969=2R7==0:;Y>25;3<P5;9285W<01=1>^;9=4>7U2>5?78\9716<1S0<915:Z?5=823Q6:53:4X=3=1>^;:94>7U2=1?78\9456<1S0?=15:Z?61823Q6993;4X=05:0=_4;=596V329<6?]:517>0T1<15:Z?75803Q68=7>15:Z?74833Q68295W<5<7?]:26=1S0;0;;Y>4:1=_414?7U26>0f8\LJNFQ'SHO.?.0"PPPD'8';+M^MFI79[WQJNJ>1S_YQHNE:8\Z6XAK_M56VP11]JFP@>3QU:=RGMUG;8\Z75W@H^J45W_01\MGSA12RT=9QFBTD:?]Y6=VCIYK74X^35[LDRN01SS<9PICWE=>^X91UBNXH6;Y]2=ZOE]O20TR?PICWE=>^X:9UBNXH6;Y]15ZOE]O30TR<=_H@VB<=_W;9TEO[I9:Z\61YNJ\L27UQ=5^KAQC?<PV8=SDLZF89[[71XAK_M56VP29]JFP@>3QU95RGMUG:8\Z4XAK_M56VP31]JFP@>3QU8=RGMUG:8\Z5XAK_M46VP4^KAQC><PV?TEO[I8:Z\2ZOE]O20TR9PICWE<>^X0VCIYK64X^;\MGSA>2RonRGk119[`hYJiceyZh||inl24>^ceVGbbb|Yesqjkk5<Pz~?7T2?>49Z8469=2S7=<0:;X>26;3<Q5;8285V<06=1>_;9<4>7T2>6?78]9706<1R0<615:[?5<833P6:285V<32=1>_;:84>7T2=2?78]9446<1R0?:15:[?60823P69:3;4Y=04:0=^4;2596W328<7?\:56<1R0>>17:[?74<76<1R0>?14:[?7;2<Q5>586W35?68]909<2S7;3:4Y=:=0>_;1790UH]7;X]3[LDRN01RS<>PICWE=>_X98UBNXH6;X]26ZOE]O30UR?<_H@VB<=^W8>TEO[I9:[\50YNJ\L27TQ>6^KAQC?<QV;<SDLZF89Z[4>XAK_M56WP18]JFP@?3PU:SDLZF89Z[76XAK_M56WP20]JFP@>3PU9>RGMUG;8]Z44W@H^J45V_36\MGSA12ST>8QFBTD:?\Y5>VCIYK74Y^04[LDRN01RS?6PICWE=>_X:0UBNXH7;X]1[LDRN01RS>>PICWE=>_X;8UBNXH7;X]0[LDRN11RS9QFBTD;?\Y2W@H^J55V_7]JFP@?3PU<SDLZF99Z[=YNJ\L37TQ6_H@VB6=cld?0e~@nn`9jwKgiWFH^J;5fs[gqkg=n{SoycRAMUG33?}g1{er?!>#lsf011xFGx;k97MNw4e8E>7<6sZ;3647545827171>8095ko;{o;4>4=i110=7)79:618yV702031894>353524<51ok37i:k:182>4}T910257:;:01753062;3mm95yT5`94?7=9339w^?7:8;901<6;=;=:<4=9gc7?!362;30(9;5e09a0a<72=819?462zJ64>"3m3>o7W;52z396?{#<h0;7):6:c`8m3d=83.?;78n;o65>5=<a?31<7*;7;4b?k212810e;950;&73?0f3g>=6?54i7494?"3?3<j7c:9:298m33=83.?;78n;o65>1=<a?>1<7*;7;4b?k212<10e;=50;&73?0f3g>=6;54i7094?"3?3<j7c:9:698m37=83.?;78n;o65>==<a?:1<7*;7;4b?k212010e8h50;&73?0f3g>=6l54i4g94?"3?3<j7c:9:c98m0e=83.?;78n;o65>f=<a<h1<7*;7;4b?k212m10e8o50;&73?0f3g>=6h54i4;94?"3?3<j7c:9:g98m0>=83.?;78n;o65>46<3`?<6=4+4685e>h3>3;:76g:6;29 11=>h1e8;4>2:9j10<72-><6;o4n54956=<a<>1<7*;7;4b?k2128>07d;<:18'02<1i2d?:7?:;:k46?6=,==1:l5a47822>=n?80;6):8:7c8j10=9>10e:>50;&73?0f3g>=6<64;h4e>5<#<>0=m6`;6;3:?>o1m3:1(9956`9m03<6i21b:i4?:%64>3g<f=<1=o54i7a94?"3?3<j7c:9:0a8?l0?290/8:49a:l72?7c32c>h7>5$5592d=i<?0:i65f5383>!202?k0b9851g98mg5=83.?;7l=;o65>5=<ak;1<7*;7;`1?k212810elh50;&73?d53g>=6?54i`g94?"3?3h97c:9:298mdb=83.?;7l=;o65>1=<ahi1<7*;7;`1?k212<10ell50;&73?d53g>=6;54i`c94?"3?3h97c:9:698md?=83.?;7l=;o65>==<ah21<7*;7;`1?k212010el950;&73?d53g>=6l54i`494?"3?3h97c:9:c98md2=83.?;7l=;o65>f=<ah91<7*;7;`1?k212m10el<50;&73?d53g>=6h54i`394?"3?3h97c:9:g98md6=83.?;7l=;o65>46<3`3m6=4+468a6>h3>3;:76g6e;29 11=j;1e8;4>2:9j=a<72-><6o<4n54956=<a0i1<7*;7;`1?k2128>07d7m:18'02<e:2d?:7?:;:kae?6=,==1n?5a47822>=nj00;6):8:c08j10=9>10eo650;&73?d53g>=6<64;h`4>5<#<>0i>6`;6;3:?>oe>3:1(995b39m03<6i21bn84?:%64>g4<f=<1=o54ic694?"3?3h97c:9:0a8?ld7290/8:4m2:l72?7c32cj97>5$559f7=i<?0:i65f9`83>!202k80b9851g98kab=831dhk4?::`41?6=93:1<v*;e;3f?M133A?;7b?k:188yg5a290?6=4?{%6f>7g<@>>0D8>4$3597>o583:17d<>:188m74=831d8?4?::a7`<72>0;6=u+4d81`>N0<2B><6*=7;68m76=831b><4?::k16?6=3`886=44i3694?=n:<0;66a;2;29?xd483:1;7>50z&7a?4c3A=?7E;?;%04>1=n:90;66g=1;29?l452900e?=50;9j61<722c997>5;n61>5<<uk9>6=4;:183!2b2;k0D::4H428 71=;2c9<7>5;h02>5<<a;81<75`4383>>{e;?0;6:4?:1y'0`<5l2B<86F:0:&13?7d3`8;6=44i3394?=n:;0;66g=3;29?l432900e?;50;9l07<722wi?:4?:783>5}#<l09o6F84:J64>"5?3;i7d<?:188m77=831b>?4?::k17?6=3`8?6=44o5094?=zj:21<7;50;2x 1c=:k1C;95G519'62<6i2c9<7>5;h02>5<<a;81<75f2283>>i3:3:17pl<9;293?6=8r.?i7<k;I57?M373-8<6<m4i3294?=n:80;66g=2;29?l442900e?:50;9j60<722e?>7>5;|`0e?6=?3:1<v*;e;0g?M133A?;7)<8:0a8m76=831b><4?::k16?6=3`886=44i3694?=n:<0;66a;2;29?xd4j3:1;7>50z&7a?4c3A=?7E;?;%04>4e<a;:1<75f2083>>o5:3:17d<<:188m72=831b>84?::m76?6=3th8o7>56;294~"3m38h7E9;;I73?!4028h0e?>50;9j64<722c9>7>5;h00>5<<a;>1<75`4383>>{e;80;684?:1y'0`<5j2B<86F:0:&13?7f3`8;6=44i3394?=n:;0;66g=3;29?j252900qo==:184>5<7s->n6?j4H668L06<,;=1=n5f2183>>o593:17d<=:188m75=831b>94?::k11?6=3f>96=44}c10>5<0290;w):j:3f8L22<@<:0(?951b9j65<722c9=7>5;h01>5<<a;91<75f2583>>o5=3:17b:=:188yg53290<6=4?{%6f>7b<@>>0D8>4$3595<=n:90;66g=1;29?l452900e?=50;9j61<722c997>5;n61>5<<uk2n6=4=:183!2b2;<0D::4H428m4`=831d8?4?::a<a<72;0;6=u+4d812>N0<2B><6g>f;29?j252900qo6m:181>5<7s->n6?84H668L06<a8l1<75`4383>>{e0h0;6?4?:1y'0`<5>2B<86F:0:k2b?6=3f>96=44}c::>5<5290;w):j:348L22<@<:0e<h50;9l07<722wi454?:383>5}#<l09:6F84:J64>o6n3:17b:=:188yg>029096=4?{%6f>70<@>>0D8>4i0d94?=h<;0;66sm8783>7<729q/8h4=6:J40>N282c:j7>5;n61>5<<uk2>6=4=:183!2b2;<0D::4H428m4`=831d8?4?::a<1<72;0;6=u+4d812>N0<2B><6g>f;29?j252900qo6<:181>5<7s->n6?84H668L06<a8l1<75`4383>>{e0;0;6?4?:1y'0`<5>2B<86F:0:k2b?6=3f>96=44}c:3>5<5290;w):j:348L22<@<:0e<h50;9l07<722wi;k4?:383>5}#<l09:6F84:J64>o6n3:17b:=:188yg1b29096=4?{%6f>70<@>>0D8>4i0d94?=h<;0;66sm7e83>7<729q/8h4=6:J40>N282c:j7>5;n61>5<<uk=h6=4=:183!2b2;<0D::4H428m4`=831d8?4?::a3g<72;0;6=u+4d812>N0<2B><6g>f;29?j252900qo9n:181>5<7s->n6?84H668L06<a8l1<75`4383>>{e?00;6?4?:1y'0`<5>2B<86F:0:k2b?6=3f>96=44}c5;>5<5290;w):j:348L22<@<:0e<h50;9l07<722wi;:4?:383>5}#<l09:6F84:J64>o6n3:17b:=:188yg?229096=4?{%6f>70<@>>0D8>4i0d94?=h<;0;66sm9583>7<729q/8h4=6:J40>N282c:j7>5;n61>5<<uk386=4=:183!2b2;<0D::4H428m4`=831d8?4?::a=7<72;0;6=u+4d812>N0<2B><6g>f;29?j252900qo7>:181>5<7s->n6?84H668L06<a8l1<75`4383>>{e190;6?4?:1y'0`<5>2B<86F:0:k2b?6=3f>96=44}c:e>5<5290;w):j:348L22<@<:0e<h50;9l07<722wi4n4?:383>5}#<l09:6F84:J64>o6n3:17b:=:188yg>629096=4?{%6f>70<@>>0D8>4i0d94?=h<;0;66sm7783>7<729q/8h4=6:J40>N282c:j7>5;n61>5<<ukn?6=4=:183!2b2;<0D::4H428m4`=831d8?4?::a`6<72;0;6=u+4d812>N0<2B><6g>f;29?j252900qoj>:181>5<7s->n6?84H668L06<a8l1<75`4383>>{el90;6?4?:1y'0`<5>2B<86F:0:k2b?6=3f>96=44}cae>5<5290;w):j:348L22<@<:0e<h50;9l07<722wioh4?:383>5}#<l09:6F84:J64>o6n3:17b:=:188ygec29096=4?{%6f>70<@>>0D8>4i0d94?=h<;0;66smcb83>7<729q/8h4=6:J40>N282c:j7>5;n61>5<<ukii6=4=:183!2b2;<0D::4H428m4`=831d8?4?::agd<72;0;6=u+4d812>N0<2B><6g>f;29?j252900qom6:181>5<7s->n6?84H668L06<a8l1<75`4383>>{ek10;6?4?:1y'0`<5>2B<86F:0:k2b?6=3f>96=44}ca5>5<5290;w):j:348L22<@<:0e<h50;9l07<722wio84?:383>5}#<l09:6F84:J64>o6n3:17b:=:188yge329096=4?{%6f>70<@>>0D8>4i0d94?=h<;0;66smc283>7<729q/8h4=6:J40>N282c:j7>5;n61>5<<uki96=4=:183!2b2;<0D::4H428m4`=831d8?4?::ag4<72;0;6=u+4d812>N0<2B><6g>f;29?j252900qom?:181>5<7s->n6?84H668L06<a8l1<75`4383>>{ejo0;6?4?:1y'0`<5>2B<86F:0:k2b?6=3f>96=44}c`f>5<5290;w):j:348L22<@<:0e<h50;9l07<722wini4?:383>5}#<l09:6F84:J64>o6n3:17b:=:188ygbe29096=4?{%6f>70<@>>0D8>4i0d94?=h<;0;66smd`83>7<729q/8h4=6:J40>N282c:j7>5;n61>5<<ukn26=4=:183!2b2;<0D::4H428m4`=831d8?4?::a`=<72;0;6=u+4d812>N0<2B><6g>f;29?j252900qoj8:181>5<7s->n6?84H668L06<a8l1<75`4383>>{el?0;6?4?:1y'0`<5>2B<86F:0:k2b?6=3f>96=44}cf6>5<5290;w):j:348L22<@<:0e<h50;9l07<722wih?4?:383>5}#<l09:6F84:J64>o6n3:17b:=:188yge029096=4?{%6f>70<@>>0D8>4i0d94?=h<;0;66smbb83>7<729q/8h4=6:J40>N282c:j7>5;n61>5<<uknn6=4=:183!2b2=90D::4H428m4`=831d8?4?::aa5<72;0;6=u+4d877>N0<2B><6g>f;29?j252900q~6j:1818532;8015k5439~w=b=838p1>;5209><a<3:2wx4o4?:3y>70<58273n7:=;|q;e?6=:r78<7<>;<:b>14<uz226=4={<13>76<51318?5rs9:94?4|5::1>>5289876>{t0>0;6?u231816>;??3>97p}76;296~;4838>7069:508yv>22909w0=?:3689=3=<;1v5:50;0x96?=:<16494;2:p<6<72;q6?44=4:?;7?253ty3>7>52z?02?46342969<4}r:3>5<5s49=6?=4=92907=z{>l1<7<t=24967=:?o0?>6s|7d83>7}:;?099638e;61?xu0l3:1>v3<6;07?81c2=80q~9l:18185f2;>01:m5439~w2d=838p1>o5229>3g<3:2wx;l4?:3y>72<5927<m7:=;|q4=?6=:r78;7<?;<5:>14<uz=36=4={<14>72<5>218?5rs6594?4|5:=1>>5276876>{t1<0;6?u239815>;>=3>97p}64;296~;4038;707;:508yv?42909w0=7:3189<5=<;1v4<50;0x96>=:;165?4;2:p=4<72;q6?44=1:?:5?253ty2<7>52z?0=?47343;69<4}r:e>5<5s4926?=4=9d907=z{1i1<7<t=2;967=:0j0?>6s|8083>7}:;?09<6371;61?xu0>3:1>v3<7;01?8112=80q~j;:1818532;901i:5439~wa5=838p1>k5219>`6<3:2wxh<4?:3y>7`<5927o=7:=;|qg4?6=:r78i7<=;<f3>14<uzim6=4={<1f>75<5jl18?5rsbg94?4|5:o1>952cd876>{tkm0;6?u23g814>;dl3>97p}lc;296~;4n38:70ml:508yvee2909w0=i:3089fd=<;1vno50;0x964=:<16ol4;2:pg<<72;q6??4=4:?`=?253tyh47>52z?0f?4634i369<4}ra5>5<5s49i6?=4=b4907=z{j?1<7<t=2`967=:k<0?>6s|c583>7}:;k09963l4;61?xud;3:1>v3<b;07?8e42=80q~m=:1818542;>01n<5439~wf7=838p1>=5229>g4<3:2wxo=4?:3y>7f<5927h<7:=;|qab?6=:r78o7<?;<`e>14<uzhn6=4={<1`>72<5ko18?5rscf94?4|5:i1>>52be876>{tlk0;6?u230815>;cj3>97p}ka;296~;4938;70jn:508yvb>2909w0=>:3189a?=<;1vi650;0x967=:;16h54;2:p`2<72;q6??4=1:?g3?253tyo:7>52z?06?4734n=69<4}rf6>5<5s4996?=4=e7907=z{m81<7<t=20967=:l;0?>6s|c683>7}:;k09<63l7;61?xuek3:1>v3<c;01?8dd2=80q~jj:1818532=801ik51g9~w`6=838p1:;51e9>a5<6n2wx?i4?:3y>7`<3:27887<?;|q1a?6=:r78j7:=;<1f>73<uz8m6=4={<13>14<5:?1>?5rs2294?4|5:?18?5235815>{t;<0;6?u237876>;4i3897p}<6;296~;4?3>970=n:378yv502909w0=7:50896g=:91v>650;0x96?=<;16?l4=1:p7<<72;q6?l4;2:?00?423ty8m7>52z?0f?2534986?<4}r1a>5<5s49h69<4=21960=z{:i1<7<t=23907=:;:09<6s|3083>7}:;;0?>63<3;02?xu4:3:1>v3<3;61?8532;>0q~8m:181[0e342n6<h4}r4:>5<5sW<2706k:0d8yv002909wS88;<:a>4`<uz<=6=4={_45?8>f28l0q~8::181[0234226<h4}r47>5<5sW<?7067:0d8yv042909wS8<;<:4>4`<uz<96=4={_41?8>128l0q~8>:181[06342>6<h4}r43>5<5sW<;706;:0d8yv3a2909wS;i;<:0>4`<uz?n6=4={_7f?8>528l0q~;l:181[3d342;6<h4}r7a>5<5sW?i709i:0d8yv3f2909wS;n;<5f>4`<uz?26=4={_7:?81c28l0q~;7:181[3?34=h6<h4}r74>5<5sW?<709m:0d8yv312909wS;9;<5b>4`<uz?>6=4={_76?81>28l0q~;;:181[3334=36<h4}r70>5<5sW?87098:0d8yv152909wS9=;<;6>4`<uz=:6=4={_52?8?328l0q~9?:181[1734386<h4}r4e>5<5sW<m707=:0d8yv0b2909wS8j;<;2>4`<uz<o6=4={_4g?8?728l0q~8l:181[0d342m6<h4}r4;>5<5sW<3706l:0d8yv3c2909wS;k;<:2>4`<uz?96=4={_71?81128l0q~l<:181[d434n?6<h4}r`2>5<5sWh:70j<:0d8yvga2909wSoi;<f2>4`<uzkn6=4={_cf?8b728l0q~ok:181[gc34im6<h4}rc`>5<5sWkh70mj:0d8yvge2909wSom;<ag>4`<uzkj6=4={_cb?8ed28l0q~o6:181[g>34ii6<h4}rc;>5<5sWk370mn:0d8yvg02909wSo8;<a:>4`<uzk=6=4={_c5?8e?28l0q~o;:181[g334i=6<h4}rc0>5<5sWk870m::0d8yvg52909wSo=;<a7>4`<uzk:6=4={_c2?8e428l0q~o?:181[g734i96<h4}r;e>5<5sW3m70m>:0d8yv?b2909wS7j;<a3>4`<uz3o6=4={_;g?8da28l0q~7l:181[?d34hn6<h4}r;a>5<5sW3i70lk:0d8yvdf2909wSln;<fa>4`<uzh26=4={_`:?8bf28l0q~l7:181[d?34n26<h4}r`4>5<5sWh<70j7:0d8yvd12909wSl9;<f4>4`<uzh>6=4={_`6?8b128l0q~l;:181[d334n>6<h4}r`3>5<5sWh;70j=:0d8yvg22909wSo:;<a4>4`<uz3j6=4={_;b?8dd28l0q~jk:181[bc34nn69<4}rfe>5<5sWnm70k?:508yxh6?l0;6<uG519~j41a290:wE;?;|l2<5<728qC9=5rn0:2>5<6sA?;7p`>8383>4}O=91vb<6<:182M373td:494?:0yK15=zf82>6=4>{I73?xh60?0;6<uG519~j4>0290:wE;?;|l2<=<728qC9=5rn0::>5<6sA?;7p`>8`83>4}O=91vb<6m:182M373td:4n4?:0yK15=zf82o6=4>{I73?xh60l0;6<uG519~j4>a290:wE;?;|l2=5<728qC9=5rn0;2>5<6sA?;7p`>9383>4}O=91vb<7<:182M373td:594?:0yK15=zf83>6=4>{I73?xh61?0;6<uG519~j4?0290:wE;?;|l2==<728qC9=5rn0;:>5<6sA?;7p`>9`83>4}O=91vb<7m:182M373td:5n4?:0yK15=zf83o6=4>{I73?xh61l0;6<uG519~j4?a290:wE;?;|l2e5<728qC9=5rn0c2>5<6sA?;7p`>a383>4}O=91vb<o<:182M373td:m94?:0yK15=zf8k>6=4>{I73?xh6i?0;6<uG519~j4g0290:wE;?;|l2e=<728qC9=5rn0c:>5<6sA?;7p`>a`83>4}O=91vb<om:182M373td:mn4?:0yK15=zf8ko6=4>{I73?xh6il0;6<uG519~j4ga290:wE;?;|l2f5<728qC9=5rn0`2>5<6sA?;7p`>b383>4}O=91vb<l<:182M373td:n94?:0yK15=zf8h>6=4>{I73?xh6j?0;6<uG519~j4d0290:wE;?;|l2f=<728qC9=5rn0`:>5<6sA?;7p`>b`83>4}O=91vb<lm:182M373td:nn4?:0yK15=zf8ho6=4>{I73?xh6jl0;6<uG519~j4da290:wE;?;|l2g5<728qC9=5rn0a2>5<6sA?;7p`>c383>4}O=91vb<m<:182M373td:o94?:0yK15=zf8i>6=4>{I73?xh6k?0;6<uG519~j4e0290:wE;?;|l2g=<728qC9=5rn0a:>5<6sA?;7p`>c`83>4}O=91vb<mm:182M373td:on4?:0yK15=zf8io6=4>{I73?xh6kl0;6<uG519~j4ea290:wE;?;|l2`5<728qC9=5rn0f2>5<6sA?;7p`>d383>4}O=91vb<j<:182M373td:h94?:0yK15=zf8n>6=4>{I73?xh6l?0;6<uG519~j4b0290:wE;?;|l2`=<728qC9=5rn0f:>5<6sA?;7p`>d`83>4}O=91vb<jm:182M373td:hn4?:0yK15=zf8no6=4>{I73?xh6ll0;6<uG519~j4ba290:wE;?;|l2a5<728qC9=5rn0g2>5<6sA?;7p`>e383>4}O=91vb<k<:182M373td:i94?:0yK15=zf8o>6=4>{I73?xh6m?0;6<uG519~j4c0290:wE;?;|l2a=<728qC9=5rn0g:>5<6sA?;7p`>e`83>4}O=91vb<km:182M373td:in4?:0yK15=zf8oo6=4>{I73?xh6ml0;6<uG519~j4ca290:wE;?;|l2b5<728qC9=5rn0d2>5<6sA?;7p`>f383>4}O=91vb<h<:182M373td:j94?:0yK15=zf8l>6=4>{I73?xh6n?0;6<uG519~j4`0290:wE;?;|l2b=<728qC9=5rn0d:>5<6sA?;7p`>f`83>4}O=91vb<hm:182M373td:jn4?:0yK15=zf8lo6=4>{I73?xh6nl0;6<uG519~j4`a290:wE;?;|l145<728qC9=5rn322>5<6sA?;7p`=0383>4}O=91vb?><:182M373td9<94?:0yK15=zf;:>6=4>{I73?xh58?0;6<uG519~j760290:wE;?;|l14=<728qC9=5rn32:>5<6sA?;7p`=0`83>4}O=91vb?>m:182M373td9<n4?:0yK15=zf;:o6=4>{I73?xh58l0;6<uG519~j76a290:wE;?;|~yEFDs;k96>h:6d1;gxFGJr:vLM^t}AB
\ No newline at end of file
diff --git a/SpecialCasesCheck.ngr b/SpecialCasesCheck.ngr
index 8e3b39e..c97eb0e 100644
--- a/SpecialCasesCheck.ngr
+++ b/SpecialCasesCheck.ngr
@@ -1,3 +1,3 @@
 XILINX-XDB 0.1 STUB 0.1 ASCII
 XILINX-XDM V1.6e
-$ccx74=(`fgn#A{la.KPA*OBML=>8Ljkes-Pt`enieIjh}Lhdah*snc9918>7GAPTV9J956294:<6==:HLSQQ<_4:;1<3??;209MKVR\3S7?<4?>`906?H;;80;2l5<2;Z?74<76h18>7W33083:g=4{<:{}?>7-468EKB5>2KEH?L>6:CM@1D6<2KEH564BTQ\MK@H12IDA@G[TDF4?FTBI]OO=6I<;FLG<>AXadzTK<<4I108M44<A;80E><4I508M04<A?80E:=4IOD`?LHAW`g{SD@I1d9HA@VX@@OYM_MGY69OKBODIE>0B1>15:L?55823G6:=3;4N=31:0=I489596@315<6?K:6=7?0B1?9>49M8419=2D7=50:;O>2=;2<F5;596@321<6?K:597?0B1<=>49M8759=2D7>90:;O>11;3<F58=285A<35=1>H;:14>7C2=9?68J949=2D7?=08;O>05?69=2D7?<0;;O>0:1=I4=4?7C2:>59M83833G6<295A<9<7?K:>6:1EmCm4N`L\mhvXFhD:=6A<;NP17>IU;:1D^9=4OS:`?U(5889:<<=PL59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ3:PWHg=TANH^_RGAFNc8WLAXJ\YBHUl4SHE\FPUIIDO:=6]ebkbhFgtmzIcine>;U68P\VB02^Te`~PT0a8PZrjxVey<=>?d:V\phvXg{:;<=?k;U]wiuYhz9:;<?j4T^vntZiu89:;?<>4T^vntZiu89:;Sdcc:V\phvXg{:;<<j4T^vntZiu89::=i5[_uos[jt789;9h6ZPtlr\kw67889:<6ZPtlr\kw6788Uba}74TxrfGmcdc01]EHYPTXRF0>^;87?0T1??>49[8479=2R7=?0:;Y>27;3<P5;?285W<07=1>^;9?4>7U2>7?78\97?6<1S0<714:Z?5;3<P58;285W<33=1>^;:;4>7U2=3?78\9436<1S0?;15:Z?63823Q69;3;4X=0;:0=_4;3586V32?78\9576>1S0>?50?78\9566=1S0>0;;Y>7:1=_4<4?7U29>59[82833Q63295W<8<2`>^ND@DS!UJM 1,2$VRRJ):%=-O\CHK5?]USD@H<7U][_FLG5`=_[]UBA]BJMDLWEQOHFVIDB^Z]AHLWW46<PZ^T^YBPPSMSAWR^>2RonRGk119[`hYJiceyZh||inl24>^ceVGbbb|Yesqjkk5<Pz~27U}{GLmgai2<Q5:596W311<6?\:697?0U1?=>49Z8459=2S7=90:;X>21;3<Q5;=285V<05=1>_;914>7T2>9?68]979=2S7>=0:;X>15;3<Q589285V<31=1>_;:=4>7T2=5?78]9416<1R0?915:[?6=823P6953:4Y=0=1>_;;94<7T2<1;2=1>_;;84?7T2<>59Z81833P6>295V<7<7?\:06=1R050;;X>::0=n{Gkeh6g|N`l\ekb789:9<6g|N`l\ekb789:Te`~PirLbjZgil9:;<<j4irLbjZgil9:;=?>4irLbjZgil9:;=Rgbp^kpJdhXign;<=?>119jwKgiW`g{Sd}Aao35?lu]m{em7~azrbg\bljbfhgnh6}`usaf[ioimgh=7uMgebi7?}Oin=1sBl`j;ya0w06*=$zz>=69;xAkafm33pCej95vN`l~DEv5:;1KLu67:G81>4}Tm32<69851262237=:18;=v`75;38j=0=>2.3879i;|Qg>=1=<?0:?9?96081<7643m>n6=4>:0yPa?>02=<1=>:>67396=4792|M8l4?:082>5}Tm32<69851262237=:18;=6*:d;3g?!202>1i8h4?:5092?2?sE296<u+468a2>{K0:0:w)l>:19~ 06=<l1Qo7<t2;19y_2e2;q>6;4ro`c94?=hj90;66g87;29 1?=??1e854?;:k41?6=,=31;;5a4982?>o0;3:1(975779m0=<532c<>7>5$5;933=i<10876g81;29 1?=??1e854;;:k44?6=,=31;;5a4986?>o1n3:1(975779m0=<132c=i7>5$5;933=i<10<76g9d;29 1?=??1e8547;:k5g?6=,=31;;5a498:?>o1j3:1(975779m0=<f32c=m7>5$5;933=i<10i76g98;29 1?=??1e854l;:k53?6=,=31;;5a498g?>o1>3:1(975779m0=<b32c=97>5$5;933=i<10m76g94;29 1?=??1e854>0:9j26<72->26:84n5:954=<a?81<7*;9;55?k2?28807d8>:18'0<<0>2d?47?<;:k54?6=,=31;;5a49820>=n=o0;6):6:648j1>=9<10e:k50;&7=?113g>36<84;h5g>5<#<00<:6`;8;34?>o0k3:1(975779m0=<6021b;o4?:%6:>20<f=21=454i6c94?"313==7c:7:0c8?l1>290/84486:l7<?7e32c<47>5$5;933=i<10:o65f7583>!2>2><0b9651e98m3?=83.?5799;o6;>4c<3`?n6=4+48842>h303;m76gn2;29 1?=i81e854?;:kb4?6=,=31m<5a4982?>o>m3:1(975a09m0=<532c2h7>5$5;9e4=i<10876g6c;29 1?=i81e854;;:k:f?6=,=31m<5a4986?>o>i3:1(975a09m0=<132c257>5$5;9e4=i<10<76g68;29 1?=i81e8547;:k:3?6=,=31m<5a498:?>o>>3:1(975a09m0=<f32c297>5$5;9e4=i<10i76g63;29 1?=i81e854l;:k:6?6=,=31m<5a498g?>o>93:1(975a09m0=<b32c2<7>5$5;9e4=i<10m76g7f;29 1?=i81e854>0:9j<`<72->26l?4n5:954=<a1n1<7*;9;c2?k2?28807d6l:18'0<<f92d?47?<;:k;f?6=,=31m<5a49820>=n0h0;6):6:`38j1>=9<10el750;&7=?g63g>36<84;hc;>5<#<00j=6`;8;34?>of?3:1(975a09m0=<6021bm;4?:%6:>d7<f=21=454i`794?"313k:7c:7:0c8?lg3290/844n1:l7<?7e32cj?7>5$5;9e4=i<10:o65f9g83>!2>2h;0b9651e98m<2=83.?57o>;o6;>4c<3`226=4+488b5>h303;m76l71;295?6=8r.><7??;I:3?j`=831vno=50;01>3<5=rF3>7?tH0a8yI>42;qen?4>d:&a5?6<u-?;68m4Zb824<zR=h1=v:5}n1e>5<<g8k1<75f3683>!2>2:<0b9650:9j70<72->26>84n5:95>=n;:0;6):6:248j1>=:21b??4?:%6:>60<f=21?65f3083>!2>2:<0b9654:9j75<72->26>84n5:91>=n:o0;6):6:248j1>=>21b>h4?:%6:>60<f=21;65f2e83>!2>2:<0b9658:9j6f<72->26>84n5:9=>=n:k0;6):6:248j1>=i21b>l4?:%6:>60<f=21n65f2983>!2>2:<0b965c:9j62<72->26>84n5:9`>=n:?0;6):6:248j1>=m21b>84?:%6:>60<f=21j65f2583>!2>2:<0b9651198m75=83.?57=9;o6;>47<3`896=4+48802>h303;976g=1;29 1?=;?1e854>3:9j65<72->26>84n5:951=<a8l1<7*;9;15?k2?28?07d=j:18'0<<4>2d?47?9;:k0`?6=,=31?;5a49823>=n;j0;6):6:248j1>=9110e>l50;&7=?513g>36<74;h1b>5<#<008:6`;8;3b?>o413:1(975379m0=<6j21b?54?:%6:>60<f=21=n54i2694?"3139=7c:7:0f8?l4>290/844<6:l7<?7b32c:i7>5$5;973=i<10:j65m5783>f<42lq/9=4:6:m66?6=3`8h6=44i3`94?=n:h0;66g=8;29?l402900e?850;9j60<722c987>5;h00>5<<a;81<75f2083>>d2;3:157>50z&64?223A2;7d?=:188m45=831b=94?::k21?6=3`;=6=44i0594?=n910;66g>9;29?j262900qo;;:187>5<7s-?;69=4H928m44=831b=>4?::k20?6=3f>:6=44}c76>5<4290;w);?:508L=6<a881<75f1283>>i393:17p}:2;296~X2:27>97:>;|q1g?6=:rT9o63:3;30?xu5j3:1>vP=b:?67?753ty9m7>52z\1e>;2;3;?7p}=8;296~X5027>?7?9;|q13?6=:rT9;63:3;36?xu5>3:1>vP=6:?67?703ty997>52z\11>;2;3;27p}=4;296~X5<27>?7?7;|q17?6=:rT9?63:4;30?xu5:3:1>vP=2:?60?753ty9=7>52z\15>;2<3;?7p}:3;296~;2;3>:70;::008yv332909w0;;:538903=9:1vqo;m:18`>6<bs-?;68l4o4594?=n=;0;66g=0;29?l7a2900e>k50;9j7a<722c8o7>5;h1a>5<<a:k1<75f3883>>o403:17d=;:188f0>=8331<7>t$42900=O091b=?4?::k27?6=3`;?6=44i0794?=n9?0;66g>7;29?l7?2900e<750;9l04<722wi944?:583>5}#=90??6F70:k26?6=3`;86=44i0694?=h<80;66sm5`83>6<729q/9=4;2:J;4>o6:3:17d?<:188k17=831v8950;0xZ01<5<k18<5rs4094?4|V<801865129~w76=838pR?>4=4:957=z{8l1<7<t^0d890>=9=1v>k50;0xZ6c<5<21=;5rs2f94?4|V:n01865149~w6e=838pR>m4=4:952=z{:h1<7<t^2`890>=901v>o50;0xZ6g<5<21=55rs2;94?4|V:301875129~w6>=838pR>64=4;957=z{:>1<7<t^26890?=9=1v8650;0x90>=<8169l4>2:p1<<72;q6944;1:?6e?743twi8=4?:283>5}#=9037E6?;h31>5<<a891<75`4083>>{e980;644?:1y'15<e3A2;7d?=:188m45=831b=94?::k21?6=3`;=6=44i0594?=n910;66g>9;29?j262900qo;>:187>5<7s-?;69=4H928m44=831b=>4?::k20?6=3f>:6=44}c3a>5<4290;w);?:89K<5=n9;0;66g>3;29?j262900q~=i:181[5a34>;69?4}r3b>5<5sW;j70?m:538yv`=839p19>5139>54<3927:n7?<;|q7b?6=;r7?<7?<;<72>17<58h1=?5rs4094?4|5<<19?525c866>{t=>0;6?u25c863>;293;97p}<5;296~X4=27:=7?=;%6g>60<f=i1=6s|3283>7}Y;:16=<4>3:&7`?513g>h6?5rs2094?4|V:801<?5159'0a<4>2d?o7=4}r12>5<5sW9:70?>:078 1b=;?1e8n4;;|q04?6=:rT8<63>1;35?!2c2:<0b9m55:p6c<72;qU>k5210823>"3l39=7c:l:79~w7c=838pR?k4=0395==#<m08:6`;c;58yv4c2909wS<k;<32>4?<,=n1?;5a4b8;?xu5k3:1>vP=c:?62?4d3->o6>84n5a9=>{t:k0;6?uQ2c9>13<5j2.?h7=9;o6`>d=z{;k1<7<t^3c8900=:h1/8i4<6:l7g?d<uz836=4={_0;?8312;20(9j5379m0f<d3ty9;7>52z\13>;2>38<7):k:248j1e=l2wx>;4?:3y]63=:=?09:6*;d;15?k2d2l1v?;50;0xZ73<5<<1>85+4e802>h3k3l0q~<;:181[4334?=6?:4$5f973=i<j0:<6s|2283>7}Y::169;4=3:&7`?513g>h6<?4}r01>5<5sW8970;9:308 1b=;?1e8n4>2:p64<72;qU><5257815>"3l39=7c:l:018yv472909wS<?;<7a>76<,=n1?;5a4b820>{t9o0;6?uQ1g9>1g<6n2.?h7=9;o6`>43<uz9n6=4={_1f?83e2:o0(9j5379m0f<6>2wx?i4?:3y]7a=:=k08h6*;d;15?k2d28=0q~=l:181[5d34?i6>m4$5f973=i<j0:46s|3c83>7}Y;k169o4<b:&7`?513g>h6<74}r1b>5<5sW9j70;m:2c8 1b=;?1e8n4>a:p7<<72;qU?4525c80=>"3l39=7c:l:0`8yv5?2909wS=7;<7a>6><,=n1?;5a4b82g>{t;=0;6?uQ359>1g<4<2.?h7=9;o6`>4b<uz826=4={_0:?8362890(9j5379m0f<6m2wx=h4?:3y]5`=:=80:86*;d;15?k2d28l0qplm7;2967<12;?p@5<51zJ2g>{K0:09wcl=:0d8 g7=82w/9=4:c:X`>4}62tP?n7?t4;l7c<722e:m7>5;h14>5<#<008:6`;8;28?l52290/844<6:l7<?7<3`986=4+48802>h303807d==:18'0<<4>2d?47=4;h12>5<#<008:6`;8;68?l57290/844<6:l7<?3<3`8m6=4+48802>h303<07d<j:18'0<<4>2d?4794;h0g>5<#<008:6`;8;:8?l4d290/844<6:l7<??<3`8i6=4+48802>h303k07d<n:18'0<<4>2d?47l4;h0;>5<#<008:6`;8;a8?l40290/844<6:l7<?b<3`8=6=4+48802>h303o07d<::18'0<<4>2d?47h4;h07>5<#<008:6`;8;33?>o5;3:1(975379m0=<6921b>?4?:%6:>60<f=21=?54i3394?"3139=7c:7:018?l47290/844<6:l7<?7332c:j7>5$5;973=i<10:965f3d83>!2>2:<0b9651798m6b=83.?57=9;o6;>41<3`9h6=4+48802>h303;376g<b;29 1?=;?1e854>9:9j7d<72->26>84n5:95d=<a:31<7*;9;15?k2?28h07d=7:18'0<<4>2d?47?l;:k00?6=,=31?;5a4982`>=n:00;6):6:248j1>=9l10e<k50;&7=?513g>36<h4;c75>5<d2:0nw);?:448k04=831b>n4?::k1f?6=3`8j6=44i3:94?=n:>0;66g=6;29?l422900e?:50;9j66<722c9>7>5;h02>5<<j<91<7750;2x 06=<<1C4=5f1383>>o6;3:17d?;:188m43=831b=;4?::k23?6=3`;36=44i0;94?=h<80;66sm5583>1<729q/9=4;3:J;4>o6:3:17d?<:188m42=831d8<4?::a10<72:0;6=u+51876>N?82c:>7>5;h30>5<<g=;1<75rs4094?4|V<8018;5409~w7e=838pR?m4=41956=z{;h1<7<t^3`8905=9;1v?o50;0xZ7g<5<91=95rs3:94?4|V;2018=5179~w71=838pR?94=41950=z{;<1<7<t^348905=9>1v?;50;0xZ73<5<91=45rs3694?4|V;>018=5199~w75=838pR?=4=46956=z{;81<7<t^308902=9;1v??50;0xZ77<5<>1=95rs4194?4|5<918<5254826>{t==0;6?u255875>;2=3;87psm5c83>f<42lq/9=4:b:m63?6=3`?96=44i3294?=n9o0;66g<e;29?l5c2900e>m50;9j7g<722c8m7>5;h1:>5<<a:21<75f3583>>d203:157>50z&64?223A2;7d?=:188m45=831b=94?::k21?6=3`;=6=44i0594?=n910;66g>9;29?j262900qo;6:187>5<7s-?;69=4H928m44=831b=>4?::k20?6=3f>:6=44}c7b>5<4290;w);?:508L=6<a881<75f1283>>i393:17p}:7;296~X2?27>m7:>;|q66?6=:rT>>63:8;30?xu583:1>vP=0:?6<?753ty:j7>52z\2b>;203;?7p}<e;296~X4m27>47?9;|q0`?6=:rT8h63:8;36?xu4k3:1>vP<c:?6<?703ty8n7>52z\0f>;203;27p}<a;296~X4i27>47?7;|q0=?6=:rT8563:9;30?xu403:1>vP<8:?6=?753ty887>52z\00>;213;?7p}:8;296~;203>:70;n:008yv3>2909w0;6:53890g=9:1vqo:?:180>5<7s-?;655G819j57<722c:?7>5;n62>5<<uk;:6=46:183!372k1C4=5f1383>>o6;3:17d?;:188m43=831b=;4?::k23?6=3`;36=44i0;94?=h<80;66sm5083>1<729q/9=4;3:J;4>o6:3:17d?<:188m42=831d8<4?::a5g<72:0;6=u+518:?M>73`;96=44i0194?=h<80;66s|3g83>7}Y;o168=4;1:p5d<72;qU=l521c875>{tn3:1?v3;0;31?8762=;01<l5129~w1`=839p19>5129>14<3927:n7?=;|q66?6=:r7>:7;=;<7a>04<uz?<6=4={<7a>01<5<;1=?5rs2794?4|V:?01<?5139'0a<4>2d?o7?4}r10>5<5sW9870?>:018 1b=;?1e8n4=;|q06?6=:rT8>63>1;37?!2c2:<0b9m53:p74<72;qU?<5210821>"3l39=7c:l:59~w66=838pR>>4=03953=#<m08:6`;c;78yv4a2909wS<i;<32>41<,=n1?;5a4b85?xu5m3:1>vP=e:?25?7?3->o6>84n5a93>{t:m0;6?uQ2e9>54<612.?h7=9;o6`>==z{;i1<7<t^3a8900=:j1/8i4<6:l7g??<uz8i6=4={_0a?8312;h0(9j5379m0f<f3ty9m7>52z\1e>;2>38j7):k:248j1e=j2wx>54?:3y]6==:=?0946*;d;15?k2d2j1v?950;0xZ71<5<<1>:5+4e802>h3k3n0q~<9:181[4134?=6?84$5f973=i<j0n7p}=5;296~X5=27>:7<:;%6g>60<f=i1j6s|2583>7}Y:=169;4=4:&7`?513g>h6<>4}r00>5<5sW8870;9:318 1b=;?1e8n4>1:p67<72;qU>?5257816>"3l39=7c:l:008yv462909wS<>;<75>77<,=n1?;5a4b827>{t:90;6?uQ219>1g<582.?h7=9;o6`>42<uz;m6=4={_3e?83e28l0(9j5379m0f<6=2wx?h4?:3y]7`=:=k08i6*;d;15?k2d28<0q~=k:181[5c34?i6>j4$5f973=i<j0:;6s|3b83>7}Y;j169o4<c:&7`?513g>h6<64}r1a>5<5sW9i70;m:2`8 1b=;?1e8n4>9:p7d<72;qU?l525c80e>"3l39=7c:l:0c8yv5>2909wS=6;<7a>6?<,=n1?;5a4b82f>{t;10;6?uQ399>1g<402.?h7=9;o6`>4e<uz9?6=4={_17?83e2:>0(9j5379m0f<6l2wx>44?:3y]6<=:=80:?6*;d;15?k2d28o0q~?j:181[7b34?:6<:4$5f973=i<j0:j6srb`d94?3=83:p(8>5459K<5=n9;0;66g>3;29?l732900e<;50;9l04<722wimn4?:483>5}#=90j7E6?;h31>5<<a891<75f1583>>o6=3:17b:>:188yggb290>6=4?{%73>d=O091b=?4?::k27?6=3`;?6=44i0794?=h<80;66s|a`83>7}Yih16mk4;1:pf5<72;qUn=52808e?xue=3:1>v3m3;1e?8ga2880q~l7:1808d028k01lm5149>e`<6<2wxmo4?:3y>ec<6<27jo7:>;|qb`?6=:r7jj7?:;<cf>17<uzh?6=4<{<`0>4g<5hi1=>52ad827>{tj00;6?u2b680b>;fn3;87p}87;290~X0?27i?7=8;<c`>42<5ho1=?5+4e842>h3k3:0q~9::181[1234h86>;4$5f933=i<j0:7p}83;296~X0;27i?7=<;%6g>20<f=i1>6s|7383>7}Y?;16n>4<2:&7`?113g>h6>5rs6394?4|V>;01o=5309'0a<0>2d?o7:4}r53>5<5sW=;70l<:228 1b=??1e8n4:;|q5b?6=:rT=j63m3;0e?!2c2><0b9m56:p2`<72;qU:h52b281a>"3l3==7c:l:69~w3b=838pR;j4=c196a=#<m0<:6`;c;:8yv0d2909wS8l;<`0>7e<,=n1;;5a4b8:?xu1j3:1>vP9b:?a7?4e3->o6:84n5a9e>{t>h0;6?uQ6`9>f6<5i2.?h799;o6`>g=z{?21<7<t^7:89g5=:11/8i486:l7g?e<uz<<6=4={_44?8d42;=0(9j5779m0f<c3ty=:7>52z\52>;e;38=7):k:648j1e=m2wx:84?:3y]20=:j:0996*;d;55?k2d2o1v;:50;0xZ32<5k91>95+4e842>h3k3;;7p}93;296~X1;27i?7<<;%6g>20<f=i1=<5rs7094?4|V?801o=5239'0a<0>2d?o7?=;|q55?6=:rT==63m3;02?!2c2><0b9m5129~w36=838pR;>4=c1965=#<m0<:6`;c;37?xu2n3:1>vP:f:?a7?7a3->o6:84n5a950=z{>o1<7<t^6g89g5=;l1/8i486:l7g?713ty<h7>52z\4`>;e;39o7):k:648j1e=9>1v:m50;0xZ2e<5k91?n5+4e842>h3k3;37p}8b;296~X0j27i?7=m;%6g>20<f=i1=45rs6c94?4|V>k01o=53`9'0a<0>2d?o7?n;|q4=?6=:rT<563m3;1:?!2c2><0b9m51c9~w2>=838pR:64=c197==#<m0<:6`;c;3`?xu0<3:1>vP84:?a7?533->o6:84n5a95a=z{?31<7<t^7;89g5=:01/8i486:l7g?7b3ty>i7>52z\6a>;e;3;n7):k:648j1e=9o1vl<50;6xZd4<5k=1?:52ab826>;fm3;>7):k:`38j1e=82wxm=4?:3y]e5=:j>0896*;d;c2?k2d281v4k50;0xZ<c<5k=1?>5+4e8b5>h3k380q~7k:181[?c34h<6><4$5f9e4=i<j087p}6c;296~X>k27i;7=>;%6g>d7<f=i186s|9c83>7}Y1k16n:4<0:&7`?g63g>h685rs8c94?4|V0k01o952g9'0a<f92d?o784}r;:>5<5sW3270l8:3g8 1b=i81e8n48;|q:<?6=:rT2463m7;0g?!2c2h;0b9m58:p=2<72;qU5:52b681g>"3l3k:7c:l:89~w<0=838pR484=c596g=#<m0j=6`;c;c8yv?22909wS7:;<`4>7g<,=n1m<5a4b8a?xu>;3:1>vP63:?a3?4?3->o6l?4n5a9g>{t1;0;6?uQ939>f2<5?2.?h7o>;o6`>a=z{0;1<7<t^8389g1=:?1/8i4n1:l7g?c<uz3;6=4={_;3?8d02;?0(9j5a09m0f<a3ty3j7>52z\;b>;e?38?7):k:`38j1e=991v5k50;0xZ=c<5k=1>>5+4e8b5>h3k3;:7p}7d;296~X?l27i;7<=;%6g>d7<f=i1=?5rs9a94?4|V1i01o95209'0a<f92d?o7?<;|q;f?6=:rT3n63m7;03?!2c2h;0b9m5159~w=g=838pR5o4=c595c=#<m0j=6`;c;36?xuf13:1>vPn9:?a3?5b3->o6l?4n5a953=z{h21<7<t^`:89g1=;m1/8i4n1:l7g?703tyj;7>52z\b3>;e?39h7):k:`38j1e=911vl850;0xZd0<5k=1?o5+4e8b5>h3k3;27p}n5;296~Xf=27i;7=n;%6g>d7<f=i1=l5rs`694?4|Vh>01o95389'0a<f92d?o7?m;|qb7?6=:rTj?63m7;1;?!2c2h;0b9m51b9~w<`=838pR4h4=c5971=#<m0j=6`;c;3g?xu><3:1>vP64:?a3?4>3->o6l?4n5a95`=z{131<7<t^9;89g1=9l1/8i4n1:l7g?7a3twvqpNOCz016?358<o8i<sO@Cy3yEFWstJK
\ No newline at end of file
+$b1x6d=(`fgn#d}j/fkbjko(ALON;8:Ndegq+KgIKaohg#xgd218+mijm&cxi"ifaolj+LCBM>??Mijjr.QsafofdJkxi~Mgebi-rmb639;0=<>4338JJUSS2G68=7>111906?OIX\^1T1=>:1<24>552@D[YY4V<2394;g<;;0E0>?50?c877<_4:;1<3o4338Z867=87>0MCJ=6:CM@7D6>2KEH9L>4:CM@=><J\YTECH@9:ALIHOS\LN<7N\JAUGG5>A43NDOj6IPcnosqqc)OV~f|<=4G^aliussm'MTx`~30?31?L653@;87D??3:K256=N9;90E<=<;H377>O6=;1B>?5F339J07=N=;1B:?5F739J<7=N1:1BBK:4IOD20>OIA]o0GHK__IKFVDTD@P=0@BIFC@N7?K:76<1E0<>15:L?54823G6:>3;4N=30:0=I48>596@314<6?K:6>7?0B1?8>49M84>9=2D7=40;;O>2:0=I4;:596@320<6?K:5:7?0B1<<>49M8729=2D7>80:;O>12;3<F58<285A<3:=1>H;:04?7C2=>49M8669?2D7?<4?>49M8679<2D7?3:4N=6=0>H;=7>0B1814:L?3;2<F52586@39?08JF5<FhD?7CoA199MeKEomja:7B:4OS357>IU::1D^9=4OS5`?U(588<;5<=PL59SEWRf3YCESO[\IEZa?UOIWK_XBLCJ3:PWHg=TANH^_RGAFNc8WLAXJ\YBHUl4SHE\FPUIIDOm7^AZRBG\BLJBFHGNh6]@USAF[IOIMGH:=6]ebkbhFgtmzIcine;;U[SAc=SWjef|xzj.U]wiu753]Uhc`~ztd,W[qkw494:?6ZPcnosqqc)\V~f|1>11018PZeheyi#ZPtlr?4;46;2^Tobcuug-PZrjx5:5?<84T^aliussm'^Tx`~30?]jiu?<\pznOeklk89UM@QX\PZN86V30?78\9776<1S0<?15:Z?57823Q6:?3;4X=37:0=_48?596V317<6?]:6?7?0T1?7>49[84?9<2R7=3;4X=03:0=_4;;596V323<6?]:5;7?0T1<;>49[8739=2R7>;0:;Y>13;3<P583285W<3;=0>^;:7?0T1=?>69[867=87?0T1=>>59[86833Q6?295W<4<7?]:16=1S0:0;;Y>;:1=_404:h6VFLHL[)]BE(9$:,^ZZB!2-5%GTK@C=7U][LH@4?]USWNDO=h5WSU]JIUJBELD_MYG@N^ALJVRUI@D__<>4XRV\VQJXX[E[I_ZV6:ZgfZOc991Sh`QBakmqR`ttafd:<6Vkm^OjjjtQm{ybcc=4Xrv:?]usODeoia:4Y=2=1>_;994>7T2>1?78]9756<1R0<=15:[?51823P6:93;4Y=35:0=^48=596W319<6?\:617>0U1?15:[?65823P69=3;4Y=01:0=^4;9596W325<6?\:5=7?0U1<9>49Z8719=2S7>50:;X>1=;2<Q58596W331<4?\:493:596W330<7?\:46=1R090;;X>6:1=^4?4?7T28>59Z8=833P62285fsOcm2>otFhd::6g|Zdpl2>~D`li`86vFng30?}OinVsXej`PAOF\57Yh9=1sEchPyRkdjZGILV;9Sb?>3:zJjcY~[`meSL@K_07\k42<p@dmSt]fgo]BJAY6=Ve:86vAao33?}g1{er?!>#lsf011c=i?ygt9m|g306)60<qJbnof:4yHle0>IigwKL}<79:BC|<4=N381=v]>0;;2>02=9:>::;?528db2~h?n3;0b4>56:&;a?>>3tYm64?555827171>8095ko9;e7f>5<628qX==461;77>4539?<:6?7ia79uB0>=83;1=7>tS029=4<2<3;88<891;0:bd0<,?=1>45+548ab>d2m3:18?4=:50xH=e=9r.>97lj;|N;`?4|,<i1=6`:d;68y!3a2<o0Vh4={485>x\2138p4775}h:2>5<#=>03<6`:6;28?l1a290/9:470:l62?7<3`=o6=4+568;4>h2>3807d9l:18'12<?82d>:7=4;h5a>5<#=>03<6`:6;68?l1f290/9:470:l62?3<3`=26=4+568;4>h2>3<07d97:18'12<?82d>:794;h54>5<#=>03<6`:6;:8?l11290/9:470:l62??<3`=>6=4+568;4>h2>3k07d9;:18'12<?82d>:7l4;h51>5<#=>03<6`:6;a8?l16290/9:470:l62?b<3`=;6=4+568;4>h2>3o07d8i:18'12<?82d>:7h4;h4f>5<#=>03<6`:6;33?>o1l3:1(895819m13<6921b:n4?:%74>=6<f<<1=?54i7`94?"2?32;7c;9:018?l0f290/9:470:l62?7332c=57>5$459<5=i=?0:965f8983>!3021:0b8851798m=1=83.>;76?;o75>41<3`2=6=4+568;4>h2>3;376g75;29 01=091e9;4>9:9j<1<72-?<65>4n4495d=<a191<7*:7;:3?k3128h07d6=:18'12<?82d>:7?l;:k4a?6=,<=14=5a5782`>=n?:0;6);8:928j00=9l10e;650;&63?>73g?=6<h4;hc`>5<#=>0jn6`:6;28?lgf290/9:4nb:l62?7<3`k36=4+568bf>h2>3807do8:18'12<fj2d>:7=4;hc5>5<#=>0jn6`:6;68?lg2290/9:4nb:l62?3<3`k?6=4+568bf>h2>3<07do<:18'12<fj2d>:794;hc1>5<#=>0jn6`:6;:8?lg6290/9:4nb:l62??<3`k;6=4+568bf>h2>3k07d7i:18'12<fj2d>:7l4;h;g>5<#=>0jn6`:6;a8?l?d290/9:4nb:l62?b<3`3i6=4+568bf>h2>3o07d7n:18'12<fj2d>:7h4;h;:>5<#=>0jn6`:6;33?>o>03:1(895ac9m13<6921b5:4?:%74>dd<f<<1=?54i8494?"2?3ki7c;9:018?l?2290/9:4nb:l62?7332c287>5$459eg=i=?0:965fb283>!302hh0b8851798mg4=83.>;7om;o75>41<3`h:6=4+568bf>h2>3;376gm0;29 01=ik1e9;4>9:9jec<72-?<6ll4n4495d=<aho1<7*:7;ca?k3128h07dok:18'12<fj2d>:7?l;:kb=?6=,<=1mo5a5782`>=n1l0;6);8:``8j00=9l10e4=50;&63?ge3g?=6<h4;n`7>5<<gk<1<75m8c83>4<729q/9k4>2:J;e>i693:17pl;b;2904<22==p@5m51zJ1<>{K0m09w);l:09m1a<612w/9k4;e:Xf>7}22?0vV8752z:9=?{n080;6);8:928j00=821b;k4?:%74>=6<f<<1=65f7e83>!3021:0b8852:9j3f<72-?<65>4n4497>=n?k0;6);8:928j00=<21b;l4?:%74>=6<f<<1965f7883>!3021:0b8856:9j3=<72-?<65>4n4493>=n?>0;6);8:928j00=021b;;4?:%74>=6<f<<1565f7483>!3021:0b885a:9j31<72-?<65>4n449f>=n?;0;6);8:928j00=k21b;<4?:%74>=6<f<<1h65f7183>!3021:0b885e:9j2c<72-?<65>4n449b>=n>l0;6);8:928j00=9910e;j50;&63?>73g?=6<?4;h4`>5<#=>03<6`:6;31?>o1j3:1(895819m13<6;21b:l4?:%74>=6<f<<1=954i7;94?"2?32;7c;9:078?l>?290/9:470:l62?7132c3;7>5$459<5=i=?0:;65f8783>!3021:0b8851998m=3=83.>;76?;o75>4?<3`2?6=4+568;4>h2>3;j76g73;29 01=091e9;4>b:9j<7<72-?<65>4n4495f=<a>o1<7*:7;:3?k3128n07d9<:18'12<?82d>:7?j;:k5<?6=,<=14=5a5782b>=nij0;6);8:``8j00=821bml4?:%74>dd<f<<1=65fa983>!302hh0b8852:9je2<72-?<6ll4n4497>=ni?0;6);8:``8j00=<21bm84?:%74>dd<f<<1965fa583>!302hh0b8856:9je6<72-?<6ll4n4493>=ni;0;6);8:``8j00=021bm<4?:%74>dd<f<<1565fa183>!302hh0b885a:9j=c<72-?<6ll4n449f>=n1m0;6);8:``8j00=k21b5n4?:%74>dd<f<<1h65f9c83>!302hh0b885e:9j=d<72-?<6ll4n449b>=n100;6);8:``8j00=9910e4650;&63?ge3g?=6<?4;h;4>5<#=>0jn6`:6;31?>o>>3:1(895ac9m13<6;21b584?:%74>dd<f<<1=954i8694?"2?3ki7c;9:078?ld4290/9:4nb:l62?7132ci>7>5$459eg=i=?0:;65fb083>!302hh0b8851998mg6=83.>;7om;o75>4?<3`km6=4+568bf>h2>3;j76gne;29 01=ik1e9;4>b:9jea<72-?<6ll4n4495f=<ah31<7*:7;ca?k3128n07d7j:18'12<fj2d>:7?j;:k:7?6=,<=1mo5a5782b>=hj=0;66lm7;2967<32;9p@5m51zJ1<>{K0m09w);l:19m1a<6j2w/9k496:Xf>4}32tP>57?t7;j06<72-?<69<4n4494>=n<80;6);8:508j00=921b?k4?:%74>14<f<<1>65f3d83>!302=80b8853:9j7a<72-?<69<4n4490>=n;j0;6);8:508j00==21b?o4?:%74>14<f<<1:65f3`83>!302=80b8857:9j7<<72-?<69<4n449<>=n;10;6);8:508j00=121b?:4?:%74>14<f<<1m65f3783>!302=80b885b:9j71<72-?<69<4n449g>=n;:0;6);8:508j00=l21b??4?:%74>14<f<<1i65f3083>!302=80b885f:9j75<72-?<69<4n44955=<a;l1<7*:7;61?k3128;07d<j:18'12<3:2d>:7?=;:k1`?6=,<=18?5a57827>=n:j0;6);8:508j00=9=10e?l50;&63?253g?=6<;4;h6b>5<#=>0?>6`:6;35?>o313:1(895439m13<6?21b854?:%74>14<f<<1=554i5594?"2?3>97c;9:0;8?l21290/9:4;2:l62?7f32c?97>5$45907=i=?0:n65f4583>!302=80b8851b98m16=83.>;7:=;o75>4b<3`9>6=4+56876>h2>3;n76g=a;29 01=<;1e9;4>f:9l0f<722e997>5;c6g>5<4290;w);i:`9K<d=n9<0;66g>6;29?j2a2900qo<9:180>5<7s-?m6o5G8`9j50<722c::7>5;n6e>5<<uk;?6=46:183!3a2m1C4l5f1483>>o6>3:17d?k:188m4c=831b=k4?::k14?6=3`8:6=44i3094?=h<o0;66sm6483>4>=;3;jw);i:778m7d=831b>l4?::k1g?6=3`8n6=44i3f94?=n:o0;66g<1;29?l572900e><50;9j71<722c8?7>5;h16>5<<a:=1<75f3783>>o403:17d:;:188m16=831b884?::k73?6=3`>=6=44i5;94?=n<10;66g;a;29?j072900n;<50;32>5<7s-?m68>4H9c8m43=831b=;4?::k2`?6=3`;n6=44i0d94?=n:90;66g=1;29?l452900e?=50;9j61<722c:;7>5;h3;>5<<a831<75f1`83>>o6j3:17d?l:188k1`=831vn;=50;:94?6|,<l19>5G8`9j50<722c::7>5;h3g>5<<a8o1<75f1g83>>o583:17d<>:188k1`=831vn;:50;194?6|,<l19<5G8`9j50<722c::7>5;n6e>5<<uz8i6=4={_0a?80528?0q~<n:181[4f34<96<84}r0`>5<5sW8h708=:0f8yv4b2909wS<j;<41>4c<uz8o6=4={_0g?80528l0q~<i:181[4a34<96?>4}r12>5<5sW9:708=:338yv572909wS=?;<41>74<uz996=4={_11?8052;90q~=;:181[5334<96?:4}r10>5<5sW98708=:058yv522909wS=:;<41>4><uz9<6=4={_14?8052830q~=9:181[5134<96<o4}r1;>5<5sW93708=:0`8yv232909wS:;;<41>4e<uz<:6=4={<47>43<5?818k5rs5294?4|V=:01;=5149~w13=838pR9;4=71953=z{==1<7<t^558935=9m1v9850;0xZ10<5?91=h5rs5;94?4|V=301;=51g9~w1>=838pR964=71965=z{=k1<7<t^5c8935=:81v;<50;0x932=9?16:>4;f:p25<72;qU:=526587b>{z{=;1<7<t^538942=:;1/9o4;2:l6e?7<uz9m6=4={_1e?8732;;0(8l5439m1d<53ty8i7>52z\0a>;6<38;7);m:508j0g=;2wx?i4?:3y]7a=:9=0:j6*:b;61?k3f2=1v>m50;0xZ6e<58>1=h5+5c876>h2i3?0q~=m:181[5e34;?6<j4$4`907=i=h0=7p}<a;296~X4i27:87?9;%7a>14<f<k1;6s|3883>7}Y;016=94>5:&6f?253g?j655rs2:94?4|V:201;;5399'1g<3:2d>m774}r14>5<5sW9<708::258 0d=<;1e9l4n;|q02?6=:rT8:6395;15?!3e2=80b8o5b:p71<72;qU?95264800>"2j3>97c;n:b9~w65=838pR>=4=77976=#=k0?>6`:a;f8yv552909wS==;<46>64<,<h18?5a5`8f?xu493:1>vP<1:?51?563-?i69<4n4c9b>{t;90;6?uQ319>20<482.>n7:=;o7b>46<uz8m6=4={_0e?8022;l0(8l5439m1d<692wx>h4?:3y]6`=:><09i6*:b;61?k3f2880q~<k:181[4c34<>6?j4$4`907=i=h0:?6s|2b83>7}Y:j16:84=c:&6f?253g?j6<:4}r0a>5<5sW8i708::3`8 0d=<;1e9l4>5:p0d<72;qU8l526487e>"2j3>97c;n:048yv2>2909wS:6;<46>1?<,<h18?5a5`823>{t<10;6?uQ499>20<302.>n7:=;o7b>4><uz><6=4={_64?8022==0(8l5439m1d<612wx8;4?:3y]03=:><0?:6*:b;61?k3f28k0q~:::181[2234<>69;4$4`907=i=h0:n6s|4583>7}Y<=16:84;4:&6f?253g?j6<m4}r63>5<5sW>;708::528 0d=<;1e9l4>d:p70<72;qU?85264801>"2j3>97c;n:0g8yv4f2909wS<n;<46>7g<,<h18?5a5`82b>{t9:0;6>u24e821>;5>3;=70?;:5d8H=e=9r.9;7=4}|q54?6=;r7?h7?9;<05>43<5??1:=5C8b82!402;1vq~:l:181[2d34>o69h4}r06>5<5sW8>70<9:5d8yxdd83:1>?4;:31xH=e=9rB946sC8e81!3d291e9i4>d:'1c<1>2Pn6<u;:|X6=?7|?3wb8>4?:%74>14<f<<1<65f4083>!302=80b8851:9j7c<72-?<69<4n4496>=n;l0;6);8:508j00=;21b?i4?:%74>14<f<<1865f3b83>!302=80b8855:9j7g<72-?<69<4n4492>=n;h0;6);8:508j00=?21b?44?:%74>14<f<<1465f3983>!302=80b8859:9j72<72-?<69<4n449e>=n;?0;6);8:508j00=j21b?94?:%74>14<f<<1o65f3283>!302=80b885d:9j77<72-?<69<4n449a>=n;80;6);8:508j00=n21b?=4?:%74>14<f<<1==54i3d94?"2?3>97c;9:038?l4b290/9:4;2:l62?7532c9h7>5$45907=i=?0:?65f2b83>!302=80b8851598m7d=83.>;7:=;o75>43<3`>j6=4+56876>h2>3;=76g;9;29 01=<;1e9;4>7:9j0=<72-?<69<4n4495==<a==1<7*:7;61?k3128307d:9:18'12<3:2d>:7?n;:k71?6=,<=18?5a5782f>=n<=0;6);8:508j00=9j10e9>50;&63?253g?=6<j4;h16>5<#=>0?>6`:6;3f?>o5i3:1(895439m13<6n21d8n4?::m11?6=3k>o6=4<:183!3a2h1C4l5f1483>>o6>3:17b:i:188yg4129086=4?{%7e>g=O0h1b=84?::k22?6=3f>m6=44}c37>5<>290;w);i:e9K<d=n9<0;66g>6;29?l7c2900e<k50;9j5c<722c9<7>5;h02>5<<a;81<75`4g83>>{e><0;6<653;3b!3a2??0e?l50;9j6d<722c9o7>5;h0f>5<<a;n1<75f2g83>>o493:17d=?:188m64=831b?94?::k07?6=3`9>6=44i2594?=n;?0;66g<8;29?l232900e9>50;9j00<722c?;7>5;h65>5<<a=31<75f4983>>o3i3:17b8?:188f34=83;:6=4?{%7e>06<@1k0e<;50;9j53<722c:h7>5;h3f>5<<a8l1<75f2183>>o593:17d<=:188m75=831b>94?::k23?6=3`;36=44i0;94?=n9h0;66g>b;29?l7d2900c9h50;9~f35=8321<7>t$4d916=O0h1b=84?::k22?6=3`;o6=44i0g94?=n9o0;66g=0;29?l462900c9h50;9~f32=8391<7>t$4d914=O0h1b=84?::k22?6=3f>m6=44}r0a>5<5sW8i708=:078yv4f2909wS<n;<41>40<uz8h6=4={_0`?80528n0q~<j:181[4b34<96<k4}r0g>5<5sW8o708=:0d8yv4a2909wS<i;<41>76<uz9:6=4={_12?8052;;0q~=?:181[5734<96?<4}r11>5<5sW99708=:318yv532909wS=;;<41>72<uz986=4={_10?80528=0q~=::181[5234<96<64}r14>5<5sW9<708=:0;8yv512909wS=9;<41>4g<uz936=4={_1;?80528h0q~:;:181[2334<96<m4}r42>5<5s4<?6<;4=7090c=z{=:1<7<t^528935=9<1v9;50;0xZ13<5?91=;5rs5594?4|V==01;=51e9~w10=838pR984=7195`=z{=31<7<t^5;8935=9o1v9650;0xZ1><5?91>=5rs5c94?4|V=k01;=5209~w34=838p1;:5179>26<3n2wx:=4?:3y]25=:>=0?j6srs5394?4|V=;01<:5239'1g<3:2d>m7?4}r1e>5<5sW9m70?;:338 0d=<;1e9l4=;|q0a?6=:rT8i63>4;03?!3e2=80b8o53:p7a<72;qU?i521582b>"2j3>97c;n:59~w6e=838pR>m4=0695`=#=k0?>6`:a;78yv5e2909wS=m;<37>4b<,<h18?5a5`85?xu4i3:1>vP<a:?20?713-?i69<4n4c93>{t;00;6?uQ389>51<6=2.>n7:=;o7b>==z{:21<7<t^2:8933=;11/9o4;2:l6e??<uz9<6=4={_14?8022:=0(8l5439m1d<f3ty8:7>52z\02>;1=39=7);m:508j0g=j2wx?94?:3y]71=:><0886*:b;61?k3f2j1v>=50;0xZ65<5??1?>5+5c876>h2i3n0q~==:181[5534<>6><4$4`907=i=h0n7p}<1;296~X4927=97=>;%7a>14<f<k1j6s|3183>7}Y;916:84<0:&6f?253g?j6<>4}r0e>5<5sW8m708::3d8 0d=<;1e9l4>1:p6`<72;qU>h526481a>"2j3>97c;n:008yv4c2909wS<k;<46>7b<,<h18?5a5`827>{t:j0;6?uQ2b9>20<5k2.>n7:=;o7b>42<uz8i6=4={_0a?8022;h0(8l5439m1d<6=2wx8l4?:3y]0d=:><0?m6*:b;61?k3f28<0q~:6:181[2>34<>6974$4`907=i=h0:;6s|4983>7}Y<116:84;8:&6f?253g?j6<64}r64>5<5sW><708::558 0d=<;1e9l4>9:p03<72;qU8;5264872>"2j3>97c;n:0c8yv222909wS::;<46>13<,<h18?5a5`82f>{t<=0;6?uQ459>20<3<2.>n7:=;o7b>4e<uz>;6=4={_63?8022=:0(8l5439m1d<6l2wx?84?:3y]70=:><0896*:b;61?k3f28o0q~<n:181[4f34<>6?o4$4`907=i=h0:j6s|1283>6}:<m0:963=6;35?8732=l0@5m51z&13?5<uty=<7>53z?7`?71348=6<;4=77925=K0j0:w)<8:39~yv2d2909wS:l;<6g>1`<uz8>6=4={_06?8412=l0qplm5;291?6=8r.>j7;=;I:b?l722900e<850;9j5a<722c:i7>5;n6e>5<<ukhj6=4::183!3a2j1C4l5f1483>>o6>3:17d?k:188m4c=831d8k4?::aff<72<0;6=u+5g8`?M>f3`;>6=44i0494?=n9m0;66g>e;29?j2a2900q~6>:187[>634h<69=4=cc95a=:jj0:96*:b;:3?k3f291v:h50;0xZ2`<5k=18<5+5c8;4>h2i3;0q~9k:181[1c34h<6>h4$4`9<5=i=h097p}8c;296~X0k27i;7=j;%7a>=6<f<k1?6s|7c83>7}Y?k16n:4<d:&6f?>73g?j695rs6c94?4|V>k01o953b9'1g<?82d>m7;4}r5:>5<5sW=270l8:2`8 0d=091e9l49;|q4<?6=:rT<463m7;1b?!3e21:0b8o57:p32<72;qU;:52b680=>"2j32;7c;n:99~w20=838pR:84=c597==#=k03<6`:a;;8yv122909wS9:;<`4>61<,<h14=5a5`8b?xu0<3:1>vP84:?a3?513-?i65>4n4c9f>{t?;0;6?uQ739>f2<4<2.>n76?;o7b>f=z{>;1<7<t^6389g1=;:1/9o470:l6e?b<uz=;6=4={_53?8d02:80(8l5819m1d<b3ty=j7>52z\5b>;e?39:7);m:928j0g=n2wx:h4?:3y]2`=:j>08<6*:b;:3?k3f28:0q~8k:181[0c34h<6?h4$4`9<5=i=h0:=6s|6b83>7}Y>j16n:4=e:&6f?>73g?j6<<4}r4a>5<5sW<i70l8:3f8 0d=091e9l4>3:p2d<72;qU:l52b681g>"2j32;7c;n:068yv0>2909wS86;<`4>7d<,<h14=5a5`821>{t010;6?uQ899>f2<3i2.>n76?;o7b>40<uz2<6=4={_:4?8d02=30(8l5819m1d<6?2wx4;4?:3y]<3=:j>0?46*:b;:3?k3f2820q~6::181[>234h<6994$4`9<5=i=h0:56s|8583>7}Y0=16n:4;6:&6f?>73g?j6<o4}r:0>5<5sW2870l8:578 0d=091e9l4>b:p<7<72;qU4?52b6870>"2j32;7c;n:0a8yv1b2909wS9j;<`4>16<,<h14=5a5`82`>{t?:0;6?uQ729>f2<4=2.>n76?;o7b>4c<uz<36=4={_4;?8d02;k0(8l5819m1d<6n2wxmn4?:5y]ef=:k90??63ma;36?8dd28o0(8l5ac9m1d<73tyjm7>52z\be>;d83>:7);m:``8j0g=92wxm54?:3y]e==:k908j6*:b;ca?k3f2;1vl950;0xZd1<5j:1?h5+5c8bf>h2i390q~o9:181[g134i;6>j4$4`9eg=i=h0?7p}n5;296~Xf=27h<7=l;%7a>dd<f<k196s|a583>7}Yi=16o=4<b:&6f?ge3g?j6;5rs`194?4|Vh901n>53`9'1g<fj2d>m794}rc1>5<5sWk970m?:2;8 0d=ik1e9l47;|qb5?6=:rTj=63l0;1;?!3e2hh0b8o59:pe5<72;qUm=52c1803>"2j3ki7c;n:`9~w<`=838pR4h4=b2973=#=k0jn6`:a;`8yv?c2909wS7k;<a3>62<,<h1mo5a5`8`?xu>k3:1>vP6c:?`4?543-?i6ll4n4c9`>{t1k0;6?uQ9c9>g5<4:2.>n7om;o7b>`=z{0k1<7<t^8c89f6=;81/9o4nb:l6e?`<uz326=4={_;:?8e72::0(8l5ac9m1d<682wx554?:3y]===:k909j6*:b;ca?k3f28;0q~78:181[?034i;6?k4$4`9eg=i=h0:>6s|9783>7}Y1?16o=4=d:&6f?ge3g?j6<=4}r;6>5<5sW3>70m?:3a8 0d=ik1e9l4>4:p=1<72;qU5952c181f>"2j3ki7c;n:078yvd42909wSl<;<a3>1g<,<h1mo5a5`822>{tj;0;6?uQb39>g5<312.>n7om;o7b>41<uzh:6=4={_`2?8e72=20(8l5ac9m1d<602wxn=4?:3y]f5=:k90?;6*:b;ca?k3f2830q~oi:181[ga34i;6984$4`9eg=i=h0:m6s|ad83>7}Yil16o=4;5:&6f?ge3g?j6<l4}rcg>5<5sWko70m?:568 0d=ik1e9l4>c:pe<<72;qUm452c1874>"2j3ki7c;n:0f8yv?b2909wS7j;<a3>63<,<h1mo5a5`82a>{t1:0;6?uQ929>g5<5i2.>n7om;o7b>4`<uzho6=4={<`4>1e<5k?1=i5rsc:94?5|5k=1>852b`822>;ek3;=7p}l2;296~;d83>h70l::0g8yve62908w0m?:3789gg=9l16nn4>d:pf1<72;qUn952b487b>{tj00;6?u2b4821>;ei3>m7p}mb;296~;e=3;=70ll:5d8yxu?93:1>vP71:?7f?>63-?i65>4n4c94>{t?o0;6?uQ7g9>0g<0n2.>n76?;o7b>4=z{>n1<7<t^6f891d=?m1/9o470:l6e?4<uz=h6=4={_5`?82e2>i0(8l5819m1d<43ty<n7>52z\4f>;3j3=i7);m:928j0g=<2wx;l4?:3y]3d=:<k0<m6*:b;:3?k3f2<1v:750;0xZ2?<5=h1;45+5c8;4>h2i3<0q~97:181[1?34>i6:64$4`9<5=i=h0<7p}87;296~X0?27?n798;%7a>=6<f<k146s|7783>7}Y??168o486:&6f?>73g?j645rs6794?4|V>?019l5749'1g<?82d>m7o4}r57>5<5sW=?70:m:668 0d=091e9l4m;|q46?6=:rT<>63;b;51?!3e21:0b8o5c:p34<72;qU;<524c845>"2j32;7c;n:e9~w26=838pR:>4=5`935=#=k03<6`:a;g8yv0a2909wS8i;<6a>3`<,<h14=5a5`8e?xu1m3:1>vP9e:?7f?0b3-?i65>4n4c955=z{?n1<7<t^7f891d=>m1/9o470:l6e?763ty=o7>52z\5g>;3j3<h7);m:928j0g=9;1v;l50;0xZ3d<5=h1:o5+5c8;4>h2i3;87p}9a;296~X1i27?n78n;%7a>=6<f<k1=95rs7;94?4|V?3019l5689'1g<?82d>m7?:;|q;<?6=:rT3463;b;:;?!3e21:0b8o5179~w=1=838pR594=5`9<2=#=k03<6`:a;34?xu?>3:1>vP76:?7f?>13-?i65>4n4c95==z{1?1<7<t^97891d=0<1/9o470:l6e?7>3ty387>52z\;0>;3j32?7);m:928j0g=9h1v5=50;0xZ=5<5=h14>5+5c8;4>h2i3;i7p}72;296~X?:27?n76=;%7a>=6<f<k1=n5rs6g94?4|V>o019l57d9'1g<?82d>m7?k;|q47?6=:rT<?63;b;50?!3e21:0b8o51d9~w3>=838pR;64=5`92==#=k03<6`:a;3e?xufk3:1>vPnc:?7f?gd3-?i6ll4n4c94>{tih0;6?uQa`9>0g<fi2.>n7om;o7b>4=z{h21<7<t^`:891d=i11/9o4nb:l6e?4<uzk<6=4={_c4?82e2h=0(8l5ac9m1d<43tyj:7>52z\b2>;3j3k=7);m:``8j0g=<2wxm84?:3y]e0=:<k0j96*:b;ca?k3f2<1vl:50;0xZd2<5=h1m95+5c8bf>h2i3<0q~o<:181[g434>i6l=4$4`9eg=i=h0<7p}n2;296~Xf:27?n7o=;%7a>dd<f<k146s|a083>7}Yi8168o4n1:&6f?ge3g?j645rs`294?4|Vh:019l5a19'1g<fj2d>m7o4}r;e>5<5sW3m70:m:8d8 0d=ik1e9l4m;|q:`?6=:rT2h63;b;;g?!3e2hh0b8o5c:p=f<72;qU5n524c8:g>"2j3ki7c;n:e9~w<d=838pR4l4=5`9=g=#=k0jn6`:a;g8yv?f2909wS7n;<6a><g<,<h1mo5a5`8e?xu>13:1>vP69:?7f??>3-?i6ll4n4c955=z{021<7<t^8:891d=111/9o4nb:l6e?763ty2;7>52z\:3>;3j33<7);m:``8j0g=9;1v4850;0xZ<0<5=h15;5+5c8bf>h2i3;87p}65;296~X>=27?n77:;%7a>dd<f<k1=95rs8694?4|V0>019l5959'1g<fj2d>m7?:;|qa7?6=:rTi?63;b;`0?!3e2hh0b8o5179~wg4=838pRo<4=5`9f7=#=k0jn6`:a;34?xue93:1>vPm1:?7f?d63-?i6ll4n4c95==z{k:1<7<t^c2891d=j91/9o4nb:l6e?7>3tyjj7>52z\bb>;3j3km7);m:``8j0g=9h1vlk50;0xZdc<5=h1mh5+5c8bf>h2i3;i7p}nd;296~Xfl27?n7ok;%7a>dd<f<k1=n5rs`;94?4|Vh3019l5a89'1g<fj2d>m7?k;|q:a?6=:rT2i63;b;;f?!3e2hh0b8o51d9~w<5=838pR4=4=5`9=6=#=k0jn6`:a;3e?xue<3:1>vPm4:?7f?d33tyi:7>52z?;f?763Wh=7psr}|BCG~4?13oj?o7=64CDG}7uIJ[wpNO
\ No newline at end of file
diff --git a/SpecialCasesCheck.prj b/SpecialCasesCheck.prj
index ada0325..81b04dc 100644
--- a/SpecialCasesCheck.prj
+++ b/SpecialCasesCheck.prj
@@ -1,2 +1,3 @@
 vhdl work "TypeCheck.vhd"
+vhdl work "NaNCheck.vhd"
 vhdl work "SpecialCasesCheck.vhd"
diff --git a/SpecialCasesCheck.syr b/SpecialCasesCheck.syr
index 077b6ec..749be4d 100644
--- a/SpecialCasesCheck.syr
+++ b/SpecialCasesCheck.syr
@@ -1,37 +1,42 @@
-Release 14.7 - xst P.20131013 (lin64)
+Release 14.7 - xst P.20160913 (lin64)
 Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.
 --> 
 Parameter TMPDIR set to xst/projnav.tmp
 
 
 Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.05 secs
+Total CPU time to Xst completion: 0.09 secs
  
 --> 
 Parameter xsthdpdir set to xst
 
 
 Total REAL time to Xst completion: 0.00 secs
-Total CPU time to Xst completion: 0.05 secs
+Total CPU time to Xst completion: 0.09 secs
  
 --> 
 Reading design: SpecialCasesCheck.prj
 
 TABLE OF CONTENTS
   1) Synthesis Options Summary
-  2) HDL Compilation
-  3) Design Hierarchy Analysis
-  4) HDL Analysis
-  5) HDL Synthesis
-     5.1) HDL Synthesis Report
-  6) Advanced HDL Synthesis
-     6.1) Advanced HDL Synthesis Report
-  7) Low Level Synthesis
-  8) Partition Report
-  9) Final Report
-	9.1) Device utilization summary
-	9.2) Partition Resource Summary
-	9.3) TIMING REPORT
+  2) HDL Parsing
+  3) HDL Elaboration
+  4) HDL Synthesis
+       4.1) HDL Synthesis Report
+  5) Advanced HDL Synthesis
+       5.1) Advanced HDL Synthesis Report
+  6) Low Level Synthesis
+  7) Partition Report
+  8) Design Summary
+       8.1) Primitive and Black Box Usage
+       8.2) Device utilization summary
+       8.3) Partition Resource Summary
+       8.4) Timing Report
+            8.4.1) Clock Information
+            8.4.2) Asynchronous Control Signals Information
+            8.4.3) Timing Summary
+            8.4.4) Timing Details
+            8.4.5) Cross Clock Domains Report
 
 
 =========================================================================
@@ -39,13 +44,12 @@ TABLE OF CONTENTS
 =========================================================================
 ---- Source Parameters
 Input File Name                    : "SpecialCasesCheck.prj"
-Input Format                       : mixed
 Ignore Synthesis Constraint File   : NO
 
 ---- Target Parameters
 Output File Name                   : "SpecialCasesCheck"
 Output Format                      : NGC
-Target Device                      : xc3s50-5-pq208
+Target Device                      : xa6slx4-3-csg225
 
 ---- Source Options
 Top Module Name                    : SpecialCasesCheck
@@ -56,25 +60,21 @@ FSM Style                          : LUT
 RAM Extraction                     : Yes
 RAM Style                          : Auto
 ROM Extraction                     : Yes
-Mux Style                          : Auto
-Decoder Extraction                 : YES
-Priority Encoder Extraction        : Yes
 Shift Register Extraction          : YES
-Logical Shifter Extraction         : YES
-XOR Collapsing                     : YES
 ROM Style                          : Auto
-Mux Extraction                     : Yes
 Resource Sharing                   : YES
 Asynchronous To Synchronous        : NO
-Multiplier Style                   : Auto
+Shift Register Minimum Size        : 2
+Use DSP Block                      : Auto
 Automatic Register Balancing       : No
 
 ---- Target Options
+LUT Combining                      : Auto
+Reduce Control Sets                : Auto
 Add IO Buffers                     : YES
-Global Maximum Fanout              : 500
-Add Generic Clock Buffer(BUFG)     : 8
+Global Maximum Fanout              : 100000
+Add Generic Clock Buffer(BUFG)     : 32
 Register Duplication               : YES
-Slice Packing                      : YES
 Optimize Instantiated Primitives   : NO
 Use Clock Enable                   : Yes
 Use Synchronous Set                : Yes
@@ -85,6 +85,7 @@ Equivalent register Removal        : YES
 ---- General Options
 Optimization Goal                  : Speed
 Optimization Effort                : 1
+Power Reduction                    : NO
 Keep Hierarchy                     : No
 Netlist Hierarchy                  : As_Optimized
 RTL Output                         : Yes
@@ -97,7 +98,7 @@ Bus Delimiter                      : <>
 Case Specifier                     : Maintain
 Slice Utilization Ratio            : 100
 BRAM Utilization Ratio             : 100
-Verilog 2001                       : YES
+DSP48 Utilization Ratio            : 100
 Auto BRAM Packing                  : NO
 Slice Utilization Ratio Delta      : 5
 
@@ -105,48 +106,50 @@ Slice Utilization Ratio Delta      : 5
 
 
 =========================================================================
-*                          HDL Compilation                              *
+*                          HDL Parsing                                  *
 =========================================================================
-Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" in Library work.
-Architecture typecheckarch of Entity typecheck is up to date.
-Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work.
-Entity <specialcasescheck> compiled.
-Entity <specialcasescheck> (Architecture <specialcasescheckarch>) compiled.
+Parsing VHDL file "/home/ise/gianni/IEEE754Adder/TypeCheck.vhd" into library work
+Parsing entity <TypeCheck>.
+Parsing architecture <TypeCheckArch> of entity <typecheck>.
+Parsing VHDL file "/home/ise/gianni/IEEE754Adder/NaNCheck.vhd" into library work
+Parsing entity <NaNCheck>.
+Parsing architecture <NaNCheckArch> of entity <nancheck>.
+Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd" into library work
+Parsing entity <SpecialCasesCheck>.
+Parsing architecture <SpecialCasesCheckArch> of entity <specialcasescheck>.
 
 =========================================================================
-*                     Design Hierarchy Analysis                         *
+*                            HDL Elaboration                            *
 =========================================================================
-Analyzing hierarchy for entity <SpecialCasesCheck> in library <work> (architecture <specialcasescheckarch>).
 
-Analyzing hierarchy for entity <TypeCheck> in library <work> (architecture <typecheckarch>).
+Elaborating entity <SpecialCasesCheck> (architecture <SpecialCasesCheckArch>) from library <work>.
 
+Elaborating entity <NaNCheck> (architecture <NaNCheckArch>) from library <work>.
 
-=========================================================================
-*                            HDL Analysis                               *
-=========================================================================
-Analyzing Entity <SpecialCasesCheck> in library <work> (Architecture <specialcasescheckarch>).
-Entity <SpecialCasesCheck> analyzed. Unit <SpecialCasesCheck> generated.
-
-Analyzing Entity <TypeCheck> in library <work> (Architecture <typecheckarch>).
-Entity <TypeCheck> analyzed. Unit <TypeCheck> generated.
-
+Elaborating entity <TypeCheck> (architecture <TypeCheckArch>) from library <work>.
 
 =========================================================================
 *                           HDL Synthesis                               *
 =========================================================================
 
-Performing bidirectional port resolution...
-
-Synthesizing Unit <TypeCheck>.
-    Related source file is "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd".
-WARNING:Xst:647 - Input <N<31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
-Unit <TypeCheck> synthesized.
-
-
 Synthesizing Unit <SpecialCasesCheck>.
-    Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd".
+    Related source file is "/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd".
+    Summary:
+	no macro.
 Unit <SpecialCasesCheck> synthesized.
 
+Synthesizing Unit <NaNCheck>.
+    Related source file is "/home/ise/gianni/IEEE754Adder/NaNCheck.vhd".
+    Summary:
+	no macro.
+Unit <NaNCheck> synthesized.
+
+Synthesizing Unit <TypeCheck>.
+    Related source file is "/home/ise/gianni/IEEE754Adder/TypeCheck.vhd".
+WARNING:Xst:647 - Input <N<31:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+    Summary:
+	no macro.
+Unit <TypeCheck> synthesized.
 
 =========================================================================
 HDL Synthesis Report
@@ -173,7 +176,7 @@ Optimizing unit <SpecialCasesCheck> ...
 
 Mapping all equations...
 Building and optimizing final netlist ...
-Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 1.
+Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 0.
 
 Final Macro Processing ...
 
@@ -195,38 +198,45 @@ Partition Implementation Status
 -------------------------------
 
 =========================================================================
-*                            Final Report                               *
+*                            Design Summary                             *
 =========================================================================
-Final Results
-RTL Top Level Output File Name     : SpecialCasesCheck.ngr
-Top Level Output File Name         : SpecialCasesCheck
-Output Format                      : NGC
-Optimization Goal                  : Speed
-Keep Hierarchy                     : No
 
-Design Statistics
-# IOs                              : 66
+Top Level Output File Name         : SpecialCasesCheck.ngc
 
-Cell Usage :
-# BELS                             : 24
+Primitive and Black Box Usage:
+------------------------------
+# BELS                             : 16
 #      GND                         : 1
-#      LUT2                        : 1
 #      LUT3                        : 2
-#      LUT4                        : 20
+#      LUT4                        : 2
+#      LUT5                        : 2
+#      LUT6                        : 9
 # IO Buffers                       : 66
 #      IBUF                        : 64
 #      OBUF                        : 2
-=========================================================================
 
 Device utilization summary:
 ---------------------------
 
-Selected Device : 3s50pq208-5 
+Selected Device : xa6slx4csg225-3 
 
- Number of Slices:                       13  out of    768     1%  
- Number of 4 input LUTs:                 23  out of   1536     1%  
+
+Slice Logic Utilization: 
+ Number of Slice LUTs:                   15  out of   2400     0%  
+    Number used as Logic:                15  out of   2400     0%  
+
+Slice Logic Distribution: 
+ Number of LUT Flip Flop pairs used:     15
+   Number with an unused Flip Flop:      15  out of     15   100%  
+   Number with an unused LUT:             0  out of     15     0%  
+   Number of fully used LUT-FF pairs:     0  out of     15     0%  
+   Number of unique control sets:         0
+
+IO Utilization: 
  Number of IOs:                          66
- Number of bonded IOBs:                  66  out of    124    53%  
+ Number of bonded IOBs:                  66  out of    132    50%  
+
+Specific Feature Utilization:
 
 ---------------------------
 Partition Resource Summary:
@@ -238,7 +248,7 @@ Partition Resource Summary:
 
 
 =========================================================================
-TIMING REPORT
+Timing Report
 
 NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE.
       FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT
@@ -254,50 +264,53 @@ No asynchronous control signals found in this design
 
 Timing Summary:
 ---------------
-Speed Grade: -5
+Speed Grade: -3
 
    Minimum period: No path found
    Minimum input arrival time before clock: No path found
    Maximum output required time after clock: No path found
-   Maximum combinational path delay: 13.307ns
+   Maximum combinational path delay: 7.532ns
 
-Timing Detail:
---------------
+Timing Details:
+---------------
 All values displayed in nanoseconds (ns)
 
 =========================================================================
 Timing constraint: Default path analysis
-  Total number of paths / destination ports: 72 / 1
+  Total number of paths / destination ports: 64 / 1
 -------------------------------------------------------------------------
-Delay:               13.307ns (Levels of Logic = 7)
-  Source:            Y<8> (PAD)
+Delay:               7.532ns (Levels of Logic = 5)
+  Source:            Y<4> (PAD)
   Destination:       isNan (PAD)
 
-  Data Path: Y<8> to isNan
+  Data Path: Y<4> to isNan
                                 Gate     Net
     Cell:in->out      fanout   Delay   Delay  Logical Name (Net Name)
     ----------------------------------------  ------------
-     IBUF:I->O             1   0.715   0.976  Y_8_IBUF (Y_8_IBUF)
-     LUT4:I0->O            1   0.479   0.976  isNan35 (isNan35)
-     LUT2:I0->O            1   0.479   0.704  isNan41 (isNan41)
-     LUT4:I3->O            1   0.479   0.976  isNan61 (isNan61)
-     LUT3:I0->O            1   0.479   0.976  isNan209_SW0 (N6)
-     LUT4:I0->O            1   0.479   0.681  isNan209 (isNan_OBUF)
-     OBUF:I->O                 4.909          isNan_OBUF (isNan)
+     IBUF:I->O             1   1.222   0.944  Y_4_IBUF (Y_4_IBUF)
+     LUT6:I0->O            1   0.203   0.924  NC/isNan11 (NC/isNan10)
+     LUT6:I1->O            1   0.203   0.684  NC/isNan12 (NC/isNan11)
+     LUT6:I4->O            1   0.203   0.579  NC/isNan13 (isNan_OBUF)
+     OBUF:I->O                 2.571          isNan_OBUF (isNan)
     ----------------------------------------
-    Total                     13.307ns (8.019ns logic, 5.288ns route)
-                                       (60.3% logic, 39.7% route)
+    Total                      7.532ns (4.402ns logic, 3.130ns route)
+                                       (58.4% logic, 41.6% route)
+
+=========================================================================
+
+Cross Clock Domains Report:
+--------------------------
 
 =========================================================================
 
 
-Total REAL time to Xst completion: 3.00 secs
-Total CPU time to Xst completion: 3.05 secs
+Total REAL time to Xst completion: 22.00 secs
+Total CPU time to Xst completion: 19.75 secs
  
 --> 
 
 
-Total memory usage is 606300 kilobytes
+Total memory usage is 473740 kilobytes
 
 Number of errors   :    0 (   0 filtered)
 Number of warnings :    1 (   0 filtered)
diff --git a/SpecialCasesCheck.vhd b/SpecialCasesCheck.vhd
index f74787a..4a81344 100644
--- a/SpecialCasesCheck.vhd
+++ b/SpecialCasesCheck.vhd
@@ -10,33 +10,26 @@ end SpecialCasesCheck;
 
 
 architecture SpecialCasesCheckArch of SpecialCasesCheck is
-	component TypeCheck is
+	component NaNCheck is
 		port(
-			N: in std_logic_vector(31 downto 0);
-			NaN, INF: out std_logic
+			X, Y: in std_logic_vector(31 downto 0);
+			isNan: out std_logic
 		);
 	end component;
-	
-	signal xNan: std_logic;
-	signal xInf: std_logic;
+
 	signal xSign: std_logic;
-	signal yNan: std_logic;
-	signal yInf: std_logic;
 	signal ySign: std_logic;
 	signal isSameAbsValue: std_logic;
 	
 begin
-	xCheck: TypeCheck
-		port map (N => X, NaN => xNan, INF => xInf);
-	yCheck: TypeCheck
-		port map (N => Y, NaN => yNan, INF => yInf);
+	NC: NaNCheck
+		port map (X => X, Y => Y, isNan => isNan);
 
 	xSign <= X(31);
 	ySign <= Y(31);
 	
 	isSameAbsValue <= '0'; -- TODO
 	
-	isNan <= xNan or yNan or (xInf and xSign and yInf and (not ySign)) or (xInf and (not xSign) and yInf and ySign);
 	isZero <= (xSign and (not ySign) and isSameAbsValue) or ((not xSign) and ySign and isSameAbsValue);
 end SpecialCasesCheckArch;
 
diff --git a/SpecialCasesCheck.xst b/SpecialCasesCheck.xst
index 4ad8c20..b60d7e8 100644
--- a/SpecialCasesCheck.xst
+++ b/SpecialCasesCheck.xst
@@ -2,13 +2,13 @@ set -tmpdir "xst/projnav.tmp"
 set -xsthdpdir "xst"
 run
 -ifn SpecialCasesCheck.prj
--ifmt mixed
 -ofn SpecialCasesCheck
 -ofmt NGC
--p xc3s50-5-pq208
+-p xa6slx4-3-csg225
 -top SpecialCasesCheck
 -opt_mode Speed
 -opt_level 1
+-power NO
 -iuc NO
 -keep_hierarchy No
 -netlist_hierarchy As_Optimized
@@ -22,31 +22,27 @@ run
 -case Maintain
 -slice_utilization_ratio 100
 -bram_utilization_ratio 100
--verilog2001 YES
+-dsp_utilization_ratio 100
+-lc Auto
+-reduce_control_sets Auto
 -fsm_extract YES -fsm_encoding Auto
 -safe_implementation No
 -fsm_style LUT
 -ram_extract Yes
 -ram_style Auto
 -rom_extract Yes
--mux_style Auto
--decoder_extract YES
--priority_extract Yes
 -shreg_extract YES
--shift_extract YES
--xor_collapse YES
 -rom_style Auto
 -auto_bram_packing NO
--mux_extract Yes
 -resource_sharing YES
 -async_to_sync NO
--mult_style Auto
+-shreg_min_size 2
+-use_dsp48 Auto
 -iobuf YES
--max_fanout 500
--bufg 8
+-max_fanout 100000
+-bufg 32
 -register_duplication YES
 -register_balancing No
--slice_packing YES
 -optimize_primitives NO
 -use_clock_enable Yes
 -use_sync_set Yes
diff --git a/SpecialCasesCheck_envsettings.html b/SpecialCasesCheck_envsettings.html
index a9b7595..1d78746 100644
--- a/SpecialCasesCheck_envsettings.html
+++ b/SpecialCasesCheck_envsettings.html
@@ -15,14 +15,21 @@
 </tr>
 <tr>
 <td>LD_LIBRARY_PATH</td>
-<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>LMC_HOME</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64</td>
 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
 </tr>
 <tr>
 <td>PATH</td>
-<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/ise/bin</td>
 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp;data not available&nbsp;&gt;</font></td>
@@ -74,12 +81,6 @@
 <td>&nbsp;</td>
 </tr>
 <tr>
-<td>-ifmt</td>
-<td>&nbsp;</td>
-<td>mixed</td>
-<td>MIXED</td>
-</tr>
-<tr>
 <td>-ofn</td>
 <td>&nbsp;</td>
 <td>SpecialCasesCheck</td>
@@ -94,7 +95,7 @@
 <tr>
 <td>-p</td>
 <td>&nbsp;</td>
-<td>xc3s50-5-pq208</td>
+<td>xa6slx4-3-csg225</td>
 <td>&nbsp;</td>
 </tr>
 <tr>
@@ -107,7 +108,7 @@
 <td>-opt_mode</td>
 <td>Optimization Goal</td>
 <td>Speed</td>
-<td>SPEED</td>
+<td>Speed</td>
 </tr>
 <tr>
 <td>-opt_level</td>
@@ -116,52 +117,58 @@
 <td>1</td>
 </tr>
 <tr>
+<td>-power</td>
+<td>Power Reduction</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
 <td>-iuc</td>
 <td>Use synthesis Constraints File</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-keep_hierarchy</td>
 <td>Keep Hierarchy</td>
 <td>No</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-netlist_hierarchy</td>
 <td>Netlist Hierarchy</td>
 <td>As_Optimized</td>
-<td>as_optimized</td>
+<td>As_Optimized</td>
 </tr>
 <tr>
 <td>-rtlview</td>
 <td>Generate RTL Schematic</td>
 <td>Yes</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-glob_opt</td>
 <td>Global Optimization Goal</td>
 <td>AllClockNets</td>
-<td>ALLCLOCKNETS</td>
+<td>AllClockNets</td>
 </tr>
 <tr>
 <td>-read_cores</td>
 <td>Read Cores</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-write_timing_constraints</td>
 <td>Write Timing Constraints</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-cross_clock_analysis</td>
 <td>Cross Clock Analysis</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-bus_delimiter</td>
@@ -173,37 +180,43 @@
 <td>-slice_utilization_ratio</td>
 <td>Slice Utilization Ratio</td>
 <td>100</td>
-<td>100%</td>
+<td>100</td>
 </tr>
 <tr>
 <td>-bram_utilization_ratio</td>
 <td>BRAM Utilization Ratio</td>
 <td>100</td>
-<td>100%</td>
+<td>100</td>
 </tr>
 <tr>
-<td>-verilog2001</td>
-<td>Verilog 2001</td>
-<td>YES</td>
-<td>YES</td>
+<td>-dsp_utilization_ratio</td>
+<td>DSP Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-reduce_control_sets</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-fsm_extract</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-fsm_encoding</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-safe_implementation</td>
 <td>&nbsp;</td>
 <td>No</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-fsm_style</td>
@@ -215,127 +228,127 @@
 <td>-ram_extract</td>
 <td>&nbsp;</td>
 <td>Yes</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-ram_style</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-rom_extract</td>
 <td>&nbsp;</td>
 <td>Yes</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-shreg_extract</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-rom_style</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-auto_bram_packing</td>
 <td>&nbsp;</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-resource_sharing</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-async_to_sync</td>
 <td>&nbsp;</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
-<td>-mult_style</td>
+<td>-use_dsp48</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-iobuf</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-max_fanout</td>
 <td>&nbsp;</td>
-<td>500</td>
-<td>500</td>
+<td>100000</td>
+<td>100000</td>
 </tr>
 <tr>
 <td>-bufg</td>
 <td>&nbsp;</td>
-<td>8</td>
-<td>8</td>
+<td>32</td>
+<td>16</td>
 </tr>
 <tr>
 <td>-register_duplication</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-register_balancing</td>
 <td>&nbsp;</td>
 <td>No</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-optimize_primitives</td>
 <td>&nbsp;</td>
 <td>NO</td>
-<td>NO</td>
+<td>No</td>
 </tr>
 <tr>
 <td>-use_clock_enable</td>
 <td>&nbsp;</td>
 <td>Yes</td>
-<td>YES</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-use_sync_set</td>
 <td>&nbsp;</td>
 <td>Yes</td>
-<td>YES</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-use_sync_reset</td>
 <td>&nbsp;</td>
 <td>Yes</td>
-<td>YES</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-iob</td>
 <td>&nbsp;</td>
 <td>Auto</td>
-<td>AUTO</td>
+<td>Auto</td>
 </tr>
 <tr>
 <td>-equivalent_register_removal</td>
 <td>&nbsp;</td>
 <td>YES</td>
-<td>YES</td>
+<td>Yes</td>
 </tr>
 <tr>
 <td>-slice_utilization_ratio_maxmargin</td>
 <td>&nbsp;</td>
 <td>5</td>
-<td>0%</td>
+<td>0</td>
 </tr>
 </TABLE>
 <A NAME="Operating System Information"></A>
@@ -352,28 +365,28 @@
 </tr>
 <tr>
 <td>CPU Architecture/Speed</td>
-<td>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</td>
+<td>Intel(R) Core(TM) i7-5500U CPU @ 2.40GHz/2394.454 MHz</td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 </tr>
 <tr>
 <td>Host</td>
-<td>Xilinx</td>
+<td>localhost.localdomain</td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 </tr>
 <tr>
 <td>OS Name</td>
-<td>CentOS</td>
+<td>OracleServer</td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 </tr>
 <tr>
 <td>OS Release</td>
-<td>CentOS release 6.10 (Final)</td>
+<td>Oracle Linux Server release 6.4</td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
 <td><font color=gray>&lt;&nbsp; data not available &nbsp;&gt;</font></td>
diff --git a/SpecialCasesCheck_summary.html b/SpecialCasesCheck_summary.html
index cc69285..c575689 100644
--- a/SpecialCasesCheck_summary.html
+++ b/SpecialCasesCheck_summary.html
@@ -2,7 +2,7 @@
 <BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
 <TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'>
-<TD ALIGN=CENTER COLSPAN='4'><B>SpecialCasesCheck Project Status (08/17/2019 - 16:41:04)</B></TD></TR>
+<TD ALIGN=CENTER COLSPAN='4'><B>SpecialCasesCheck Project Status (08/17/2019 - 17:19:45)</B></TD></TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
 <TD>IEEE754Adder.xise</TD>
@@ -17,14 +17,15 @@
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
-<TD>xc3s50-5pq208</TD>
+<TD>xa6slx4-3csg225</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
+<TD>
+No Errors</TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
-<TD>&nbsp;</TD>
+<TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/*.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD>
 </TR>
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
@@ -42,7 +43,7 @@
 <TR ALIGN=LEFT>
 <TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
 <TD>
-<A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck_envsettings.html'>
+<A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/SpecialCasesCheck_envsettings.html'>
 System Settings</A>
 </TD>
 <TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
@@ -52,7 +53,26 @@ System Settings</A>
 
 
 
-
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
+<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
+<TD ALIGN=RIGHT>15</TD>
+<TD ALIGN=RIGHT>2400</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>15</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
+<TD ALIGN=RIGHT>66</TD>
+<TD ALIGN=RIGHT>132</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>50%</TD>
+</TR>
+</TABLE>
 
 
 
@@ -64,7 +84,7 @@ System Settings</A>
 <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
 <TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
 <TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
-<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 17 16:39:00 2019</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 17 17:19:45 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/xst.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
 <TR ALIGN=LEFT><TD>Translation Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>Map Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
 <TR ALIGN=LEFT><TD>Place and Route Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
@@ -78,5 +98,5 @@ System Settings</A>
 </TABLE>
 
 
-<br><center><b>Date Generated:</b> 08/17/2019 - 16:41:04</center>
+<br><center><b>Date Generated:</b> 08/17/2019 - 17:19:45</center>
 </BODY></HTML>
\ No newline at end of file
diff --git a/SpecialCasesCheck_xst.xrpt b/SpecialCasesCheck_xst.xrpt
index 2217582..93a37c7 100644
--- a/SpecialCasesCheck_xst.xrpt
+++ b/SpecialCasesCheck_xst.xrpt
@@ -5,7 +5,7 @@
     The structure and the elements are likely to change over the next few releases.
     This means code written to parse this file will need to be revisited each subsequent release.-->
 
-  <application stringID="Xst" timeStamp="Sat Aug 17 18:43:52 2019">
+  <application stringID="Xst" timeStamp="Sat Aug 17 17:19:23 2019">
     <section stringID="User_Env">
       <table stringID="User_EnvVar">
         <column stringID="variable"/>
@@ -16,7 +16,7 @@
         </row>
         <row stringID="row" value="1">
           <item stringID="variable" value="LD_LIBRARY_PATH"/>
-          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:/opt/Xilinx/14.7/ISE_DS/common/lib/lin64"/>
         </row>
         <row stringID="row" value="2">
           <item stringID="variable" value="XILINX_EDK"/>
@@ -24,98 +24,86 @@
         </row>
         <row stringID="row" value="3">
           <item stringID="variable" value="PATH"/>
-          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/Luca/bin"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:/usr/lib64/qt-3.3/bin:/usr/local/bin:/usr/bin:/bin:/usr/local/sbin:/usr/sbin:/sbin:/home/ise/bin"/>
         </row>
         <row stringID="row" value="4">
+          <item stringID="variable" value="LMC_HOME"/>
+          <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64"/>
+        </row>
+        <row stringID="row" value="5">
           <item stringID="variable" value="XILINX_PLANAHEAD"/>
           <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/PlanAhead"/>
         </row>
-        <row stringID="row" value="5">
+        <row stringID="row" value="6">
           <item stringID="variable" value="XILINX"/>
           <item stringID="value" value="/opt/Xilinx/14.7/ISE_DS/ISE/"/>
         </row>
       </table>
       <item stringID="User_EnvOs" value="OS Information">
-        <item stringID="User_EnvOsname" value="CentOS"/>
-        <item stringID="User_EnvOsrelease" value="CentOS release 6.10 (Final)"/>
+        <item stringID="User_EnvOsname" value="OracleServer"/>
+        <item stringID="User_EnvOsrelease" value="Oracle Linux Server release 6.4"/>
       </item>
-      <item stringID="User_EnvHost" value="Xilinx"/>
+      <item stringID="User_EnvHost" value="localhost.localdomain"/>
       <table stringID="User_EnvCpu">
         <column stringID="arch"/>
         <column stringID="speed"/>
         <row stringID="row" value="0">
-          <item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
-          <item stringID="speed" value="2494.222 MHz"/>
-        </row>
-        <row stringID="row" value="1">
-          <item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
-          <item stringID="speed" value="2494.222 MHz"/>
-        </row>
-        <row stringID="row" value="2">
-          <item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
-          <item stringID="speed" value="2494.222 MHz"/>
-        </row>
-        <row stringID="row" value="3">
-          <item stringID="arch" value="Intel Core Processor (Haswell, no TSX)"/>
-          <item stringID="speed" value="2494.222 MHz"/>
+          <item stringID="arch" value="Intel(R) Core(TM) i7-5500U CPU @ 2.40GHz"/>
+          <item stringID="speed" value="2394.454 MHz"/>
         </row>
       </table>
     </section>
     <section stringID="XST_OPTION_SUMMARY">
       <item DEFAULT="" label="-ifn" stringID="XST_IFN" value="SpecialCasesCheck.prj"/>
-      <item DEFAULT="MIXED" label="-ifmt" stringID="XST_IFMT" value="mixed"/>
       <item DEFAULT="" label="-ofn" stringID="XST_OFN" value="SpecialCasesCheck"/>
       <item DEFAULT="NGC" label="-ofmt" stringID="XST_OFMT" value="NGC"/>
-      <item DEFAULT="" label="-p" stringID="XST_P" value="xc3s50-5-pq208"/>
+      <item DEFAULT="" label="-p" stringID="XST_P" value="xa6slx4-3-csg225"/>
       <item DEFAULT="" label="-top" stringID="XST_TOP" value="SpecialCasesCheck"/>
-      <item DEFAULT="SPEED" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
+      <item DEFAULT="Speed" label="-opt_mode" stringID="XST_OPTMODE" value="Speed"/>
       <item DEFAULT="1" label="-opt_level" stringID="XST_OPTLEVEL" value="1"/>
-      <item DEFAULT="NO" label="-iuc" stringID="XST_IUC" value="NO"/>
-      <item DEFAULT="NO" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
-      <item DEFAULT="as_optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
-      <item DEFAULT="NO" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
-      <item DEFAULT="ALLCLOCKNETS" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
-      <item DEFAULT="YES" label="-read_cores" stringID="XST_READCORES" value="YES"/>
-      <item DEFAULT="NO" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
-      <item DEFAULT="NO" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
+      <item DEFAULT="No" label="-power" stringID="XST_POWER" value="NO"/>
+      <item DEFAULT="No" label="-iuc" stringID="XST_IUC" value="NO"/>
+      <item DEFAULT="No" label="-keep_hierarchy" stringID="XST_KEEPHIERARCHY" value="No"/>
+      <item DEFAULT="As_Optimized" label="-netlist_hierarchy" stringID="XST_NETLISTHIERARCHY" value="As_Optimized"/>
+      <item DEFAULT="No" label="-rtlview" stringID="XST_RTLVIEW" value="Yes"/>
+      <item DEFAULT="AllClockNets" label="-glob_opt" stringID="XST_GLOBOPT" value="AllClockNets"/>
+      <item DEFAULT="Yes" label="-read_cores" stringID="XST_READCORES" value="YES"/>
+      <item DEFAULT="No" label="-write_timing_constraints" stringID="XST_WRITETIMINGCONSTRAINTS" value="NO"/>
+      <item DEFAULT="No" label="-cross_clock_analysis" stringID="XST_CROSSCLOCKANALYSIS" value="NO"/>
       <item DEFAULT="/" stringID="XST_HIERARCHYSEPARATOR" value="/"/>
       <item DEFAULT="&lt;>" label="-bus_delimiter" stringID="XST_BUSDELIMITER" value="&lt;>"/>
-      <item DEFAULT="MAINTAIN" stringID="XST_CASE" value="Maintain"/>
-      <item DEFAULT="100%" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
-      <item DEFAULT="100%" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
-      <item DEFAULT="YES" label="-verilog2001" stringID="XST_VERILOG2001" value="YES"/>
-      <item DEFAULT="YES" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
-      <item DEFAULT="AUTO" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
-      <item DEFAULT="NO" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
+      <item DEFAULT="Maintain" stringID="XST_CASE" value="Maintain"/>
+      <item DEFAULT="100" label="-slice_utilization_ratio" stringID="XST_SLICEUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="100" label="-bram_utilization_ratio" stringID="XST_BRAMUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="100" label="-dsp_utilization_ratio" stringID="XST_DSPUTILIZATIONRATIO" value="100"/>
+      <item DEFAULT="Auto" stringID="XST_LC" value="Auto"/>
+      <item DEFAULT="Auto" label="-reduce_control_sets" stringID="XST_REDUCECONTROLSETS" value="Auto"/>
+      <item DEFAULT="Yes" label="-fsm_extract" stringID="XST_FSMEXTRACT" value="YES"/>
+      <item DEFAULT="Auto" label="-fsm_encoding" stringID="XST_FSMENCODING" value="Auto"/>
+      <item DEFAULT="No" label="-safe_implementation" stringID="XST_SAFEIMPLEMENTATION" value="No"/>
       <item DEFAULT="LUT" label="-fsm_style" stringID="XST_FSMSTYLE" value="LUT"/>
-      <item DEFAULT="YES" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
-      <item DEFAULT="AUTO" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
-      <item DEFAULT="YES" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
-      <item DEFAULT="AUTO" stringID="XST_MUXSTYLE" value="Auto"/>
-      <item DEFAULT="NO" stringID="XST_DECODEREXTRACT" value="YES"/>
-      <item DEFAULT="NO" stringID="XST_PRIORITYEXTRACT" value="Yes"/>
-      <item DEFAULT="YES" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
-      <item DEFAULT="YES" stringID="XST_SHIFTEXTRACT" value="YES"/>
-      <item DEFAULT="YES" stringID="XST_XORCOLLAPSE" value="YES"/>
-      <item DEFAULT="AUTO" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
-      <item DEFAULT="NO" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
-      <item DEFAULT="YES" stringID="XST_MUXEXTRACT" value="Yes"/>
-      <item DEFAULT="YES" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
-      <item DEFAULT="NO" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
-      <item DEFAULT="AUTO" label="-mult_style" stringID="XST_MULTSTYLE" value="Auto"/>
-      <item DEFAULT="YES" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
-      <item DEFAULT="500" label="-max_fanout" stringID="XST_MAXFANOUT" value="500"/>
-      <item DEFAULT="8" label="-bufg" stringID="XST_BUFG" value="8"/>
-      <item DEFAULT="YES" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
-      <item DEFAULT="NO" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
-      <item DEFAULT="YES" stringID="XST_SLICEPACKING" value="YES"/>
-      <item DEFAULT="NO" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
-      <item DEFAULT="YES" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Yes"/>
-      <item DEFAULT="YES" label="-use_sync_set" stringID="XST_USESYNCSET" value="Yes"/>
-      <item DEFAULT="YES" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Yes"/>
-      <item DEFAULT="AUTO" label="-iob" stringID="XST_IOB" value="Auto"/>
-      <item DEFAULT="YES" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
-      <item DEFAULT="0%" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
+      <item DEFAULT="Yes" label="-ram_extract" stringID="XST_RAMEXTRACT" value="Yes"/>
+      <item DEFAULT="Auto" label="-ram_style" stringID="XST_RAMSTYLE" value="Auto"/>
+      <item DEFAULT="Yes" label="-rom_extract" stringID="XST_ROMEXTRACT" value="Yes"/>
+      <item DEFAULT="Yes" label="-shreg_extract" stringID="XST_SHREGEXTRACT" value="YES"/>
+      <item DEFAULT="Auto" label="-rom_style" stringID="XST_ROMSTYLE" value="Auto"/>
+      <item DEFAULT="No" label="-auto_bram_packing" stringID="XST_AUTOBRAMPACKING" value="NO"/>
+      <item DEFAULT="Yes" label="-resource_sharing" stringID="XST_RESOURCESHARING" value="YES"/>
+      <item DEFAULT="No" label="-async_to_sync" stringID="XST_ASYNCTOSYNC" value="NO"/>
+      <item DEFAULT="2" stringID="XST_SHREGMINSIZE" value="2"/>
+      <item DEFAULT="Auto" label="-use_dsp48" stringID="XST_USEDSP48" value="Auto"/>
+      <item DEFAULT="Yes" label="-iobuf" stringID="XST_IOBUF" value="YES"/>
+      <item DEFAULT="100000" label="-max_fanout" stringID="XST_MAXFANOUT" value="100000"/>
+      <item DEFAULT="16" label="-bufg" stringID="XST_BUFG" value="32"/>
+      <item DEFAULT="Yes" label="-register_duplication" stringID="XST_REGISTERDUPLICATION" value="YES"/>
+      <item DEFAULT="No" label="-register_balancing" stringID="XST_REGISTERBALANCING" value="No"/>
+      <item DEFAULT="No" label="-optimize_primitives" stringID="XST_OPTIMIZEPRIMITIVES" value="NO"/>
+      <item DEFAULT="Auto" label="-use_clock_enable" stringID="XST_USECLOCKENABLE" value="Yes"/>
+      <item DEFAULT="Auto" label="-use_sync_set" stringID="XST_USESYNCSET" value="Yes"/>
+      <item DEFAULT="Auto" label="-use_sync_reset" stringID="XST_USESYNCRESET" value="Yes"/>
+      <item DEFAULT="Auto" label="-iob" stringID="XST_IOB" value="Auto"/>
+      <item DEFAULT="Yes" label="-equivalent_register_removal" stringID="XST_EQUIVALENTREGISTERREMOVAL" value="YES"/>
+      <item DEFAULT="0" label="-slice_utilization_ratio_maxmargin" stringID="XST_SLICEUTILIZATIONRATIOMAXMARGIN" value="5"/>
     </section>
     <section stringID="XST_ADVANCED_HDL_SYNTHESIS_REPORTFOUND_NO_MACRO"/>
     <section stringID="XST_FINAL_REGISTER_REPORTFOUND_NO_MACRO"/>
@@ -124,23 +112,17 @@
         <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
       </section>
     </section>
-    <section stringID="XST_FINAL_REPORT">
-      <section stringID="XST_FINAL_RESULTS">
-        <item stringID="XST_RTL_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck.ngr"/>
-        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck"/>
-        <item stringID="XST_OUTPUT_FORMAT" value="NGC"/>
-        <item stringID="XST_OPTIMIZATION_GOAL" value="Speed"/>
-        <item stringID="XST_KEEP_HIERARCHY" value="No"/>
+    <section stringID="XST_DESIGN_SUMMARY">
+      <section stringID="XST_">
+        <item stringID="XST_TOP_LEVEL_OUTPUT_FILE_NAME" value="SpecialCasesCheck.ngc"/>
       </section>
-      <section stringID="XST_DESIGN_STATISTICS">
-        <item stringID="XST_IOS" value="66"/>
-      </section>
-      <section stringID="XST_CELL_USAGE">
-        <item dataType="int" stringID="XST_BELS" value="24">
+      <section stringID="XST_PRIMITIVE_AND_BLACK_BOX_USAGE">
+        <item dataType="int" stringID="XST_BELS" value="16">
           <item dataType="int" stringID="XST_GND" value="1"/>
-          <item dataType="int" stringID="XST_LUT2" value="1"/>
           <item dataType="int" stringID="XST_LUT3" value="2"/>
-          <item dataType="int" stringID="XST_LUT4" value="20"/>
+          <item dataType="int" stringID="XST_LUT4" value="2"/>
+          <item dataType="int" stringID="XST_LUT5" value="2"/>
+          <item dataType="int" stringID="XST_LUT6" value="9"/>
         </item>
         <item dataType="int" stringID="XST_IO_BUFFERS" value="66">
           <item dataType="int" stringID="XST_IBUF" value="64"/>
@@ -149,11 +131,16 @@
       </section>
     </section>
     <section stringID="XST_DEVICE_UTILIZATION_SUMMARY">
-      <item stringID="XST_SELECTED_DEVICE" value="3s50pq208-5"/>
-      <item AVAILABLE="768" dataType="int" label="Number of Slices" stringID="XST_NUMBER_OF_SLICES" value="13"/>
-      <item AVAILABLE="1536" dataType="int" label="Number of 4 input LUTs" stringID="XST_NUMBER_OF_4_INPUT_LUTS" value="23"/>
+      <item stringID="XST_SELECTED_DEVICE" value="xa6slx4csg225-3"/>
+      <item AVAILABLE="2400" dataType="int" label="Number of Slice LUTs" stringID="XST_NUMBER_OF_SLICE_LUTS" value="15"/>
+      <item AVAILABLE="2400" dataType="int" label="Number used as Logic" stringID="XST_NUMBER_USED_AS_LOGIC" value="15"/>
+      <item dataType="int" label="Number of LUT Flip Flop pairs used" stringID="XST_NUMBER_OF_LUT_FLIP_FLOP_PAIRS_USED" value="15"/>
+      <item AVAILABLE="15" dataType="int" label="Number with an unused Flip Flop" stringID="XST_NUMBER_WITH_AN_UNUSED_FLIP_FLOP" value="15"/>
+      <item AVAILABLE="15" dataType="int" label="Number with an unused LUT" stringID="XST_NUMBER_WITH_AN_UNUSED_LUT" value="0"/>
+      <item AVAILABLE="15" dataType="int" label="Number of fully used LUT-FF pairs" stringID="XST_NUMBER_OF_FULLY_USED_LUTFF_PAIRS" value="0"/>
+      <item dataType="int" label="Number of unique control sets" stringID="XST_NUMBER_OF_UNIQUE_CONTROL_SETS" value="0"/>
       <item dataType="int" label="Number of IOs" stringID="XST_NUMBER_OF_IOS" value="66"/>
-      <item AVAILABLE="124" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>
+      <item AVAILABLE="132" dataType="int" label="Number of bonded IOBs" stringID="XST_NUMBER_OF_BONDED_IOBS" value="66"/>
     </section>
     <section stringID="XST_PARTITION_RESOURCE_SUMMARY">
       <section stringID="XST_NO_PARTITIONS_WERE_FOUND_IN_THIS_DESIGN"/>
diff --git a/TypeCheck_envsettings.html b/TypeCheck_envsettings.html
new file mode 100644
index 0000000..cac681c
--- /dev/null
+++ b/TypeCheck_envsettings.html
@@ -0,0 +1,509 @@
+<HTML><HEAD><TITLE>Xilinx System Settings Report</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<center><big><big><b>System Settings</b></big></big></center><br>
+<A NAME="Environment Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Environment Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Environment Variable</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>LD_LIBRARY_PATH</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64/lib:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/lib:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/lib/lin64:<br>/opt/Xilinx/14.7/ISE_DS/common/lib/lin64</font></td>
+</tr>
+<tr>
+<td>LMC_HOME</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE/smartmodel/lin64/installed_lin64</td>
+<td><font color=gray>&lt;&nbsp; not set &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; not set &nbsp;&gt;</font></td>
+<td><font color=gray>&lt;&nbsp; not set &nbsp;&gt;</font></td>
+</tr>
+<tr>
+<td>PATH</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/bin:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/ise/bin</td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE//bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/ISE/sysgen/util:<br>/opt/Xilinx/14.7/ISE_DS/ISE/../../../DocNav:<br>/opt/Xilinx/14.7/ISE_DS/PlanAhead/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/bin/lin64:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/powerpc-eabi/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/arm/lin/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_be/bin:<br>/opt/Xilinx/14.7/ISE_DS/EDK/gnu/microblaze/linux_toolchain/lin64_le/bin:<br>/opt/Xilinx/14.7/ISE_DS/common/bin/lin64:<br>/usr/lib64/qt-3.3/bin:<br>/usr/local/bin:<br>/usr/bin:<br>/bin:<br>/usr/local/sbin:<br>/usr/sbin:<br>/sbin:<br>/home/Luca/bin</font></td>
+</tr>
+<tr>
+<td>XILINX</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE/</td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE/</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE/</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE/</font></td>
+</tr>
+<tr>
+<td>XILINX_DSP</td>
+<td>/opt/Xilinx/14.7/ISE_DS/ISE</td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/ISE</font></td>
+</tr>
+<tr>
+<td>XILINX_EDK</td>
+<td>/opt/Xilinx/14.7/ISE_DS/EDK</td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/EDK</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/EDK</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/EDK</font></td>
+</tr>
+<tr>
+<td>XILINX_PLANAHEAD</td>
+<td>/opt/Xilinx/14.7/ISE_DS/PlanAhead</td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/PlanAhead</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/PlanAhead</font></td>
+<td><font color=gray>/opt/Xilinx/14.7/ISE_DS/PlanAhead</font></td>
+</tr>
+</TABLE>
+<A NAME="Synthesis Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Synthesis Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td>-ifn</td>
+<td>&nbsp;</td>
+<td>TypeCheck.prj</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ofn</td>
+<td>&nbsp;</td>
+<td>TypeCheck</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-ofmt</td>
+<td>&nbsp;</td>
+<td>NGC</td>
+<td>NGC</td>
+</tr>
+<tr>
+<td>-p</td>
+<td>&nbsp;</td>
+<td>xa6slx4-3-csg225</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-top</td>
+<td>&nbsp;</td>
+<td>TypeCheck</td>
+<td>&nbsp;</td>
+</tr>
+<tr>
+<td>-opt_mode</td>
+<td>Optimization Goal</td>
+<td>Speed</td>
+<td>Speed</td>
+</tr>
+<tr>
+<td>-opt_level</td>
+<td>Optimization Effort</td>
+<td>1</td>
+<td>1</td>
+</tr>
+<tr>
+<td>-power</td>
+<td>Power Reduction</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-iuc</td>
+<td>Use synthesis Constraints File</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-keep_hierarchy</td>
+<td>Keep Hierarchy</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-netlist_hierarchy</td>
+<td>Netlist Hierarchy</td>
+<td>As_Optimized</td>
+<td>As_Optimized</td>
+</tr>
+<tr>
+<td>-rtlview</td>
+<td>Generate RTL Schematic</td>
+<td>Yes</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-glob_opt</td>
+<td>Global Optimization Goal</td>
+<td>AllClockNets</td>
+<td>AllClockNets</td>
+</tr>
+<tr>
+<td>-read_cores</td>
+<td>Read Cores</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-write_timing_constraints</td>
+<td>Write Timing Constraints</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-cross_clock_analysis</td>
+<td>Cross Clock Analysis</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-bus_delimiter</td>
+<td>Bus Delimiter</td>
+<td>&lt;&gt;</td>
+<td>&lt;&gt;</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio</td>
+<td>Slice Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-bram_utilization_ratio</td>
+<td>BRAM Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-dsp_utilization_ratio</td>
+<td>DSP Utilization Ratio</td>
+<td>100</td>
+<td>100</td>
+</tr>
+<tr>
+<td>-reduce_control_sets</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-fsm_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-fsm_encoding</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-safe_implementation</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-fsm_style</td>
+<td>&nbsp;</td>
+<td>LUT</td>
+<td>LUT</td>
+</tr>
+<tr>
+<td>-ram_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-ram_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-rom_extract</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-shreg_extract</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-rom_style</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-auto_bram_packing</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-resource_sharing</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-async_to_sync</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-use_dsp48</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-iobuf</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-max_fanout</td>
+<td>&nbsp;</td>
+<td>100000</td>
+<td>100000</td>
+</tr>
+<tr>
+<td>-bufg</td>
+<td>&nbsp;</td>
+<td>32</td>
+<td>16</td>
+</tr>
+<tr>
+<td>-register_duplication</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-register_balancing</td>
+<td>&nbsp;</td>
+<td>No</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-optimize_primitives</td>
+<td>&nbsp;</td>
+<td>NO</td>
+<td>No</td>
+</tr>
+<tr>
+<td>-use_clock_enable</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-use_sync_set</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-use_sync_reset</td>
+<td>&nbsp;</td>
+<td>Yes</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-iob</td>
+<td>&nbsp;</td>
+<td>Auto</td>
+<td>Auto</td>
+</tr>
+<tr>
+<td>-equivalent_register_removal</td>
+<td>&nbsp;</td>
+<td>YES</td>
+<td>Yes</td>
+</tr>
+<tr>
+<td>-slice_utilization_ratio_maxmargin</td>
+<td>&nbsp;</td>
+<td>5</td>
+<td>0</td>
+</tr>
+</TABLE>
+<A NAME="Translation Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Translation Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td><font color=gray>-intstyle</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>ise</font></td>
+<td><font color=gray>None</font></td>
+</tr>
+<tr>
+<td><font color=gray>-dd</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>_ngo</font></td>
+<td><font color=gray>None</font></td>
+</tr>
+<tr>
+<td><font color=gray>-p</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>xc3s50-pq208-5</font></td>
+<td><font color=gray>None</font></td>
+</tr>
+</TABLE>
+<A NAME="Map Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Map Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td><font color=gray>-ir</font></td>
+<td><font color=gray>Use RLOC Constraints</font></td>
+<td><font color=gray>OFF</font></td>
+<td><font color=gray>OFF</font></td>
+</tr>
+<tr>
+<td><font color=gray>-cm</font></td>
+<td><font color=gray>Optimization Strategy (Cover Mode)</font></td>
+<td><font color=gray>area</font></td>
+<td><font color=gray>area</font></td>
+</tr>
+<tr>
+<td><font color=gray>-intstyle</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>ise</font></td>
+<td><font color=gray>None</font></td>
+</tr>
+<tr>
+<td><font color=gray>-o</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>TypeCheck_map.ncd</font></td>
+<td><font color=gray>None</font></td>
+</tr>
+<tr>
+<td><font color=gray>-pr</font></td>
+<td><font color=gray>Pack I/O Registers/Latches into IOBs</font></td>
+<td><font color=gray>off</font></td>
+<td><font color=gray>off</font></td>
+</tr>
+<tr>
+<td><font color=gray>-p</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>xc3s50-pq208-5</font></td>
+<td><font color=gray>None</font></td>
+</tr>
+</TABLE>
+<A NAME="Place and Route Property Settings"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>Place and Route Property Settings </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Switch Name</b></td>
+<td><b>Property Name</b></td>
+<td><b>Value</b></td>
+<td><b>Default Value</b></td>
+</tr>
+<tr>
+<td><font color=gray>-t</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>1</font></td>
+<td><font color=gray>1</font></td>
+</tr>
+<tr>
+<td><font color=gray>-intstyle</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>ise</font></td>
+<td><font color=gray>&nbsp;</font></td>
+</tr>
+<tr>
+<td><font color=gray>-ol</font></td>
+<td><font color=gray>Place & Route Effort Level (Overall)</font></td>
+<td><font color=gray>high</font></td>
+<td><font color=gray>std</font></td>
+</tr>
+<tr>
+<td><font color=gray>-w</font></td>
+<td><font color=gray>&nbsp;</font></td>
+<td><font color=gray>true</font></td>
+<td><font color=gray>false</font></td>
+</tr>
+</TABLE>
+<A NAME="Operating System Information"></A>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='5'><B> Operating System Information </B></TD>
+</tr>
+<tr bgcolor='#ffff99'>
+<td><b>Operating System Information</b></td>
+<td><b>xst</b></td>
+<td><b>ngdbuild</b></td>
+<td><b>map</b></td>
+<td><b>par</b></td>
+</tr>
+<tr>
+<td>CPU Architecture/Speed</td>
+<td>Intel(R) Core(TM) i7-5500U CPU @ 2.40GHz/2394.454 MHz</td>
+<td><font color=gray>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</font></td>
+<td><font color=gray>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</font></td>
+<td><font color=gray>Intel Core Processor (Haswell, no TSX)/2494.222 MHz</font></td>
+</tr>
+<tr>
+<td>Host</td>
+<td>localhost.localdomain</td>
+<td><font color=gray>Xilinx</font></td>
+<td><font color=gray>Xilinx</font></td>
+<td><font color=gray>Xilinx</font></td>
+</tr>
+<tr>
+<td>OS Name</td>
+<td>OracleServer</td>
+<td><font color=gray>CentOS</font></td>
+<td><font color=gray>CentOS</font></td>
+<td><font color=gray>CentOS</font></td>
+</tr>
+<tr>
+<td>OS Release</td>
+<td>Oracle Linux Server release 6.4</td>
+<td><font color=gray>CentOS release 6.10 (Final)</font></td>
+<td><font color=gray>CentOS release 6.10 (Final)</font></td>
+<td><font color=gray>CentOS release 6.10 (Final)</font></td>
+</tr>
+</TABLE>
+</BODY> </HTML>
\ No newline at end of file
diff --git a/TypeCheck_summary.html b/TypeCheck_summary.html
new file mode 100644
index 0000000..bbadc90
--- /dev/null
+++ b/TypeCheck_summary.html
@@ -0,0 +1,102 @@
+<HTML><HEAD><TITLE>Xilinx Design Summary</TITLE></HEAD>
+<BODY TEXT='#000000' BGCOLOR='#FFFFFF' LINK='#0000EE' VLINK='#551A8B' ALINK='#FF0000'>
+<TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'>
+<TD ALIGN=CENTER COLSPAN='4'><B>TypeCheck Project Status (08/17/2019 - 16:39:36)</B></TD></TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Project File:</B></TD>
+<TD>IEEE754Adder.xise</TD>
+<TD BGCOLOR='#FFFF99'><b>Parser Errors:</b></TD>
+<TD> No Errors </TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Module Name:</B></TD>
+<TD>TypeCheck</TD>
+<TD BGCOLOR='#FFFF99'><B>Implementation State:</B></TD>
+<TD>Synthesized</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Target Device:</B></TD>
+<TD>xa6slx4-3csg225</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Errors:</B></LI></UL></TD>
+<TD>
+No Errors</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Product Version:</B></TD><TD>ISE 14.7</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Warnings:</B></LI></UL></TD>
+<TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/*.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Goal:</B></dif></TD>
+<TD>Balanced</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Routing Results:</B></LI></UL></TD>
+<TD>
+&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Design Strategy:</B></dif></TD>
+<TD><A HREF_DISABLED='Xilinx Default (unlocked)?&DataKey=Strategy'>Xilinx Default (unlocked)</A></TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Timing Constraints:</B></LI></UL></TD>
+<TD>&nbsp;</TD>
+</TR>
+<TR ALIGN=LEFT>
+<TD BGCOLOR='#FFFF99'><B>Environment:</B></dif></TD>
+<TD>
+<A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck_envsettings.html'>
+System Settings</A>
+</TD>
+<TD BGCOLOR='#FFFF99'><UL><LI><B>Final Timing Score:</B></LI></UL></TD>
+<TD>&nbsp;&nbsp;</TD>
+</TR>
+</TABLE>
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='4'><B>Device Utilization Summary (estimated values)</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DeviceUtilizationSummary(estimatedvalues)"><B>[-]</B></a></TD></TR>
+<TR ALIGN=CENTER BGCOLOR='#FFFF99'>
+<TD ALIGN=LEFT><B>Logic Utilization</B></TD><TD><B>Used</B></TD><TD><B>Available</B></TD><TD COLSPAN='2'><B>Utilization</B></TD></TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of Slice LUTs</TD>
+<TD ALIGN=RIGHT>9</TD>
+<TD ALIGN=RIGHT>2400</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of fully used LUT-FF pairs</TD>
+<TD ALIGN=RIGHT>0</TD>
+<TD ALIGN=RIGHT>9</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>0%</TD>
+</TR>
+<TR ALIGN=RIGHT><TD ALIGN=LEFT>Number of bonded IOBs</TD>
+<TD ALIGN=RIGHT>33</TD>
+<TD ALIGN=RIGHT>132</TD>
+<TD ALIGN=RIGHT COLSPAN='2'>25%</TD>
+</TR>
+</TABLE>
+
+
+
+
+
+
+
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='6'><B>Detailed Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=DetailedReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD><B>Generated</B></TD>
+<TD ALIGN=LEFT><B>Errors</B></TD><TD ALIGN=LEFT><B>Warnings</B></TD><TD ALIGN=LEFT COLSPAN='2'><B>Infos</B></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck.syr'>Synthesis Report</A></TD><TD>Current</TD><TD>Sat Aug 17 16:39:35 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/xst.xmsgs?&DataKey=Warning'>1 Warning (1 new)</A></TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck.bld'>Translation Report</A></TD><TD>Out of Date</TD><TD>Sat Aug 17 16:35:26 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'>0</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck_map.mrp'>Map Report</A></TD><TD>Out of Date</TD><TD>Sat Aug 17 16:35:26 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/map.xmsgs?&DataKey=Info'>4 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck.par'>Place and Route Report</A></TD><TD>Out of Date</TD><TD>Sat Aug 17 16:35:26 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/par.xmsgs?&DataKey=Info'>1 Info (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD>Power Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+<TR ALIGN=LEFT><TD><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/TypeCheck.twr'>Post-PAR Static Timing Report</A></TD><TD>Out of Date</TD><TD>Sat Aug 17 16:35:26 2019</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT>0</TD><TD ALIGN=LEFT COLSPAN='2'><A HREF_DISABLED='/home/ise/gianni/IEEE754Adder/_xmsgs/trce.xmsgs?&DataKey=Info'>6 Infos (0 new)</A></TD></TR>
+<TR ALIGN=LEFT><TD>Bitgen Report</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD>&nbsp;</TD><TD COLSPAN='2'>&nbsp;</TD></TR>
+</TABLE>
+&nbsp;<BR><TABLE BORDER CELLSPACING=0 CELLPADDING=3 WIDTH='100%'>
+<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD ALIGN=CENTER COLSPAN='3'><B>Secondary Reports</B></TD><TD ALIGN=RIGHT WIDTH='10%'COLSPAN=1> <A HREF_DISABLED="?&ExpandedTable=SecondaryReports"><B>[-]</B></a></TD></TR>
+<TR BGCOLOR='#FFFF99'><TD><B>Report Name</B></TD><TD><B>Status</B></TD><TD COLSPAN='2'><B>Generated</B></TD></TR>
+</TABLE>
+
+
+<br><center><b>Date Generated:</b> 08/17/2019 - 16:39:36</center>
+</BODY></HTML>
\ No newline at end of file
diff --git a/_xmsgs/pn_parser.xmsgs b/_xmsgs/pn_parser.xmsgs
index c57b568..2aee04b 100644
--- a/_xmsgs/pn_parser.xmsgs
+++ b/_xmsgs/pn_parser.xmsgs
@@ -8,7 +8,7 @@
 <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved.    -->
 
 <messages>
-<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd&quot; into library work</arg>
+<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd&quot; into library work</arg>
 </msg>
 
 </messages>
diff --git a/_xmsgs/xst.xmsgs b/_xmsgs/xst.xmsgs
index 7f18513..71eed22 100644
--- a/_xmsgs/xst.xmsgs
+++ b/_xmsgs/xst.xmsgs
@@ -5,7 +5,7 @@
      behavior or data corruption.  It is strongly advised that
      users do not edit the contents of this file. -->
 <messages>
-<msg type="warning" file="Xst" num="647" delta="old" >Input &lt;<arg fmt="%s" index="1">N&lt;31&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
+<msg type="warning" file="Xst" num="647" delta="new" >Input &lt;<arg fmt="%s" index="1">N&lt;31:31&gt;</arg>&gt; is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
 </msg>
 
 </messages>
diff --git a/iseconfig/IEEE754Adder.projectmgr b/iseconfig/IEEE754Adder.projectmgr
new file mode 100644
index 0000000..0b2671e
--- /dev/null
+++ b/iseconfig/IEEE754Adder.projectmgr
@@ -0,0 +1,76 @@
+<?xml version='1.0' encoding='utf-8'?>
+<!--This is an ISE project configuration file.-->
+<!--It holds project specific layout data for the projectmgr plugin.-->
+<!--Copyright (c) 1995-2009 Xilinx, Inc.  All rights reserved.-->
+<Project version="2" owner="projectmgr" name="IEEE754Adder" >
+   <!--This is an ISE project configuration file.-->
+   <ItemView engineview="SynthesisOnly" guiview="Source" compilemode="AutoCompile" >
+      <ClosedNodes>
+         <ClosedNodesVersion>2</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>SpecialCasesCheck - SpecialCasesCheckArch (/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd)</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000100000000000000000000000000000000020200000001000000010000006400000222000000020000000000000000000000000200000064ffffffff000000810000000300000002000002220000000100000003000000000000000100000003</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >true</UserChangedColumnWidths>
+      <CurrentItem>SpecialCasesCheck - SpecialCasesCheckArch (/home/ise/gianni/IEEE754Adder/SpecialCasesCheck.vhd)</CurrentItem>
+   </ItemView>
+   <ItemView engineview="SynthesisOnly" sourcetype="DESUT_VHDL_ARCHITECTURE" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>Configure Target Device</ClosedNode>
+         <ClosedNode>Design Utilities</ClosedNode>
+         <ClosedNode>Implement Design</ClosedNode>
+         <ClosedNode>User Constraints</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem>View RTL Schematic</SelectedItem>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000e5000000010000000100000000000000000000000064ffffffff000000810000000000000001000000e50000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>View RTL Schematic</CurrentItem>
+   </ItemView>
+   <ItemView guiview="File" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+      </ClosedNodes>
+      <SelectedItems/>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff0000000000000001000000000000000001000000000000000000000000000000000000028a000000040101000100000000000000000000000064ffffffff000000810000000000000004000000b600000001000000000000005d0000000100000000000000840000000100000000000000f30000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>SpecialCasesCheck.vhd</CurrentItem>
+   </ItemView>
+   <ItemView guiview="Library" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>work</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems/>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff00000000000000010000000000000000010000000000000000000000000000000000000128000000010001000100000000000000000000000064ffffffff000000810000000000000001000001280000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem>work</CurrentItem>
+   </ItemView>
+   <ItemView engineview="SynthesisOnly" sourcetype="" guiview="Process" >
+      <ClosedNodes>
+         <ClosedNodesVersion>1</ClosedNodesVersion>
+         <ClosedNode>Design Utilities</ClosedNode>
+      </ClosedNodes>
+      <SelectedItems>
+         <SelectedItem/>
+      </SelectedItems>
+      <ScrollbarPosition orientation="vertical" >0</ScrollbarPosition>
+      <ScrollbarPosition orientation="horizontal" >0</ScrollbarPosition>
+      <ViewHeaderState orientation="horizontal" >000000ff000000000000000100000001000000000000000000000000000000000000000000000000f4000000010000000100000000000000000000000064ffffffff000000810000000000000001000000f40000000100000000</ViewHeaderState>
+      <UserChangedColumnWidths orientation="horizontal" >false</UserChangedColumnWidths>
+      <CurrentItem/>
+   </ItemView>
+   <SourceProcessView>000000ff00000000000000020000014c0000011d01000000060100000002</SourceProcessView>
+   <CurrentView>Implementation</CurrentView>
+</Project>
diff --git a/iseconfig/SpecialCasesCheck.xreport b/iseconfig/SpecialCasesCheck.xreport
index 0aa7809..3623fdb 100644
--- a/iseconfig/SpecialCasesCheck.xreport
+++ b/iseconfig/SpecialCasesCheck.xreport
@@ -1,11 +1,11 @@
 <?xml version='1.0' encoding='UTF-8'?>
 <report-views version="2.0" >
  <header>
-  <DateModified>2019-08-17T15:26:24</DateModified>
+  <DateModified>2019-08-17T16:51:16</DateModified>
   <ModuleName>SpecialCasesCheck</ModuleName>
   <SummaryTimeStamp>Unknown</SummaryTimeStamp>
-  <SavedFilePath>/home/Luca/ISE/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport</SavedFilePath>
-  <ImplementationReportsDirectory>/home/Luca/ISE/IEEE754Adder</ImplementationReportsDirectory>
+  <SavedFilePath>/home/ise/gianni/IEEE754Adder/iseconfig/SpecialCasesCheck.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>/home/ise/gianni/IEEE754Adder/</ImplementationReportsDirectory>
   <DateInitialized>2019-08-17T15:26:24</DateInitialized>
   <EnableMessageFiltering>false</EnableMessageFiltering>
  </header>
diff --git a/iseconfig/TypeCheck.xreport b/iseconfig/TypeCheck.xreport
new file mode 100644
index 0000000..5ff9ff0
--- /dev/null
+++ b/iseconfig/TypeCheck.xreport
@@ -0,0 +1,215 @@
+<?xml version='1.0' encoding='UTF-8'?>
+<report-views version="2.0" >
+ <header>
+  <DateModified>2019-08-17T16:37:54</DateModified>
+  <ModuleName>TypeCheck</ModuleName>
+  <SummaryTimeStamp>Unknown</SummaryTimeStamp>
+  <SavedFilePath>/home/ise/gianni/IEEE754Adder/iseconfig/TypeCheck.xreport</SavedFilePath>
+  <ImplementationReportsDirectory>/home/ise/gianni/IEEE754Adder</ImplementationReportsDirectory>
+  <DateInitialized>2019-08-17T16:37:53</DateInitialized>
+  <EnableMessageFiltering>false</EnableMessageFiltering>
+ </header>
+ <body>
+  <viewgroup label="Design Overview" >
+   <view inputState="Unknown" program="implementation" ShowPartitionData="false" type="FPGASummary" file="TypeCheck_summary.html" label="Summary" >
+    <toc-item title="Design Overview" target="Design Overview" />
+    <toc-item title="Design Utilization Summary" target="Design Utilization Summary" />
+    <toc-item title="Performance Summary" target="Performance Summary" />
+    <toc-item title="Failing Constraints" target="Failing Constraints" />
+    <toc-item title="Detailed Reports" target="Detailed Reports" />
+   </view>
+   <view inputState="Unknown" program="implementation" contextTags="FPGA_ONLY" hidden="true" type="HTML" file="TypeCheck_envsettings.html" label="System Settings" />
+   <view inputState="Translated" program="map" locator="MAP_IOB_TABLE" contextTags="FPGA_ONLY" type="IOBProperties" file="TypeCheck_map.xrpt" label="IOB Properties" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Control_Sets" file="TypeCheck_map.xrpt" label="Control Set Information" />
+   <view inputState="Translated" program="map" locator="MAP_MODULE_HIERARCHY" contextTags="FPGA_ONLY" type="Module_Utilization" file="TypeCheck_map.xrpt" label="Module Level Utilization" />
+   <view inputState="Mapped" program="par" locator="CONSTRAINT_TABLE" contextTags="FPGA_ONLY" type="ConstraintsData" file="TypeCheck.ptwx" label="Timing Constraints" translator="ptwxToTableXML.xslt" />
+   <view inputState="Mapped" program="par" locator="PAR_PINOUT_BY_PIN_NUMBER" contextTags="FPGA_ONLY" type="PinoutData" file="TypeCheck_par.xrpt" label="Pinout Report" />
+   <view inputState="Mapped" program="par" locator="PAR_CLOCK_TABLE" contextTags="FPGA_ONLY" type="ClocksData" file="TypeCheck_par.xrpt" label="Clock Report" />
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY,EDK_OFF" type="Timing_Analyzer" file="TypeCheck.twx" label="Static Timing" />
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="TypeCheck_html/fit/report.htm" label="CPLD Fitter Report" />
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="EXTERNAL_HTML" file="TypeCheck_html/tim/report.htm" label="CPLD Timing Report" />
+  </viewgroup>
+  <viewgroup label="XPS Errors and Warnings" >
+   <view program="platgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/platgen.xmsgs" label="Platgen Messages" />
+   <view program="simgen" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/simgen.xmsgs" label="Simgen Messages" />
+   <view program="bitinit" WrapMessages="true" contextTags="EDK_ON" hidden="true" type="MessageList" hideColumns="Filtered" file="__xps/ise/_xmsgs/bitinit.xmsgs" label="BitInit Messages" />
+  </viewgroup>
+  <viewgroup label="XPS Reports" >
+   <view inputState="PreSynthesized" program="platgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="platgen.log" label="Platgen Log File" />
+   <view inputState="PreSynthesized" program="simgen" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="simgen.log" label="Simgen Log File" />
+   <view inputState="PreSynthesized" program="bitinit" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="bitinit.log" label="BitInit Log File" />
+   <view inputState="PreSynthesized" program="system" contextTags="EDK_ON" hidden="true" type="Secondary_Report" file="TypeCheck.log" label="System Log File" />
+  </viewgroup>
+  <viewgroup label="Errors and Warnings" >
+   <view program="pn" WrapMessages="true" contextTags="EDK_OFF" type="MessageList" hideColumns="Filtered, New" file="_xmsgs/pn_parser.xmsgs" label="Parser Messages" />
+   <view program="xst" WrapMessages="true" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="MessageList" hideColumns="Filtered" file="_xmsgs/xst.xmsgs" label="Synthesis Messages" />
+   <view inputState="Synthesized" program="ngdbuild" WrapMessages="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/ngdbuild.xmsgs" label="Translation Messages" />
+   <view inputState="Translated" program="map" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/map.xmsgs" label="Map Messages" />
+   <view inputState="Mapped" program="par" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/par.xmsgs" label="Place and Route Messages" />
+   <view inputState="Routed" program="trce" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/trce.xmsgs" label="Timing Messages" />
+   <view inputState="Routed" program="xpwr" WrapMessages="true" contextTags="EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/xpwr.xmsgs" label="Power Messages" />
+   <view inputState="Routed" program="bitgen" WrapMessages="true" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/bitgen.xmsgs" label="Bitgen Messages" />
+   <view inputState="Translated" program="cpldfit" WrapMessages="true" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="MessageList" hideColumns="Filtered" file="_xmsgs/cpldfit.xmsgs" label="Fitter Messages" />
+   <view inputState="Current" program="implementation" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/map.xmsgs,_xmsgs/par.xmsgs,_xmsgs/trce.xmsgs,_xmsgs/xpwr.xmsgs,_xmsgs/bitgen.xmsgs" contextTags="FPGA_ONLY" type="MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages" />
+   <view inputState="Current" program="fitting" WrapMessages="true" fileList="_xmsgs/xst.xmsgs,_xmsgs/ngdbuild.xmsgs,_xmsgs/cpldfit.xmsgs,_xmsgs/xpwr.xmsgs" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="CPLD_MessageList" hideColumns="Filtered" file="_xmsgs/*.xmsgs" label="All Implementation Messages (CPLD)" />
+  </viewgroup>
+  <viewgroup label="Detailed Reports" >
+   <view program="xst" contextTags="XST_ONLY,EDK_OFF" hidden="false" type="Report" file="TypeCheck.syr" label="Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright " searchDir="Forward" />
+    <toc-item title="Synthesis Options Summary" target="   Synthesis Options Summary   " />
+    <toc-item title="HDL Compilation" target="   HDL Compilation   " />
+    <toc-item title="Design Hierarchy Analysis" target="   Design Hierarchy Analysis   " />
+    <toc-item title="HDL Analysis" target="   HDL Analysis   " />
+    <toc-item title="HDL Parsing" target="   HDL Parsing   " />
+    <toc-item title="HDL Elaboration" target="   HDL Elaboration   " />
+    <toc-item title="HDL Synthesis" target="   HDL Synthesis   " />
+    <toc-item title="HDL Synthesis Report" target="HDL Synthesis Report" searchCnt="2" searchDir="Backward" subItemLevel="1" />
+    <toc-item title="Advanced HDL Synthesis" target="   Advanced HDL Synthesis   " searchDir="Backward" />
+    <toc-item title="Advanced HDL Synthesis Report" target="Advanced HDL Synthesis Report" subItemLevel="1" />
+    <toc-item title="Low Level Synthesis" target="   Low Level Synthesis   " />
+    <toc-item title="Partition Report" target="   Partition Report     " />
+    <toc-item title="Final Report" target="   Final Report   " />
+    <toc-item title="Design Summary" target="   Design Summary   " />
+    <toc-item title="Primitive and Black Box Usage" target="Primitive and Black Box Usage:" subItemLevel="1" />
+    <toc-item title="Device Utilization Summary" target="Device utilization summary:" subItemLevel="1" />
+    <toc-item title="Partition Resource Summary" target="Partition Resource Summary:" subItemLevel="1" />
+    <toc-item title="Timing Report" target="Timing Report" subItemLevel="1" />
+    <toc-item title="Clock Information" target="Clock Information" subItemLevel="2" />
+    <toc-item title="Asynchronous Control Signals Information" target="Asynchronous Control Signals Information" subItemLevel="2" />
+    <toc-item title="Timing Summary" target="Timing Summary" subItemLevel="2" />
+    <toc-item title="Timing Details" target="Timing Details" subItemLevel="2" />
+    <toc-item title="Cross Clock Domains Report" target="Cross Clock Domains Report:" subItemLevel="2" />
+   </view>
+   <view program="synplify" contextTags="SYNPLIFY_ONLY,EDK_OFF" hidden="true" type="Report" file="TypeCheck.srr" label="Synplify Report" />
+   <view program="precision" contextTags="PRECISION_ONLY,EDK_OFF" hidden="true" type="Report" file="TypeCheck.prec_log" label="Precision Report" />
+   <view inputState="Synthesized" program="ngdbuild" type="Report" file="TypeCheck.bld" label="Translation Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Command Line" target="Command Line:" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Final Summary" target="NGDBUILD Design Results Summary:" />
+   </view>
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" type="Report" file="TypeCheck_map.mrp" label="Map Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Section 1: Errors" target="Section 1 -" searchDir="Backward" />
+    <toc-item title="Section 2: Warnings" target="Section 2 -" searchDir="Backward" />
+    <toc-item title="Section 3: Infos" target="Section 3 -" searchDir="Backward" />
+    <toc-item title="Section 4: Removed Logic Summary" target="Section 4 -" searchDir="Backward" />
+    <toc-item title="Section 5: Removed Logic" target="Section 5 -" searchDir="Backward" />
+    <toc-item title="Section 6: IOB Properties" target="Section 6 -" searchDir="Backward" />
+    <toc-item title="Section 7: RPMs" target="Section 7 -" searchDir="Backward" />
+    <toc-item title="Section 8: Guide Report" target="Section 8 -" searchDir="Backward" />
+    <toc-item title="Section 9: Area Group and Partition Summary" target="Section 9 -" searchDir="Backward" />
+    <toc-item title="Section 10: Timing Report" target="Section 10 -" searchDir="Backward" />
+    <toc-item title="Section 11: Configuration String Details" target="Section 11 -" searchDir="Backward" />
+    <toc-item title="Section 12: Control Set Information" target="Section 12 -" searchDir="Backward" />
+    <toc-item title="Section 13: Utilization by Hierarchy" target="Section 13 -" searchDir="Backward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" type="Report" file="TypeCheck.par" label="Place and Route Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Device Utilization" target="Device Utilization Summary:" />
+    <toc-item title="Router Information" target="Starting Router" />
+    <toc-item title="Partition Status" target="Partition Implementation Status" />
+    <toc-item title="Clock Report" target="Generating Clock Report" />
+    <toc-item title="Timing Results" target="Timing Score:" />
+    <toc-item title="Final Summary" target="Peak Memory Usage:" />
+   </view>
+   <view inputState="Routed" program="trce" contextTags="FPGA_ONLY" type="Report" file="TypeCheck.twr" label="Post-PAR Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Translated" program="cpldfit" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="TypeCheck.rpt" label="CPLD Fitter Report (Text)" >
+    <toc-item title="Top of Report" target="cpldfit:" searchDir="Forward" />
+    <toc-item title="Resources Summary" target="**  Mapped Resource Summary  **" />
+    <toc-item title="Pin Resources" target="** Pin Resources **" />
+    <toc-item title="Global Resources" target="** Global Control Resources **" />
+   </view>
+   <view inputState="Fitted" program="taengine" contextTags="CPLD_ONLY,EDK_OFF" hidden="true" type="Report" file="TypeCheck.tim" label="CPLD Timing Report (Text)" >
+    <toc-item title="Top of Report" target="Performance Summary Report" searchDir="Forward" />
+    <toc-item title="Performance Summary" target="Performance Summary:" />
+   </view>
+   <view inputState="Routed" program="xpwr" contextTags="EDK_OFF" type="Report" file="TypeCheck.pwr" label="Power Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Power summary" target="Power summary" />
+    <toc-item title="Thermal summary" target="Thermal summary" />
+   </view>
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" type="Report" file="TypeCheck.bgn" label="Bitgen Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Bitgen Options" target="Summary of Bitgen Options:" />
+    <toc-item title="Final Summary" target="DRC detected" />
+   </view>
+  </viewgroup>
+  <viewgroup label="Secondary Reports" >
+   <view inputState="PreSynthesized" program="isim" hidden="if_missing" type="Secondary_Report" file="isim.log" label="ISIM Simulator Log" />
+   <view inputState="Synthesized" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/synthesis/TypeCheck_synthesis.nlf" label="Post-Synthesis Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/translate/TypeCheck_translate.nlf" label="Post-Translate Simulation Model Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Translated" program="netgen" hidden="if_missing" type="Secondary_Report" file="TypeCheck_tran_fecn.nlf" label="Post-Translate Formality Netlist Report" />
+   <view inputState="Translated" program="map" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="TypeCheck_map.map" label="Map Log File" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+    <toc-item title="Design Information" target="Design Information" />
+    <toc-item title="Design Summary" target="Design Summary" />
+   </view>
+   <view inputState="Routed" program="smartxplorer" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="smartxplorer_results/smartxplorer.txt" label="SmartXplorer Report" />
+   <view inputState="Mapped" program="trce" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck_preroute.twr" label="Post-Map Static Timing Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+    <toc-item title="Timing Report Description" target="Device,package,speed:" />
+    <toc-item title="Informational Messages" target="INFO:" />
+    <toc-item title="Warning Messages" target="WARNING:" />
+    <toc-item title="Timing Constraints" target="Timing constraint:" />
+    <toc-item title="Derived Constraint Report" target="Derived Constraint Report" />
+    <toc-item title="Data Sheet Report" target="Data Sheet report:" />
+    <toc-item title="Timing Summary" target="Timing summary:" />
+    <toc-item title="Trace Settings" target="Trace Settings:" />
+   </view>
+   <view inputState="Mapped" program="netgen" hidden="if_missing" type="Secondary_Report" file="netgen/map/TypeCheck_map.nlf" label="Post-Map Simulation Model Report" />
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck_map.psr" label="Physical Synthesis Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Pad_Report" file="TypeCheck_pad.txt" label="Pad Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="true" type="Secondary_Report" file="TypeCheck.unroutes" label="Unroutes Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="map" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck_preroute.tsi" label="Post-Map Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Mapped" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.grf" label="Guide Results Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.dly" label="Asynchronous Delay Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.clk_rgn" label="Clock Region Report" />
+   <view inputState="Routed" program="par" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.tsi" label="Post-Place and Route Constraints Interaction Report" >
+    <toc-item title="Top of Report" target="Copyright (c)" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="TypeCheck_par_fecn.nlf" label="Post-Place and Route Formality Netlist Report" />
+   <view inputState="Routed" program="netgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="netgen/par/TypeCheck_timesim.nlf" label="Post-Place and Route Simulation Model Report" />
+   <view inputState="Routed" program="netgen" hidden="if_missing" type="Secondary_Report" file="TypeCheck_sta.nlf" label="Primetime Netlist Report" >
+    <toc-item title="Top of Report" target="Release" searchDir="Forward" />
+   </view>
+   <view inputState="Routed" program="ibiswriter" hidden="if_missing" type="Secondary_Report" file="TypeCheck.ibs" label="IBIS Model" >
+    <toc-item title="Top of Report" target="IBIS Models for" searchDir="Forward" />
+    <toc-item title="Component" target="Component " />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.lck" label="Back-annotate Pin Report" >
+    <toc-item title="Top of Report" target="pin2ucf Report File" searchDir="Forward" />
+    <toc-item title="Constraint Conflicts Information" target="Constraint Conflicts Information" />
+   </view>
+   <view inputState="Routed" program="pin2ucf" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="TypeCheck.lpc" label="Locked Pin Constraints" >
+    <toc-item title="Top of Report" target="top.lpc" searchDir="Forward" />
+    <toc-item title="Newly Added Constraints" target="The following constraints were newly added" />
+   </view>
+   <view inputState="Translated" program="netgen" contextTags="CPLD_ONLY,EDK_OFF" hidden="if_missing" type="Secondary_Report" file="netgen/fit/TypeCheck_timesim.nlf" label="Post-Fit Simulation Model Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="HTML" file="usage_statistics_webtalk.html" label="WebTalk Report" />
+   <view inputState="Routed" program="bitgen" contextTags="FPGA_ONLY" hidden="if_missing" type="Secondary_Report" file="webtalk.log" label="WebTalk Log File" />
+  </viewgroup>
+ </body>
+</report-views>
diff --git a/webtalk_pn.xml b/webtalk_pn.xml
index b32f26a..e8c38e2 100644
--- a/webtalk_pn.xml
+++ b/webtalk_pn.xml
@@ -3,15 +3,16 @@
 <!--The data in this file is primarily intended for consumption by Xilinx tools.
 The structure and the elements are likely to change over the next few releases.
 This means code written to parse this file will need to be revisited each subsequent release.-->
-<application name="pn" timeStamp="Sat Aug 17 18:43:50 2019">
+<application name="pn" timeStamp="Sat Aug 17 17:19:19 2019">
 <section name="Project Information" visible="false">
-<property name="ProjectID" value="0" type="project"/>
+<property name="ProjectID" value="4B48FA10A560F77F46DA66FD7F346092" type="project"/>
 <property name="ProjectIteration" value="0" type="project"/>
-<property name="ProjectFile" value="/home/Luca/ISE/IEEE754Adder/IEEE754Adder.xise" type="project"/>
-<property name="ProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="project"/>
+<property name="ProjectFile" value="/home/ise/gianni/IEEE754Adder/IEEE754Adder.xise" type="project"/>
+<property name="ProjectCreationTimestamp" value="2019-08-17T16:51:15" type="project"/>
 </section>
 <section name="Project Statistics" visible="true">
 <property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
+<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
 <property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
 <property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
 <property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
@@ -21,19 +22,26 @@ This means code written to parse this file will need to be revisited each subseq
 <property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
 <property name="PROP_UseSmartGuide" value="false" type="design"/>
 <property name="PROP_UserBrowsedStrategyFiles" value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" type="process"/>
-<property name="PROP_intProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="design"/>
-<property name="PROP_intWbtProjectID" value="0" type="design"/>
-<property name="PROP_intWorkingDirLocWRTProjDir" value="UnableToCalculate" type="design"/>
-<property name="PROP_intWorkingDirUsed" value="Unknown" type="design"/>
+<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
+<property name="PROP_intProjectCreationTimestamp" value="2019-08-17T16:51:15" type="design"/>
+<property name="PROP_intWbtProjectID" value="4B48FA10A560F77F46DA66FD7F346092" type="design"/>
+<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
+<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
+<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
+<property name="PROP_xilxSynthAddBufg_spartan6" value="32" type="process"/>
+<property name="PROP_xstUseClockEnable_spartan6" value="Yes" type="process"/>
+<property name="PROP_xstUseSyncReset_spartan6" value="Yes" type="process"/>
+<property name="PROP_xstUseSyncSet_spartan6" value="Yes" type="process"/>
+<property name="PROPEXT_mapTimingMode_spartan6" value="Non Timing Driven" type="process"/>
 <property name="PROP_AutoTop" value="true" type="design"/>
-<property name="PROP_DevFamily" value="Spartan3" type="design"/>
-<property name="PROP_DevDevice" value="xc3s50" type="design"/>
-<property name="PROP_DevFamilyPMName" value="spartan3" type="design"/>
-<property name="PROP_DevPackage" value="pq208" type="design"/>
+<property name="PROP_DevFamily" value="Automotive Spartan6" type="design"/>
+<property name="PROP_DevDevice" value="xa6slx4" type="design"/>
+<property name="PROP_DevFamilyPMName" value="aspartan6" type="design"/>
+<property name="PROP_DevPackage" value="csg225" type="design"/>
 <property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
-<property name="PROP_DevSpeed" value="-5" type="design"/>
+<property name="PROP_DevSpeed" value="-3" type="design"/>
 <property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
-<property name="FILE_VHDL" value="2" type="source"/>
+<property name="FILE_VHDL" value="3" type="source"/>
 </section>
 </application>
 </document>
diff --git a/xst/work/work.vdbl b/xst/work/work.vdbl
new file mode 100644
index 0000000..f0a1800
Binary files /dev/null and b/xst/work/work.vdbl differ
diff --git a/xst/work/work.vdbx b/xst/work/work.vdbx
new file mode 100644
index 0000000..00066de
Binary files /dev/null and b/xst/work/work.vdbx differ