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Refactoring controllo NaN

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Giulio
2019-08-17 19:22:19 +02:00
parent 47cc74e0d0
commit 2ecaee1b19
23 changed files with 1337 additions and 392 deletions
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36
webtalk_pn.xml
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@@ -3,15 +3,16 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Aug 17 18:43:50 2019">
<application name="pn" timeStamp="Sat Aug 17 17:19:19 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="0" type="project"/>
<property name="ProjectID" value="4B48FA10A560F77F46DA66FD7F346092" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="/home/Luca/ISE/IEEE754Adder/IEEE754Adder.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="project"/>
<property name="ProjectFile" value="/home/ise/gianni/IEEE754Adder/IEEE754Adder.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2019-08-17T16:51:15" type="project"/>
</section>
<section name="Project Statistics" visible="true">
<property name="PROP_Enable_Message_Filtering" value="false" type="design"/>
<property name="PROP_FitterReportFormat" value="HTML" type="process"/>
<property name="PROP_LastAppliedGoal" value="Balanced" type="design"/>
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
@@ -21,19 +22,26 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
<property name="PROP_UseSmartGuide" value="false" type="design"/>
<property name="PROP_UserBrowsedStrategyFiles" value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="YYYY-MM-DDTHH:MM:SS" type="design"/>
<property name="PROP_intWbtProjectID" value="0" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="UnableToCalculate" type="design"/>
<property name="PROP_intWorkingDirUsed" value="Unknown" type="design"/>
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2019-08-17T16:51:15" type="design"/>
<property name="PROP_intWbtProjectID" value="4B48FA10A560F77F46DA66FD7F346092" type="design"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_xilxSynthAddBufg_spartan6" value="32" type="process"/>
<property name="PROP_xstUseClockEnable_spartan6" value="Yes" type="process"/>
<property name="PROP_xstUseSyncReset_spartan6" value="Yes" type="process"/>
<property name="PROP_xstUseSyncSet_spartan6" value="Yes" type="process"/>
<property name="PROPEXT_mapTimingMode_spartan6" value="Non Timing Driven" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_DevFamily" value="Spartan3" type="design"/>
<property name="PROP_DevDevice" value="xc3s50" type="design"/>
<property name="PROP_DevFamilyPMName" value="spartan3" type="design"/>
<property name="PROP_DevPackage" value="pq208" type="design"/>
<property name="PROP_DevFamily" value="Automotive Spartan6" type="design"/>
<property name="PROP_DevDevice" value="xa6slx4" type="design"/>
<property name="PROP_DevFamilyPMName" value="aspartan6" type="design"/>
<property name="PROP_DevPackage" value="csg225" type="design"/>
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-5" type="design"/>
<property name="PROP_DevSpeed" value="-3" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="2" type="source"/>
<property name="FILE_VHDL" value="3" type="source"/>
</section>
</application>
</document>