2019-09-08 23:16:55 +02:00
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/NormalizerTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/NormalizerTest_beh.prj work.NormalizerTest
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ISim P.20131013 (signature 0xfbc00daa)
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Number of CPUs detected in this system: 4
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Turning on mult-threading, number of parallel sub-compilation jobs: 8
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2019-08-24 14:39:01 +02:00
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Determining compilation order of HDL files
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2019-09-08 23:16:55 +02:00
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/UTILS.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounter.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ShiftLeft.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Comparator.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSub.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Normalizer.vhd" into library work
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Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/NormalizerTest.vhd" into library work
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2019-08-24 14:39:01 +02:00
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Starting static elaboration
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2019-09-07 15:54:31 +02:00
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Completed static elaboration
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2019-09-08 23:16:55 +02:00
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Fuse Memory Usage: 96516 KB
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Fuse CPU Usage: 1020 ms
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2019-09-07 15:54:31 +02:00
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Compiling package standard
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Compiling package std_logic_1164
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2019-09-08 23:16:55 +02:00
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Compiling package numeric_std
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Compiling package math_real
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Compiling package utils
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Compiling architecture zerocounterarch of entity ZeroCounter [\ZeroCounter(48,8)\]
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Compiling architecture comparatorarch of entity Comparator [\Comparator(8)\]
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Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
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Compiling architecture addsubarch of entity AddSub [\AddSub(8)\]
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Compiling architecture shiftleftarch of entity ShiftLeft48 [shiftleft48_default]
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Compiling architecture normalizerarch of entity Normalizer [normalizer_default]
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Compiling architecture behavior of entity normalizertest
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2019-09-07 15:54:31 +02:00
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Time Resolution for simulation is 1ps.
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2019-09-08 23:16:55 +02:00
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Waiting for 1 sub-compilation(s) to finish...
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Compiled 18 VHDL Units
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Built simulation executable /home/Luca/ISE/IEEE754Adder/NormalizerTest_isim_beh.exe
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Fuse Memory Usage: 670604 KB
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Fuse CPU Usage: 1130 ms
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GCC CPU Usage: 480 ms
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