2019-08-30 19:24:54 +02:00
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Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/SumDataAdapterTest_beh.prj work.SumDataAdapterTest
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2019-08-27 11:50:27 +02:00
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ISim P.20160913 (signature 0xfbc00daa)
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Number of CPUs detected in this system: 1
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Turning on mult-threading, number of parallel sub-compilation jobs: 0
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2019-08-24 14:39:01 +02:00
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Determining compilation order of HDL files
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2019-08-30 19:24:54 +02:00
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/ShiftRight.vhd" into library work
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapter.vhd" into library work
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" into library work
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2019-08-24 14:39:01 +02:00
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Starting static elaboration
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2019-08-30 19:24:54 +02:00
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ERROR:HDLCompiler:410 - "/home/ise/gianni/IEEE754Adder/SumDataAdapterTest.vhd" Line 74: Expression has 30 elements ; expected 31
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ERROR:Simulator:777 - Static elaboration of top level VHDL design unit sumdataadaptertest in library work failed
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