55 lines
920 B
VHDL
55 lines
920 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity TwoComplement is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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DIFF_EXP_C2 : in std_logic_vector((BITCOUNT-1) downto 0);
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DIFF_EXP : out std_logic_vector((BITCOUNT-1) downto 0)
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);
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end TwoComplement;
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architecture TwoComplementArch of TwoComplement is
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signal SIGN : std_logic;
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signal DIFF_EXP_ABS : std_logic_vector((BITCOUNT-2) downto 0);
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begin
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SIGN <= DIFF_EXP_C2(BITCOUNT-1);
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C2_PROCESS : process(DIFF_EXP_C2, SIGN)
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begin
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for i in (BITCOUNT-2) downto 0 loop
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DIFF_EXP_ABS(i) <= SIGN xor DIFF_EXP_C2(i);
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end loop;
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end process;
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SUM : process(DIFF_EXP_ABS, SIGN)
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variable CARRY : std_logic;
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begin
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CARRY := SIGN;
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for i in 0 to (BITCOUNT-2) loop
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DIFF_EXP(i) <= DIFF_EXP_ABS(i) xor CARRY;
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CARRY := DIFF_EXP_ABS(i) and CARRY;
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end loop;
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DIFF_EXP(BITCOUNT-1) <= CARRY;
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end process;
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end TwoComplementArch;
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