37 lines
1000 B
VHDL
37 lines
1000 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Adder is
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generic( BITCOUNT: integer := 8 );
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port(
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X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
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carry_in: in std_logic;
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result: out std_logic_vector((BITCOUNT-1) downto 0);
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carry_out: out std_logic
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);
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end Adder;
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architecture CarryLookAheadArch of Adder is
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signal generation: std_logic_vector((BITCOUNT-1) downto 0);
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signal propagation: std_logic_vector((BITCOUNT-1) downto 0);
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signal carry: std_logic_vector((BITCOUNT-1) downto 0);
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signal sum_no_carry: std_logic_vector((BITCOUNT-1) downto 0);
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begin
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generation <= X and Y;
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propagation <= X or Y;
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sum_no_carry <= X xor Y;
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carry_look_ahead: process (generation, propagation, carry, carry_in)
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begin
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carry(0) <= carry_in;
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for i in (BITCOUNT-1) downto 1 loop
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carry(i) <= generation(i) or (propagation(i) and carry(i-1));
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end loop;
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end process;
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result <= sum_no_carry xor carry;
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carry_out <= sum_no_carry(BITCOUNT-1) xor carry(BITCOUNT-1);
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end CarryLookAheadArch;
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