80 lines
1.6 KiB
VHDL
80 lines
1.6 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY ZeroCounterTest IS
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END ZeroCounterTest;
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ARCHITECTURE behavior OF ZeroCounterTest IS
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COMPONENT ZeroCounter
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PORT(
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X : IN std_logic_vector(7 downto 0);
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Z_COUNT : OUT std_logic_vector(2 downto 0);
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ALL_ZEROS : OUT std_logic
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);
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END COMPONENT;
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--Inputs
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signal X : std_logic_vector(7 downto 0) := (others => '0');
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--Outputs
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signal Z_COUNT : std_logic_vector(2 downto 0);
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signal ALL_ZEROS : std_logic;
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constant clock_period : time := 10 ns;
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signal clock: std_logic;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: ZeroCounter PORT MAP (
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X => X,
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Z_COUNT => Z_COUNT,
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ALL_ZEROS => ALL_ZEROS
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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stim_proc: process
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begin
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X <= "00000000";
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wait for clock_period;
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X <= "00000001";
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wait for clock_period;
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X <= "00000010";
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wait for clock_period;
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X <= "00000100";
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wait for clock_period;
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X <= "00001000";
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wait for clock_period;
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X <= "00010000";
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wait for clock_period;
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X <= "00100000";
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wait for clock_period;
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X <= "01000000";
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wait for clock_period;
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X <= "10000000";
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wait for clock_period;
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X <= "00100110";
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wait for clock_period;
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X <= "11111111";
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wait for clock_period;
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X <= "01111111";
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wait for clock_period;
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X <= "00111111";
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wait for clock_period;
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X <= "00101111";
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wait for clock_period;
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end process;
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END;
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