89 lines
2.2 KiB
VHDL
89 lines
2.2 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY OutputSelectorTest IS
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END OutputSelectorTest;
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ARCHITECTURE behavior OF OutputSelectorTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT OutputSelector
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PORT(
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IS_NAN : IN std_logic;
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IS_ZERO : IN std_logic;
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IEEE_754_SUM : IN std_logic_vector(31 downto 0);
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RESULT : OUT std_logic_vector(31 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal IS_NAN : std_logic := '0';
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signal IS_ZERO : std_logic := '0';
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signal IEEE_754_SUM : std_logic_vector(31 downto 0) := (others => '0');
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--Outputs
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signal RESULT : std_logic_vector(31 downto 0);
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signal clock : std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: OutputSelector PORT MAP (
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IS_NAN => IS_NAN,
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IS_ZERO => IS_ZERO,
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IEEE_754_SUM => IEEE_754_SUM,
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RESULT => RESULT
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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test_proc: process
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begin
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IS_NAN <= '0';
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IS_ZERO <= '0';
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IEEE_754_SUM <= "0" & "00111000" & "00000100100010110000110";
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wait for clock_period;
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IS_NAN <= '0';
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IS_ZERO <= '0';
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IEEE_754_SUM <= "1" & "11000010" & "00000011110010111000000";
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wait for clock_period;
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IS_NAN <= '0';
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IS_ZERO <= '1';
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IEEE_754_SUM <= "0" & "00100111" & "01111111100000000000000";
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wait for clock_period;
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IS_NAN <= '0';
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IS_ZERO <= '1';
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IEEE_754_SUM <= "1" & "00000010" & "01110000000000000000111";
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wait for clock_period;
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IS_NAN <= '1';
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IS_ZERO <= '0';
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IEEE_754_SUM <= "0" & "11111111" & "00000000000000000000000";
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wait for clock_period;
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IS_NAN <= '1';
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IS_ZERO <= '0';
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IEEE_754_SUM <= "1" & "00001111" & "10000000000000111100000";
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wait for clock_period;
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IS_NAN <= '1';
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IS_ZERO <= '1';
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IEEE_754_SUM <= "0" & "00110000" & "00000000111000000000011";
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wait for clock_period;
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IS_NAN <= '1';
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IS_ZERO <= '1';
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IEEE_754_SUM <= "1" & "11111111" & "00110011001100110011100";
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wait for clock_period;
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end process;
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END;
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