66 lines
1.4 KiB
VHDL
66 lines
1.4 KiB
VHDL
LIBRARY ieee;
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USE ieee.std_logic_1164.ALL;
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ENTITY TwoComplementTest IS
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END TwoComplementTest;
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ARCHITECTURE behavior OF TwoComplementTest IS
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-- Component Declaration for the Unit Under Test (UUT)
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COMPONENT TwoComplement
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PORT(
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DIFF_EXP_C2 : IN std_logic_vector(7 downto 0);
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DIFF_EXP : OUT std_logic_vector(7 downto 0)
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);
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END COMPONENT;
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--Inputs
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signal DIFF_EXP_C2 : std_logic_vector(7 downto 0) := (others => '0');
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--Outputs
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signal DIFF_EXP : std_logic_vector(7 downto 0);
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signal clock : std_logic;
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constant clock_period : time := 10 ns;
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BEGIN
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-- Instantiate the Unit Under Test (UUT)
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uut: TwoComplement PORT MAP (
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DIFF_EXP_C2 => DIFF_EXP_C2,
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DIFF_EXP => DIFF_EXP
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);
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-- Clock process definitions
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clock_process :process
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begin
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clock <= '0';
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wait for clock_period/2;
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clock <= '1';
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wait for clock_period/2;
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end process;
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test_process :process
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begin
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DIFF_EXP_C2 <= "01001110";
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wait for clock_period;
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DIFF_EXP_C2 <= "11111111";
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wait for clock_period;
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DIFF_EXP_C2 <= "10000000";
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wait for clock_period;
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DIFF_EXP_C2 <= "01111111";
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wait for clock_period;
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DIFF_EXP_C2 <= "01100101";
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wait for clock_period;
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DIFF_EXP_C2 <= "10011101";
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wait for clock_period;
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DIFF_EXP_C2 <= "11100010";
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wait for clock_period;
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DIFF_EXP_C2 <= "10010011";
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wait for clock_period;
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end process;
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END;
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