54 lines
1.1 KiB
VHDL
54 lines
1.1 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity Adder is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
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CARRY_IN : in std_logic;
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RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
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CARRY_OUT : out std_logic
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);
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end Adder;
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architecture CarryLookAheadArch of Adder is
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signal GENERATION : std_logic_vector((BITCOUNT-1) downto 0);
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signal PROPAGATION : std_logic_vector((BITCOUNT-1) downto 0);
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signal CARRY : std_logic_vector((BITCOUNT-1) downto 0);
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signal SUM_NO_CARRY : std_logic_vector((BITCOUNT-1) downto 0);
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begin
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GENERATION <= X and Y;
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PROPAGATION <= X or Y;
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SUM_NO_CARRY <= X xor Y;
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CARRY_LOOK_AHEAD_PROCESS : process (GENERATION, PROPAGATION, CARRY_IN)
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variable C : std_logic;
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begin
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C := CARRY_IN;
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CARRY(0) <= C;
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for i in 1 to (BITCOUNT-1) loop
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C := GENERATION(i-1) or (PROPAGATION(i-1) and C);
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CARRY(i) <= C;
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end loop;
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end process;
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RESULT <= SUM_NO_CARRY xor CARRY;
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CARRY_OUT <= (X(BITCOUNT-1) and Y(BITCOUNT-1)) or (X(BITCOUNT-1) and CARRY(BITCOUNT-1)) or (CARRY(BITCOUNT-1) and Y(BITCOUNT-1));
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end CarryLookAheadArch;
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