43 lines
996 B
VHDL
43 lines
996 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity AddSub is
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generic( BITCOUNT: integer := 8 );
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port(
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X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
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isSub: in std_logic := '0';
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result: out std_logic_vector((BITCOUNT-1) downto 0);
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overflow: out std_logic
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);
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end AddSub;
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architecture AddSubArch of AddSub is
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component Adder is
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generic( BITCOUNT: integer := 8 );
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port(
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X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
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carry_in: in std_logic;
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result: out std_logic_vector((BITCOUNT-1) downto 0);
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carry_out: out std_logic
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);
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end component;
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signal Y2: std_logic_vector((BITCOUNT-1) downto 0);
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signal C_out: std_logic;
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begin
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y2proc: process(Y, isSub)
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begin
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for i in Y2'range loop
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Y2(i) <= Y(i) xor isSub;
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end loop;
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end process;
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ADD: Adder
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generic map ( BITCOUNT => BITCOUNT )
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port map ( X => X, Y => Y2, carry_in => isSub, result => result, carry_out => C_out );
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overflow <= ((not isSub) and C_out) or (isSub and (not C_out));
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end AddSubArch;
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