22 lines
1.1 KiB
Plaintext
22 lines
1.1 KiB
Plaintext
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/OutputSelectorTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/OutputSelectorTest_beh.prj work.OutputSelectorTest
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ISim P.20160913 (signature 0xfbc00daa)
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Number of CPUs detected in this system: 1
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Turning on mult-threading, number of parallel sub-compilation jobs: 0
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Determining compilation order of HDL files
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/OutputSelector.vhd" into library work
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Parsing VHDL file "/home/ise/gianni/IEEE754Adder/OutputSelectorTest.vhd" into library work
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Starting static elaboration
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Completed static elaboration
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Fuse Memory Usage: 95300 KB
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Fuse CPU Usage: 2310 ms
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Compiling package standard
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Compiling package std_logic_1164
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Compiling architecture outputselectorarch of entity OutputSelector [outputselector_default]
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Compiling architecture behavior of entity outputselectortest
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Time Resolution for simulation is 1ps.
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Compiled 5 VHDL Units
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Built simulation executable /home/ise/gianni/IEEE754Adder/OutputSelectorTest_isim_beh.exe
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Fuse Memory Usage: 103948 KB
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Fuse CPU Usage: 2410 ms
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GCC CPU Usage: 550 ms
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