65 lines
1.2 KiB
VHDL
65 lines
1.2 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity PipelineStageThree is
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port(
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RES_SIGN : in std_logic;
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EXP : in std_logic_vector(7 downto 0);
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MANT : in std_logic_vector(47 downto 0);
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MANT_OF : in std_logic;
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IS_NAN, IS_ZERO : in std_logic;
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FINAL_RES : out std_logic_vector(31 downto 0)
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);
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end PipelineStageThree;
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architecture StageThreeArch of PipelineStageThree is
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component Normalizer is
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port(
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SIGN : in std_logic;
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EXP : in std_logic_vector(7 downto 0);
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MANT : in std_logic_vector(47 downto 0);
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SUM_OVERFLOW : in std_logic;
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IEEE_754_SUM : out std_logic_vector(31 downto 0)
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);
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end component;
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component OutputSelector is
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port(
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IS_NAN : in std_logic;
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IS_ZERO : in std_logic;
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IEEE_754_SUM : in std_logic_vector(31 downto 0);
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RESULT : out std_logic_vector(31 downto 0)
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);
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end component;
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signal NORMALIZED : std_logic_vector(31 downto 0);
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begin
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N : Normalizer
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port map (
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SIGN => RES_SIGN,
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EXP => EXP,
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MANT => MANT,
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SUM_OVERFLOW => MANT_OF,
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IEEE_754_SUM => NORMALIZED
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);
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OS : OutputSelector
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port map (
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IS_NAN => IS_NAN,
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IS_ZERO => IS_ZERO,
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IEEE_754_SUM => NORMALIZED,
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RESULT => FINAL_RES
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);
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end StageThreeArch;
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