46 lines
828 B
VHDL
46 lines
828 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity NaNCheck is
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port(
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X, Y : in std_logic_vector(31 downto 0);
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IS_NAN : out std_logic
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);
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end NaNCheck;
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architecture NaNCheckArch of NaNCheck is
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component TypeCheck is
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port(
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N : in std_logic_vector(31 downto 0);
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NAN, INF : out std_logic
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);
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end component;
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signal X_NAN : std_logic;
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signal X_INF : std_logic;
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signal X_SIGN : std_logic;
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signal Y_NAN : std_logic;
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signal Y_INF : std_logic;
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signal Y_SIGN : std_logic;
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begin
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xCheck: TypeCheck
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port map (N => X, NAN => X_NAN, INF => X_INF);
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yCheck: TypeCheck
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port map (N => Y, NAN => Y_NAN, INF => Y_INF);
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X_SIGN <= X(31);
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Y_SIGN <= Y(31);
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IS_NAN <= X_NAN or Y_NAN or (X_INF and X_SIGN and Y_INF and (not Y_SIGN)) or (X_INF and (not X_SIGN) and Y_INF and Y_SIGN);
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end NaNCheckArch;
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