33 lines
634 B
VHDL
33 lines
634 B
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity EqualCheck is
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generic(
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BITCOUNT: integer := 8
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);
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port(
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X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
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IS_EQUAL : out std_logic
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);
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end EqualCheck;
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architecture EqualCheckArch of EqualCheck is
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signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
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begin
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COMP_VEC <= X xor Y;
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RES_COMPUTE: process (COMP_VEC)
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variable RES_TMP : std_logic;
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begin
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RES_TMP := '0';
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for i in COMP_VEC'range loop
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RES_TMP := RES_TMP or COMP_VEC(i);
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end loop;
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IS_EQUAL <= not RES_TMP;
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end process;
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end EqualCheckArch;
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