59 lines
1.0 KiB
VHDL
59 lines
1.0 KiB
VHDL
library IEEE;
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use IEEE.STD_LOGIC_1164.ALL;
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entity AddSub is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
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IS_SUB : in std_logic := '0';
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RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
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OVERFLOW : out std_logic
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);
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end AddSub;
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architecture AddSubArch of AddSub is
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component Adder is
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generic(
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BITCOUNT : integer := 8
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);
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port(
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X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
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CARRY_IN : in std_logic;
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RESULT : out std_logic_vector((BITCOUNT-1) downto 0);
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CARRY_OUT : out std_logic
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);
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end component;
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signal Y2 : std_logic_vector((BITCOUNT-1) downto 0);
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signal C_OUT : std_logic;
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begin
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Y2_PROCESS : process(Y, IS_SUB)
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begin
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for i in Y2'range loop
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Y2(i) <= Y(i) xor IS_SUB;
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end loop;
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end process;
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ADD : Adder
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generic map (BITCOUNT => BITCOUNT)
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port map (X => X, Y => Y2, CARRY_IN => IS_SUB, RESULT => RESULT, CARRY_OUT => C_OUT);
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OVERFLOW <= ((not IS_SUB) and C_OUT) or (IS_SUB and (not C_OUT));
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end AddSubArch;
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