| SpecialCasesCheck Project Status (08/24/2019 - 12:12:36) | |||
| Project File: | IEEE754Adder.xise | Parser Errors: | No Errors |
| Module Name: | equalCheck | Implementation State: | Placed and Routed |
| Target Device: | xa6slx4-3csg225 |
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| Product Version: | ISE 14.7 |
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| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice LUTs | 4 | 2400 | 0% | |
| Number of fully used LUT-FF pairs | 0 | 4 | 0% | |
| Number of bonded IOBs | 17 | 132 | 12% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Sat Aug 24 10:22:02 2019 | ||||
| Translation Report | ||||||
| Map Report | ||||||
| Place and Route Report | ||||||
| CPLD Fitter Report (Text) | ||||||
| Power Report | ||||||
| Post-PAR Static Timing Report | ||||||
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |
| ISIM Simulator Log | Out of Date | Sat Aug 24 12:11:57 2019 | |
| Post-Synthesis Simulation Model Report | Out of Date | Sat Aug 24 10:53:07 2019 | |
| WebTalk Report | Out of Date | Sat Aug 24 10:52:31 2019 | |
| WebTalk Log File | Out of Date | Sat Aug 24 10:52:32 2019 | |