| TypeCheck Project Status (08/17/2019 - 16:39:36) | |||
| Project File: | IEEE754Adder.xise | Parser Errors: | No Errors |
| Module Name: | TypeCheck | Implementation State: | Synthesized |
| Target Device: | xa6slx4-3csg225 |
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No Errors |
| Product Version: | ISE 14.7 |
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1 Warning (1 new) |
| Design Goal: | Balanced |
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| Design Strategy: | Xilinx Default (unlocked) |
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| Environment: | System Settings |
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| Device Utilization Summary (estimated values) | [-] | |||
| Logic Utilization | Used | Available | Utilization | |
| Number of Slice LUTs | 9 | 2400 | 0% | |
| Number of fully used LUT-FF pairs | 0 | 9 | 0% | |
| Number of bonded IOBs | 33 | 132 | 25% | |
| Detailed Reports | [-] | |||||
| Report Name | Status | Generated | Errors | Warnings | Infos | |
| Synthesis Report | Current | Sat Aug 17 16:39:35 2019 | 0 | 1 Warning (1 new) | 0 | |
| Translation Report | Out of Date | Sat Aug 17 16:35:26 2019 | 0 | 0 | 0 | |
| Map Report | Out of Date | Sat Aug 17 16:35:26 2019 | 0 | 0 | 4 Infos (0 new) | |
| Place and Route Report | Out of Date | Sat Aug 17 16:35:26 2019 | 0 | 0 | 1 Info (0 new) | |
| Power Report | ||||||
| Post-PAR Static Timing Report | Out of Date | Sat Aug 17 16:35:26 2019 | 0 | 0 | 6 Infos (0 new) | |
| Bitgen Report | ||||||
| Secondary Reports | [-] | ||
| Report Name | Status | Generated | |