Release 14.7 - xst P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. --> Parameter TMPDIR set to xst/projnav.tmp Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.05 secs --> Parameter xsthdpdir set to xst Total REAL time to Xst completion: 0.00 secs Total CPU time to Xst completion: 0.05 secs --> Reading design: SpecialCasesCheck.prj TABLE OF CONTENTS 1) Synthesis Options Summary 2) HDL Compilation 3) Design Hierarchy Analysis 4) HDL Analysis 5) HDL Synthesis 5.1) HDL Synthesis Report 6) Advanced HDL Synthesis 6.1) Advanced HDL Synthesis Report 7) Low Level Synthesis 8) Partition Report 9) Final Report 9.1) Device utilization summary 9.2) Partition Resource Summary 9.3) TIMING REPORT ========================================================================= * Synthesis Options Summary * ========================================================================= ---- Source Parameters Input File Name : "SpecialCasesCheck.prj" Input Format : mixed Ignore Synthesis Constraint File : NO ---- Target Parameters Output File Name : "SpecialCasesCheck" Output Format : NGC Target Device : xc3s50-5-pq208 ---- Source Options Top Module Name : SpecialCasesCheck Automatic FSM Extraction : YES FSM Encoding Algorithm : Auto Safe Implementation : No FSM Style : LUT RAM Extraction : Yes RAM Style : Auto ROM Extraction : Yes Mux Style : Auto Decoder Extraction : YES Priority Encoder Extraction : Yes Shift Register Extraction : YES Logical Shifter Extraction : YES XOR Collapsing : YES ROM Style : Auto Mux Extraction : Yes Resource Sharing : YES Asynchronous To Synchronous : NO Multiplier Style : Auto Automatic Register Balancing : No ---- Target Options Add IO Buffers : YES Global Maximum Fanout : 500 Add Generic Clock Buffer(BUFG) : 8 Register Duplication : YES Slice Packing : YES Optimize Instantiated Primitives : NO Use Clock Enable : Yes Use Synchronous Set : Yes Use Synchronous Reset : Yes Pack IO Registers into IOBs : Auto Equivalent register Removal : YES ---- General Options Optimization Goal : Speed Optimization Effort : 1 Keep Hierarchy : No Netlist Hierarchy : As_Optimized RTL Output : Yes Global Optimization : AllClockNets Read Cores : YES Write Timing Constraints : NO Cross Clock Analysis : NO Hierarchy Separator : / Bus Delimiter : <> Case Specifier : Maintain Slice Utilization Ratio : 100 BRAM Utilization Ratio : 100 Verilog 2001 : YES Auto BRAM Packing : NO Slice Utilization Ratio Delta : 5 ========================================================================= ========================================================================= * HDL Compilation * ========================================================================= Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" in Library work. Architecture typecheckarch of Entity typecheck is up to date. Compiling vhdl file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" in Library work. Entity compiled. Entity (Architecture ) compiled. ========================================================================= * Design Hierarchy Analysis * ========================================================================= Analyzing hierarchy for entity in library (architecture ). Analyzing hierarchy for entity in library (architecture ). ========================================================================= * HDL Analysis * ========================================================================= Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. Analyzing Entity in library (Architecture ). Entity analyzed. Unit generated. ========================================================================= * HDL Synthesis * ========================================================================= Performing bidirectional port resolution... Synthesizing Unit . Related source file is "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd". WARNING:Xst:647 - Input > is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved. Unit synthesized. Synthesizing Unit . Related source file is "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd". Unit synthesized. ========================================================================= HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Advanced HDL Synthesis * ========================================================================= ========================================================================= Advanced HDL Synthesis Report Found no macro ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit ... Mapping all equations... Building and optimizing final netlist ... Found area constraint ratio of 100 (+ 5) on block SpecialCasesCheck, actual ratio is 1. Final Macro Processing ... ========================================================================= Final Register Report Found no macro ========================================================================= ========================================================================= * Partition Report * ========================================================================= Partition Implementation Status ------------------------------- No Partitions were found in this design. ------------------------------- ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : SpecialCasesCheck.ngr Top Level Output File Name : SpecialCasesCheck Output Format : NGC Optimization Goal : Speed Keep Hierarchy : No Design Statistics # IOs : 66 Cell Usage : # BELS : 24 # GND : 1 # LUT2 : 1 # LUT3 : 2 # LUT4 : 20 # IO Buffers : 66 # IBUF : 64 # OBUF : 2 ========================================================================= Device utilization summary: --------------------------- Selected Device : 3s50pq208-5 Number of Slices: 13 out of 768 1% Number of 4 input LUTs: 23 out of 1536 1% Number of IOs: 66 Number of bonded IOBs: 66 out of 124 53% --------------------------- Partition Resource Summary: --------------------------- No Partitions were found in this design. --------------------------- ========================================================================= TIMING REPORT NOTE: THESE TIMING NUMBERS ARE ONLY A SYNTHESIS ESTIMATE. FOR ACCURATE TIMING INFORMATION PLEASE REFER TO THE TRACE REPORT GENERATED AFTER PLACE-and-ROUTE. Clock Information: ------------------ No clock signals found in this design Asynchronous Control Signals Information: ---------------------------------------- No asynchronous control signals found in this design Timing Summary: --------------- Speed Grade: -5 Minimum period: No path found Minimum input arrival time before clock: No path found Maximum output required time after clock: No path found Maximum combinational path delay: 13.307ns Timing Detail: -------------- All values displayed in nanoseconds (ns) ========================================================================= Timing constraint: Default path analysis Total number of paths / destination ports: 72 / 1 ------------------------------------------------------------------------- Delay: 13.307ns (Levels of Logic = 7) Source: Y<8> (PAD) Destination: isNan (PAD) Data Path: Y<8> to isNan Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) ---------------------------------------- ------------ IBUF:I->O 1 0.715 0.976 Y_8_IBUF (Y_8_IBUF) LUT4:I0->O 1 0.479 0.976 isNan35 (isNan35) LUT2:I0->O 1 0.479 0.704 isNan41 (isNan41) LUT4:I3->O 1 0.479 0.976 isNan61 (isNan61) LUT3:I0->O 1 0.479 0.976 isNan209_SW0 (N6) LUT4:I0->O 1 0.479 0.681 isNan209 (isNan_OBUF) OBUF:I->O 4.909 isNan_OBUF (isNan) ---------------------------------------- Total 13.307ns (8.019ns logic, 5.288ns route) (60.3% logic, 39.7% route) ========================================================================= Total REAL time to Xst completion: 3.00 secs Total CPU time to Xst completion: 3.05 secs --> Total memory usage is 606300 kilobytes Number of errors : 0 ( 0 filtered) Number of warnings : 1 ( 0 filtered) Number of infos : 0 ( 0 filtered)