]> Release 14.7 Trace (lin64)Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved./opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/trce -intstyle ise -v 3 -s 5 -n 3 -fastpaths -xml TypeCheck.twx TypeCheck.ncd -o TypeCheck.twr TypeCheck.pcf TypeCheck.ncdTypeCheck.ncdTypeCheck.pcfTypeCheck.pcfxc3s50-5PRODUCTION 1.39 2013-10-133INFO:Timing:2698 - No timing constraints found, doing default enumeration.INFO:Timing:3412 - To improve timing, see the Timing Closure User Guide (UG612).INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report.INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet.INFO:Timing:3390 - This architecture does not support a default System Jitter value, please add SYSTEM_JITTER constraint to the UCF to modify the Clock Uncertainty calculation.INFO:Timing:3389 - This architecture does not support 'Discrete Jitter' and 'Phase Error' calculations, these terms will be zero in the Clock Uncertainty calculation. Please make appropriate modification to SYSTEM_JITTER to account for the unsupported Discrete Jitter and Phase Error.N<0>INF7.509N<0>NaN7.466N<23>INF7.017N<23>NaN7.274Sat Aug 17 16:41:03 2019 TraceTrace Settings Peak Memory Usage: 309 MB