SpecialCasesCheck Project Status (08/17/2019 - 17:19:45)
Project File: IEEE754Adder.xise Parser Errors: No Errors
Module Name: SpecialCasesCheck Implementation State: Synthesized
Target Device: xa6slx4-3csg225
  • Errors:
 No Errors
Product Version:ISE 14.7
  • Warnings:
 1 Warning (1 new)
Design Goal: Balanced
  • Routing Results:
  
Design Strategy: Xilinx Default (unlocked)
  • Timing Constraints:
  
Environment: System Settings
  • Final Timing Score:
   
 
Device Utilization Summary (estimated values) [-]
Logic UtilizationUsedAvailableUtilization
Number of Slice LUTs 15 2400 0%
Number of fully used LUT-FF pairs 0 15 0%
Number of bonded IOBs 66 132 50%
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentSat Aug 17 17:19:45 201901 Warning (1 new)0
Translation Report     
Map Report     
Place and Route Report     
Power Report     
Post-PAR Static Timing Report     
Bitgen Report     
 
Secondary Reports [-]
Report NameStatusGenerated

Date Generated: 08/17/2019 - 17:19:45