From a91e1252d096f09209a76c5998b47321923b51dd Mon Sep 17 00:00:00 2001 From: Luca Cuzzocrea Date: Wed, 28 Aug 2019 21:50:05 +0200 Subject: [PATCH] Sommatore 1 --- AddSub.vhd | 20 + Adder.vhd | 36 + AdderTest.vhd | 90 + AdderTest_isim_beh.exe | Bin 0 -> 21792 bytes AdderTest_isim_beh.wdb | Bin 0 -> 6399 bytes IEEE754Adder.xise | 54 +- SpecialCasesCheck.ucf | 0 SpecialCasesCheck.vhd | 2 +- SpecialCasesCheck.xdl | Bin 0 -> 6582 bytes SpecialCasesCheck_isim_beh.exe | Bin 0 -> 21792 bytes fuse.log | 32 +- fuseRelaunch.cmd | 2 +- isim.log | 2 +- .../AdderTest_isim_beh.exe | Bin 0 -> 50451 bytes .../ISimEngine-DesignHierarchy.dbg | Bin 0 -> 5076 bytes isim/AdderTest_isim_beh.exe.sim/isimcrash.log | 0 .../AdderTest_isim_beh.exe.sim/isimkernel.log | 29 + isim/AdderTest_isim_beh.exe.sim/netId.dat | Bin 0 -> 84 bytes isim/AdderTest_isim_beh.exe.sim/tmp_save/_1 | Bin 0 -> 2802 bytes .../work/AdderTest_isim_beh.exe_main.c | 40 + .../work/AdderTest_isim_beh.exe_main.lin64.o | Bin 0 -> 2768 bytes .../work/a_3841309559_2737618828.c | 462 +++++ .../work/a_3841309559_2737618828.didat | Bin 0 -> 4928 bytes .../work/a_3841309559_2737618828.lin64.o | Bin 0 -> 6488 bytes .../work/a_4008929629_2372691052.c | 154 ++ .../work/a_4008929629_2372691052.didat | Bin 0 -> 4312 bytes .../work/a_4008929629_2372691052.lin64.o | Bin 0 -> 3792 bytes .../ISimEngine-DesignHierarchy.dbg | Bin 0 -> 8588 bytes .../SpecialCasesCheck_isim_beh.exe | Bin 0 -> 55073 bytes .../isimcrash.log | 0 .../isimkernel.log | 29 + .../netId.dat | Bin 0 -> 52 bytes .../tmp_save/_1 | Bin 0 -> 8136 bytes .../SpecialCasesCheck_isim_beh.exe_main.c | 43 + ...pecialCasesCheck_isim_beh.exe_main.lin64.o | Bin 0 -> 3048 bytes .../work/a_0557987184_1272247069.c | 368 ++++ .../work/a_0557987184_1272247069.didat | Bin 0 -> 4632 bytes .../work/a_0557987184_1272247069.lin64.o | Bin 0 -> 5512 bytes .../work/a_1540508602_4151211736.c | 278 +++ .../work/a_1540508602_4151211736.didat | Bin 0 -> 5160 bytes .../work/a_1540508602_4151211736.lin64.o | Bin 0 -> 4888 bytes .../work/a_1684417184_3395701438.c | 31 + .../work/a_1684417184_3395701438.didat | Bin 0 -> 3668 bytes .../work/a_1684417184_3395701438.lin64.o | Bin 0 -> 1880 bytes .../work/a_2347761600_1146481140.c | 180 ++ .../work/a_2347761600_1146481140.didat | Bin 0 -> 3488 bytes .../work/a_2347761600_1146481140.lin64.o | Bin 0 -> 4144 bytes .../work/a_3914402253_2628201599.c | 221 +++ .../work/a_3914402253_2628201599.didat | Bin 0 -> 5044 bytes .../work/a_3914402253_2628201599.lin64.o | Bin 0 -> 4352 bytes .../ISimEngine-DesignHierarchy.dbg | Bin 9797 -> 9797 bytes .../isimkernel.log | 8 +- .../work/a_0557987184_1272247069.didat | Bin 4632 -> 4632 bytes .../work/a_1540508602_4151211736.didat | Bin 5160 -> 5160 bytes .../work/a_2347761600_1146481140.didat | Bin 3488 -> 3488 bytes .../work/a_2912948712_3395701438.didat | Bin 3692 -> 3692 bytes .../work/a_3914402253_2628201599.didat | Bin 5036 -> 5036 bytes .../work/a_4189535622_2372691052.didat | Bin 6500 -> 6500 bytes isim/isim_usage_statistics.html | 12 +- .../ieee/p_2592010699.didat | Bin 5868 -> 5868 bytes isim/temp/adder.vdb | Bin 0 -> 5106 bytes isim/temp/addertest.vdb | Bin 0 -> 4653 bytes isim/work/adder.vdb | Bin 0 -> 5356 bytes isim/work/addertest.vdb | Bin 0 -> 4648 bytes pa.fromNcd.tcl | 15 + planAhead.ngc2edif.log | 12 + planAhead_pid7025.debug | 92 + .../cache/SpecialCasesCheck_ngc_ec4f3bca.edif | 1762 +++++++++++++++++ .../IEEE754Adder.data/constrs_1/fileset.xml | 16 + .../IEEE754Adder.data/runs/impl_1.psg | 20 + .../IEEE754Adder.data/runs/runs.xml | 5 + .../IEEE754Adder.data/sim_1/fileset.xml | 10 + .../IEEE754Adder.data/sources_1/fileset.xml | 30 + .../wt/java_command_handlers.wdf | 3 + .../IEEE754Adder.data/wt/project.wpc | 4 + .../IEEE754Adder.data/wt/webtalk_pa.xml | 29 + planAhead_run_1/IEEE754Adder.ppr | 28 + planAhead_run_1/planAhead.jou | 10 + planAhead_run_1/planAhead.log | 83 + planAhead_run_1/planAhead_run.log | 74 + 80 files changed, 4236 insertions(+), 50 deletions(-) create mode 100644 AddSub.vhd create mode 100644 Adder.vhd create mode 100644 AdderTest.vhd create mode 100755 AdderTest_isim_beh.exe create mode 100644 AdderTest_isim_beh.wdb create mode 100644 SpecialCasesCheck.ucf create mode 100644 SpecialCasesCheck.xdl create mode 100755 SpecialCasesCheck_isim_beh.exe create mode 100755 isim/AdderTest_isim_beh.exe.sim/AdderTest_isim_beh.exe create mode 100644 isim/AdderTest_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg create mode 100644 isim/AdderTest_isim_beh.exe.sim/isimcrash.log create mode 100644 isim/AdderTest_isim_beh.exe.sim/isimkernel.log create mode 100644 isim/AdderTest_isim_beh.exe.sim/netId.dat create mode 100644 isim/AdderTest_isim_beh.exe.sim/tmp_save/_1 create mode 100644 isim/AdderTest_isim_beh.exe.sim/work/AdderTest_isim_beh.exe_main.c create mode 100644 isim/AdderTest_isim_beh.exe.sim/work/AdderTest_isim_beh.exe_main.lin64.o create mode 100644 isim/AdderTest_isim_beh.exe.sim/work/a_3841309559_2737618828.c create mode 100644 isim/AdderTest_isim_beh.exe.sim/work/a_3841309559_2737618828.didat create mode 100644 isim/AdderTest_isim_beh.exe.sim/work/a_3841309559_2737618828.lin64.o create mode 100644 isim/AdderTest_isim_beh.exe.sim/work/a_4008929629_2372691052.c create mode 100644 isim/AdderTest_isim_beh.exe.sim/work/a_4008929629_2372691052.didat create mode 100644 isim/AdderTest_isim_beh.exe.sim/work/a_4008929629_2372691052.lin64.o create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg create mode 100755 isim/SpecialCasesCheck_isim_beh.exe.sim/SpecialCasesCheck_isim_beh.exe create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/isimcrash.log create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/isimkernel.log create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/netId.dat create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/tmp_save/_1 create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/SpecialCasesCheck_isim_beh.exe_main.c create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/SpecialCasesCheck_isim_beh.exe_main.lin64.o create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.c create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.didat create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.lin64.o create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1540508602_4151211736.c create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1540508602_4151211736.didat create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1540508602_4151211736.lin64.o create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.c create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.didat create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.lin64.o create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_2347761600_1146481140.c create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_2347761600_1146481140.didat create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_2347761600_1146481140.lin64.o create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_3914402253_2628201599.c create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_3914402253_2628201599.didat create mode 100644 isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_3914402253_2628201599.lin64.o create mode 100644 isim/temp/adder.vdb create mode 100644 isim/temp/addertest.vdb create mode 100644 isim/work/adder.vdb create mode 100644 isim/work/addertest.vdb create mode 100644 pa.fromNcd.tcl create mode 100644 planAhead.ngc2edif.log create mode 100644 planAhead_pid7025.debug create mode 100644 planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif create mode 100644 planAhead_run_1/IEEE754Adder.data/constrs_1/fileset.xml create mode 100644 planAhead_run_1/IEEE754Adder.data/runs/impl_1.psg create mode 100644 planAhead_run_1/IEEE754Adder.data/runs/runs.xml create mode 100644 planAhead_run_1/IEEE754Adder.data/sim_1/fileset.xml create mode 100644 planAhead_run_1/IEEE754Adder.data/sources_1/fileset.xml create mode 100644 planAhead_run_1/IEEE754Adder.data/wt/java_command_handlers.wdf create mode 100644 planAhead_run_1/IEEE754Adder.data/wt/project.wpc create mode 100644 planAhead_run_1/IEEE754Adder.data/wt/webtalk_pa.xml create mode 100644 planAhead_run_1/IEEE754Adder.ppr create mode 100644 planAhead_run_1/planAhead.jou create mode 100644 planAhead_run_1/planAhead.log create mode 100644 planAhead_run_1/planAhead_run.log diff --git a/AddSub.vhd b/AddSub.vhd new file mode 100644 index 0000000..e792fe8 --- /dev/null +++ b/AddSub.vhd @@ -0,0 +1,20 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity AddSub is + generic( BITCOUNT: integer := 8 ); + port( + X, Y: in std_logic_vector((BITCOUNT-1) downto 0); + isSub: in std_logic := 0; + result: out std_logic_vector((BITCOUNT-1) downto 0) + ); +end AddSub; + +architecture CLAAddSubArch of AddSub is + +begin + + +end CLAAddSubArch; + diff --git a/Adder.vhd b/Adder.vhd new file mode 100644 index 0000000..783f011 --- /dev/null +++ b/Adder.vhd @@ -0,0 +1,36 @@ +library IEEE; +use IEEE.STD_LOGIC_1164.ALL; + + +entity Adder is + generic( BITCOUNT: integer := 8 ); + port( + X, Y: in std_logic_vector((BITCOUNT-1) downto 0); + carry_in: in std_logic; + result: out std_logic_vector((BITCOUNT-1) downto 0); + carry_out: out std_logic + ); +end Adder; + +architecture CarryLookAheadArch of Adder is + signal generation: std_logic_vector((BITCOUNT-1) downto 0); + signal propagation: std_logic_vector((BITCOUNT-1) downto 0); + signal carry: std_logic_vector((BITCOUNT-1) downto 0); + signal sum_no_carry: std_logic_vector((BITCOUNT-1) downto 0); +begin + generation <= X and Y; + propagation <= X or Y; + sum_no_carry <= X xor Y; + + carry_look_ahead: process (generation, propagation, carry, carry_in) + begin + carry(0) <= carry_in; + for i in (BITCOUNT-1) downto 1 loop + carry(i) <= generation(i) or (propagation(i) and carry(i-1)); + end loop; + end process; + + result <= sum_no_carry xor carry; + carry_out <= sum_no_carry(BITCOUNT-1) xor carry(BITCOUNT-1); +end CarryLookAheadArch; + diff --git a/AdderTest.vhd b/AdderTest.vhd new file mode 100644 index 0000000..ae199c6 --- /dev/null +++ b/AdderTest.vhd @@ -0,0 +1,90 @@ +-------------------------------------------------------------------------------- +-- Company: +-- Engineer: +-- +-- Create Date: 17:01:26 08/24/2019 +-- Design Name: +-- Module Name: /home/Luca/ISE/IEEE754Adder/AdderTest.vhd +-- Project Name: IEEE754Adder +-- Target Device: +-- Tool versions: +-- Description: +-- +-- VHDL Test Bench Created by ISE for module: Adder +-- +-- Dependencies: +-- +-- Revision: +-- Revision 0.01 - File Created +-- Additional Comments: +-- +-- Notes: +-- This testbench has been automatically generated using types std_logic and +-- std_logic_vector for the ports of the unit under test. Xilinx recommends +-- that these types always be used for the top-level I/O of a design in order +-- to guarantee that the testbench will bind correctly to the post-implementation +-- simulation model. +-------------------------------------------------------------------------------- +LIBRARY ieee; +USE ieee.std_logic_1164.ALL; + +-- Uncomment the following library declaration if using +-- arithmetic functions with Signed or Unsigned values +--USE ieee.numeric_std.ALL; + +ENTITY AdderTest IS +END AdderTest; + +ARCHITECTURE behavior OF AdderTest IS + + -- Component Declaration for the Unit Under Test (UUT) + + COMPONENT Adder + PORT( + X : IN std_logic_vector(7 downto 0); + Y : IN std_logic_vector(7 downto 0); + carry_in : IN std_logic; + result : OUT std_logic_vector(7 downto 0); + carry_out : OUT std_logic + ); + END COMPONENT; + + + --Inputs + signal X : std_logic_vector(7 downto 0) := (others => '0'); + signal Y : std_logic_vector(7 downto 0) := (others => '0'); + signal carry_in : std_logic := '0'; + + --Outputs + signal result : std_logic_vector(7 downto 0); + signal carry_out : std_logic; + -- No clocks detected in port list. Replace clock below with + -- appropriate port name + signal clock: std_logic; + + constant clock_period : time := 10 ns; + +BEGIN + + -- Instantiate the Unit Under Test (UUT) + uut: Adder PORT MAP ( + X => X, + Y => Y, + carry_in => carry_in, + result => result, + carry_out => carry_out + ); + + -- Clock process definitions + clock_process :process + begin + clock <= '0'; + wait for clock_period/2; + clock <= '1'; + wait for clock_period/2; + end process; + + x <= "00010101"; + y <= "00001110"; + +END; diff --git a/AdderTest_isim_beh.exe b/AdderTest_isim_beh.exe new file mode 100755 index 0000000000000000000000000000000000000000..3209988d8d84424c4d5c423f8f5aaa98e3cf50c8 GIT binary patch literal 21792 zcmeHPe|%KcmB0A~DTPcx(C|Zf!k{2#NHC#EOmHSMkvDe02*F|(of#&RWHgzH^8mpFAK}b^6wo27n6~*6g1Qe^Kh}PNfx$oZOG2(VV zOaC)BpZCs>d(OG%p8Mn7d*7Sf(%`u~Hz$Y5l*^VfqLdOlXBl_Kd@DF9cvY;B+1X4s zgN*~H0GFNT5Hv6e2ZU(}3x!-BU_Rlwf{|-C5CLZy6q8VTNRY}KO?H7A@L54hh??+x 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0 HcmV?d00001 diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise index 0391d9b..3875e8b 100644 --- a/IEEE754Adder.xise +++ b/IEEE754Adder.xise @@ -16,31 +16,48 @@ - + - + - + - + - + - + + + + + + + + + + + + + + + + + + @@ -109,7 +126,7 @@ - + @@ -206,7 +223,7 @@ - + @@ -328,7 +345,8 @@ - + + @@ -336,7 +354,7 @@ - + @@ -353,10 +371,10 @@ - - + + - + @@ -373,7 +391,7 @@ - + @@ -382,13 +400,15 @@ - - + + - + + + diff --git a/SpecialCasesCheck.ucf b/SpecialCasesCheck.ucf new file mode 100644 index 0000000..e69de29 diff --git a/SpecialCasesCheck.vhd b/SpecialCasesCheck.vhd index dfaf432..4c056fd 100644 --- a/SpecialCasesCheck.vhd +++ b/SpecialCasesCheck.vhd @@ -16,7 +16,7 @@ architecture SpecialCasesCheckArch of SpecialCasesCheck is isNaN: out std_logic ); end component; - + component ZeroCheck is port( X, Y: in std_logic_vector(31 downto 0); diff --git a/SpecialCasesCheck.xdl b/SpecialCasesCheck.xdl new file mode 100644 index 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a/isim/AdderTest_isim_beh.exe.sim/isimkernel.log b/isim/AdderTest_isim_beh.exe.sim/isimkernel.log new file mode 100644 index 0000000..2d62d69 --- /dev/null +++ b/isim/AdderTest_isim_beh.exe.sim/isimkernel.log @@ -0,0 +1,29 @@ +Command line: + AdderTest_isim_beh.exe + -simmode gui + -simrunnum 0 + -socket 37101 + +Sat Aug 24 17:55:24 2019 + + + Elaboration Time: 0.02 sec + + Current Memory Usage: 195.351 Meg + + Total Signals : 15 + Total Nets : 59 + Total Signal Drivers : 9 + Total Blocks : 3 + Total Primitive Blocks : 2 + Total Processes : 9 + Total Traceable Variables : 10 + Total Scalar Nets and Variables : 421 +Total Line Count : 14 + + Total Simulation Time: 0.03 sec + + Current Memory Usage: 272.949 Meg + +Sat Aug 24 18:01:51 2019 + diff --git a/isim/AdderTest_isim_beh.exe.sim/netId.dat b/isim/AdderTest_isim_beh.exe.sim/netId.dat new file mode 100644 index 0000000000000000000000000000000000000000..bb2641a9d9aee7a14e5ba9e969257543d0825f59 GIT binary patch literal 84 zcmXxXK@I>B6ocVfJv(EEgD{5Mx~N|=ntW+%k}7VD(f;G^=A1J$JLY=|^{+{%{^%T!+(CCSk|-yMC|JvNR6xunh!Xwn2cfbC8W72HJun z;lRq}YSnHaNF~VAxRn*pBwiB5YQWBqCW0zrcg|u0n5bxi(s5|=^-ZJU5P)=AfXc7*a45O9b9i)Jbd{18E0wTB literal 0 HcmV?d00001 diff --git a/isim/AdderTest_isim_beh.exe.sim/work/AdderTest_isim_beh.exe_main.c b/isim/AdderTest_isim_beh.exe.sim/work/AdderTest_isim_beh.exe_main.c new file mode 100644 index 0000000..b0a7feb --- /dev/null +++ b/isim/AdderTest_isim_beh.exe.sim/work/AdderTest_isim_beh.exe_main.c @@ -0,0 +1,40 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +#include "xsi.h" + +struct XSI_INFO xsi_info; + +char *IEEE_P_2592010699; +char *STD_STANDARD; + + +int main(int argc, char **argv) +{ + xsi_init_design(argc, argv); + xsi_register_info(&xsi_info); + + xsi_register_min_prec_unit(-12); + ieee_p_2592010699_init(); + work_a_3841309559_2737618828_init(); + work_a_4008929629_2372691052_init(); + + + xsi_register_tops("work_a_4008929629_2372691052"); + + IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699"); + xsi_register_ieee_std_logic_1164(IEEE_P_2592010699); + STD_STANDARD = xsi_get_engine_memory("std_standard"); + + return xsi_run_simulation(argc, argv); + +} diff --git a/isim/AdderTest_isim_beh.exe.sim/work/AdderTest_isim_beh.exe_main.lin64.o b/isim/AdderTest_isim_beh.exe.sim/work/AdderTest_isim_beh.exe_main.lin64.o new file mode 100644 index 0000000000000000000000000000000000000000..ac16d1fa2b5286061d4a96ddd3817efa60c01060 GIT binary patch literal 2768 zcmbW3U2hvj6o$ukOHCJ@c_Up4m^E z?bU21!<1#%TkNo=C}V%7U_Hil_B1=qZgyIGf8&44!*Kb}amW{HpSR|Qk zmaJ0o^1A33TTYblt9I!MW=M8EaV+!kI?L?NWGa%;@>U zq3}rJ`H?Va?pJ9&y}P7Cw%Fu%0%s`XOdj7ADHU7c39XB|tjB9iwVg=C2rp348F=wY z{4(~f+-FZwj4%&KHkUYdi9C2t)|LB31)A5#dX?JI=i}yEl#B6gDrr;WzmbL%%jF#S zx@4xNJ1>QX#`XMbGGCLiB_-4vbo`#o&uY4s6xKDap1;DkDbSxO+V)Q;3iY1w{*bHk z6+cHzfA+|{FUQ|RC1v{jQP<}Vxp^{4x-T2gP!&ZVAKPrw`1_}le4!1fRTI&KU+7M- zzs3`qXuQe2gL2^t^{uo!QKWum<4v+UUFZs)d(l|=ax0CEOjiZ`7 zb_y_t{X3gluR0G(#AlGC8TRuej(v8H{XJG~%5O~3M^pG$Q}}mN_|H@L?^F1rDSVb* zIp(k4fb#Ri)mkX^z?xI^>r?cs(eI0(E5eAop*!RoV$%@2f)5?nGkVNuFPr$Gi=n-2 zGf>9Y+BcROZGK~QwbShKZeyw43on)yD^|5?SC1$r-qVQ!6Fitlf`lNw914xGR +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/Adder.vhd"; +extern char *IEEE_P_2592010699; + +char *ieee_p_2592010699_sub_16439767405979520975_503743352(char *, char *, char *, char *, char *, char *); +char *ieee_p_2592010699_sub_16439989832805790689_503743352(char *, char *, char *, char *, char *, char *); +char *ieee_p_2592010699_sub_16439989833707593767_503743352(char *, char *, char *, char *, char *, char *); +unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char ); +unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char ); +unsigned char ieee_p_2592010699_sub_3488768497506413324_503743352(char *, unsigned char , unsigned char ); + + +static void work_a_3841309559_2737618828_p_0(char *t0) +{ + char t1[16]; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(21, ng0); + +LAB3: t2 = (t0 + 1032U); + t3 = *((char **)t2); + t2 = (t0 + 7680U); + t4 = (t0 + 1192U); + t5 = *((char **)t4); + t4 = (t0 + 7696U); + t6 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4); + t7 = (t1 + 12U); + t8 = *((unsigned int *)t7); + t9 = (1U * t8); + t10 = (8U != t9); + if (t10 == 1) + goto LAB5; + +LAB6: t11 = (t0 + 5304); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t6, 8U); + xsi_driver_first_trans_fast(t11); + +LAB2: t16 = (t0 + 5144); + *((int *)t16) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(8U, t9, 0); + goto LAB6; + +} + +static void work_a_3841309559_2737618828_p_1(char *t0) +{ + char t1[16]; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(22, ng0); + +LAB3: t2 = (t0 + 1032U); + t3 = *((char **)t2); + t2 = (t0 + 7680U); + t4 = (t0 + 1192U); + t5 = *((char **)t4); + t4 = (t0 + 7696U); + t6 = ieee_p_2592010699_sub_16439767405979520975_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4); + t7 = (t1 + 12U); + t8 = *((unsigned int *)t7); + t9 = (1U * t8); + t10 = (8U != t9); + if (t10 == 1) + goto LAB5; + +LAB6: t11 = (t0 + 5368); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t6, 8U); + xsi_driver_first_trans_fast(t11); + +LAB2: t16 = (t0 + 5160); + *((int *)t16) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(8U, t9, 0); + goto LAB6; + +} + +static void work_a_3841309559_2737618828_p_2(char *t0) +{ + char t1[16]; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(23, ng0); + +LAB3: t2 = (t0 + 1032U); + t3 = *((char **)t2); + t2 = (t0 + 7680U); + t4 = (t0 + 1192U); + t5 = *((char **)t4); + t4 = (t0 + 7696U); + t6 = ieee_p_2592010699_sub_16439989833707593767_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4); + t7 = (t1 + 12U); + t8 = *((unsigned int *)t7); + t9 = (1U * t8); + t10 = (8U != t9); + if (t10 == 1) + goto LAB5; + +LAB6: t11 = (t0 + 5432); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t6, 8U); + xsi_driver_first_trans_fast(t11); + +LAB2: t16 = (t0 + 5176); + *((int *)t16) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(8U, t9, 0); + goto LAB6; + +} + +static void work_a_3841309559_2737618828_p_3(char *t0) +{ + char *t1; + char *t2; + unsigned char t3; + char *t4; + char *t5; + char *t6; + char *t7; + int t8; + int t9; + int t10; + int t11; + int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + char *t16; + int t17; + int t18; + unsigned int t19; + unsigned int t20; + unsigned int t21; + char *t22; + unsigned char t23; + char *t24; + char *t25; + int t26; + int t27; + int t28; + unsigned int t29; + unsigned int t30; + unsigned int t31; + char *t32; + unsigned char t33; + unsigned char t34; + unsigned char t35; + char *t36; + int t37; + int t38; + unsigned int t39; + unsigned int t40; + unsigned int t41; + char *t42; + char *t43; + char *t44; + char *t45; + char *t46; + +LAB0: xsi_set_current_line(27, ng0); + t1 = (t0 + 1352U); + t2 = *((char **)t1); + t3 = *((unsigned char *)t2); + t1 = (t0 + 5496); + t4 = (t1 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + *((unsigned char *)t7) = t3; + xsi_driver_first_trans_delta(t1, 7U, 1, 0LL); + xsi_set_current_line(28, ng0); + t8 = (8 - 1); + t1 = (t0 + 7853); + *((int *)t1) = t8; + t2 = (t0 + 7857); + *((int *)t2) = 1; + t9 = t8; + t10 = 1; + +LAB2: if (t9 >= t10) + goto LAB3; + +LAB5: t1 = (t0 + 5192); + *((int *)t1) = 1; + +LAB1: return; +LAB3: xsi_set_current_line(29, ng0); + t4 = (t0 + 1832U); + t5 = *((char **)t4); + t4 = (t0 + 7853); + t11 = *((int *)t4); + t12 = (t11 - 7); + t13 = (t12 * -1); + xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t4)); + t14 = (1U * t13); + t15 = (0 + t14); + t6 = (t5 + t15); + t3 = *((unsigned char *)t6); + t7 = (t0 + 1992U); + t16 = *((char **)t7); + t7 = (t0 + 7853); + t17 = *((int *)t7); + t18 = (t17 - 7); + t19 = (t18 * -1); + xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t7)); + t20 = (1U * t19); + t21 = (0 + t20); + t22 = (t16 + t21); + t23 = *((unsigned char *)t22); + t24 = (t0 + 2152U); + t25 = *((char **)t24); + t24 = (t0 + 7853); + t26 = *((int *)t24); + t27 = (t26 - 1); + t28 = (t27 - 7); + t29 = (t28 * -1); + xsi_vhdl_check_range_of_index(7, 0, -1, t27); + t30 = (1U * t29); + t31 = (0 + t30); + t32 = (t25 + t31); + t33 = *((unsigned char *)t32); + t34 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t23, t33); + t35 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t3, t34); + t36 = (t0 + 7853); + t37 = *((int *)t36); + t38 = (t37 - 7); + t39 = (t38 * -1); + t40 = (1 * t39); + t41 = (0U + t40); + t42 = (t0 + 5496); + t43 = (t42 + 56U); + t44 = *((char **)t43); + t45 = (t44 + 56U); + t46 = *((char **)t45); + *((unsigned char *)t46) = t35; + xsi_driver_first_trans_delta(t42, t41, 1, 0LL); + +LAB4: t1 = (t0 + 7853); + t9 = *((int *)t1); + t2 = (t0 + 7857); + t10 = *((int *)t2); + if (t9 == t10) + goto LAB5; + +LAB6: t8 = (t9 + -1); + t9 = t8; + t4 = (t0 + 7853); + *((int *)t4) = t9; + goto LAB2; + +} + +static void work_a_3841309559_2737618828_p_4(char *t0) +{ + char t1[16]; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(33, ng0); + +LAB3: t2 = (t0 + 2312U); + t3 = *((char **)t2); + t2 = (t0 + 7776U); + t4 = (t0 + 2152U); + t5 = *((char **)t4); + t4 = (t0 + 7760U); + t6 = ieee_p_2592010699_sub_16439989833707593767_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4); + t7 = (t1 + 12U); + t8 = *((unsigned int *)t7); + t9 = (1U * t8); + t10 = (8U != t9); + if (t10 == 1) + goto LAB5; + +LAB6: t11 = (t0 + 5560); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t6, 8U); + xsi_driver_first_trans_fast_port(t11); + +LAB2: t16 = (t0 + 5208); + *((int *)t16) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(8U, t9, 0); + goto LAB6; + +} + +static void work_a_3841309559_2737618828_p_5(char *t0) +{ + char *t1; + char *t2; + int t3; + int t4; + unsigned int t5; + unsigned int t6; + unsigned int t7; + unsigned char t8; + char *t9; + char *t10; + int t11; + int t12; + unsigned int t13; + unsigned int t14; + unsigned int t15; + unsigned char t16; + unsigned char t17; + char *t18; + char *t19; + char *t20; + char *t21; + char *t22; + char *t23; + +LAB0: xsi_set_current_line(34, ng0); + +LAB3: t1 = (t0 + 2312U); + t2 = *((char **)t1); + t3 = (8 - 1); + t4 = (t3 - 7); + t5 = (t4 * -1); + t6 = (1U * t5); + t7 = (0 + t6); + t1 = (t2 + t7); + t8 = *((unsigned char *)t1); + t9 = (t0 + 2152U); + t10 = *((char **)t9); + t11 = (8 - 1); + t12 = (t11 - 7); + t13 = (t12 * -1); + t14 = (1U * t13); + t15 = (0 + t14); + t9 = (t10 + t15); + t16 = *((unsigned char *)t9); + t17 = ieee_p_2592010699_sub_3488768497506413324_503743352(IEEE_P_2592010699, t8, t16); + t18 = (t0 + 5624); + t19 = (t18 + 56U); + t20 = *((char **)t19); + t21 = (t20 + 56U); + t22 = *((char **)t21); + *((unsigned char *)t22) = t17; + xsi_driver_first_trans_fast_port(t18); + +LAB2: t23 = (t0 + 5224); + *((int *)t23) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + + +extern void work_a_3841309559_2737618828_init() +{ + static char *pe[] = {(void *)work_a_3841309559_2737618828_p_0,(void *)work_a_3841309559_2737618828_p_1,(void *)work_a_3841309559_2737618828_p_2,(void *)work_a_3841309559_2737618828_p_3,(void *)work_a_3841309559_2737618828_p_4,(void *)work_a_3841309559_2737618828_p_5}; + xsi_register_didat("work_a_3841309559_2737618828", "isim/AdderTest_isim_beh.exe.sim/work/a_3841309559_2737618828.didat"); + xsi_register_executes(pe); +} diff --git a/isim/AdderTest_isim_beh.exe.sim/work/a_3841309559_2737618828.didat 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+/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0xfbc00daa */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/AdderTest.vhd"; + + + +static void work_a_4008929629_2372691052_p_0(char *t0) +{ + char *t1; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + int64 t7; + int64 t8; + +LAB0: t1 = (t0 + 3104U); + t2 = *((char **)t1); + if (t2 == 0) + goto LAB2; + +LAB3: goto *t2; + +LAB2: xsi_set_current_line(81, ng0); + t2 = (t0 + 3984); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t4 + 56U); + t6 = *((char **)t5); + *((unsigned char *)t6) = (unsigned char)2; + xsi_driver_first_trans_fast(t2); + xsi_set_current_line(82, ng0); + t2 = (t0 + 2128U); + t3 = *((char **)t2); + t7 = *((int64 *)t3); + t8 = (t7 / 2); + t2 = (t0 + 2912); + xsi_process_wait(t2, t8); + +LAB6: *((char **)t1) = &&LAB7; + +LAB1: return; +LAB4: xsi_set_current_line(83, ng0); + t2 = (t0 + 3984); + t3 = (t2 + 56U); + t4 = *((char **)t3); + t5 = (t4 + 56U); + t6 = *((char **)t5); + *((unsigned char *)t6) = (unsigned char)3; + xsi_driver_first_trans_fast(t2); + xsi_set_current_line(84, ng0); + t2 = (t0 + 2128U); + t3 = *((char **)t2); + t7 = *((int64 *)t3); + t8 = (t7 / 2); + t2 = (t0 + 2912); + xsi_process_wait(t2, t8); + +LAB10: *((char **)t1) = &&LAB11; + goto LAB1; + +LAB5: goto LAB4; + +LAB7: goto LAB5; + +LAB8: goto LAB2; + +LAB9: goto LAB8; + +LAB11: goto LAB9; + +} + +static void work_a_4008929629_2372691052_p_1(char *t0) +{ + char *t1; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + +LAB0: xsi_set_current_line(87, ng0); + +LAB3: t1 = (t0 + 6136); + t3 = (t0 + 4048); + t4 = (t3 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memcpy(t7, t1, 8U); + xsi_driver_first_trans_fast(t3); + +LAB2: +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_4008929629_2372691052_p_2(char *t0) +{ + char *t1; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + +LAB0: xsi_set_current_line(88, ng0); + +LAB3: t1 = (t0 + 6144); + t3 = (t0 + 4112); + t4 = (t3 + 56U); + t5 = *((char **)t4); + t6 = (t5 + 56U); + t7 = *((char **)t6); + memcpy(t7, t1, 8U); + xsi_driver_first_trans_fast(t3); + +LAB2: +LAB1: return; +LAB4: goto LAB2; + +} + + +extern void work_a_4008929629_2372691052_init() +{ + static char *pe[] = {(void *)work_a_4008929629_2372691052_p_0,(void *)work_a_4008929629_2372691052_p_1,(void *)work_a_4008929629_2372691052_p_2}; + xsi_register_didat("work_a_4008929629_2372691052", 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\ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0xfbc00daa */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd"; +extern char *IEEE_P_2592010699; + +unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char ); +unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char ); +unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char ); + + +static void work_a_0557987184_1272247069_p_0(char *t0) +{ + char *t1; + char *t2; + unsigned int t3; + unsigned int t4; + unsigned int t5; + char *t6; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + +LAB0: xsi_set_current_line(17, ng0); + +LAB3: t1 = (t0 + 1032U); + t2 = *((char **)t1); + t3 = (31 - 30); + t4 = (t3 * 1U); + t5 = (0 + t4); + t1 = (t2 + t5); + t6 = (t0 + 5104); + t7 = (t6 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t1, 8U); + xsi_driver_first_trans_fast(t6); + +LAB2: t11 = (t0 + 4944); + *((int *)t11) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_0557987184_1272247069_p_1(char *t0) +{ + char *t1; + char *t2; + unsigned int t3; + unsigned int t4; + unsigned int t5; + char *t6; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + +LAB0: xsi_set_current_line(18, ng0); + +LAB3: t1 = (t0 + 1032U); + t2 = *((char **)t1); + t3 = (31 - 22); + t4 = (t3 * 1U); + t5 = (0 + t4); + t1 = (t2 + t5); + t6 = (t0 + 5168); + t7 = (t6 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t1, 23U); + xsi_driver_first_trans_fast(t6); + +LAB2: t11 = (t0 + 4960); + *((int *)t11) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_0557987184_1272247069_p_2(char *t0) +{ + char *t1; + char *t2; + int t3; + int t4; + char *t5; + char *t6; + unsigned char t7; + char *t8; + int t9; + int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + char *t14; + unsigned char t15; + unsigned char t16; + char *t17; + char *t18; + +LAB0: xsi_set_current_line(23, ng0); + t1 = (t0 + 2288U); + t2 = *((char **)t1); + t1 = (t2 + 0); + *((unsigned char *)t1) = (unsigned char)3; + xsi_set_current_line(24, ng0); + t1 = (t0 + 7603); + *((int *)t1) = 7; + t2 = (t0 + 7607); + *((int *)t2) = 0; + t3 = 7; + t4 = 0; + +LAB2: if (t3 >= t4) + goto LAB3; + +LAB5: xsi_set_current_line(27, ng0); + t1 = (t0 + 2288U); + t2 = *((char **)t1); + t7 = *((unsigned char *)t2); + t1 = (t0 + 5232); + t5 = (t1 + 56U); + t6 = *((char **)t5); + t8 = (t6 + 56U); + t14 = *((char **)t8); + *((unsigned char *)t14) = t7; + xsi_driver_first_trans_fast(t1); + t1 = (t0 + 4976); + *((int *)t1) = 1; + +LAB1: return; +LAB3: xsi_set_current_line(25, ng0); + t5 = (t0 + 2288U); + t6 = *((char **)t5); + t7 = *((unsigned char *)t6); + t5 = (t0 + 1512U); + t8 = *((char **)t5); + t5 = (t0 + 7603); + t9 = *((int *)t5); + t10 = (t9 - 7); + t11 = (t10 * -1); + t12 = (1U * t11); + t13 = (0 + t12); + t14 = (t8 + t13); + t15 = *((unsigned char *)t14); + t16 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t7, t15); + t17 = (t0 + 2288U); + t18 = *((char **)t17); + t17 = (t18 + 0); + *((unsigned char *)t17) = t16; + +LAB4: t1 = (t0 + 7603); + t3 = *((int *)t1); + t2 = (t0 + 7607); + t4 = *((int *)t2); + if (t3 == t4) + goto LAB5; + +LAB6: t9 = (t3 + -1); + t3 = t9; + t5 = (t0 + 7603); + *((int *)t5) = t3; + goto LAB2; + +} + +static void work_a_0557987184_1272247069_p_3(char *t0) +{ + char *t1; + char *t2; + int t3; + int t4; + char *t5; + char *t6; + unsigned char t7; + char *t8; + int t9; + int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + char *t14; + unsigned char t15; + unsigned char t16; + char *t17; + char *t18; + +LAB0: xsi_set_current_line(33, ng0); + t1 = (t0 + 2408U); + t2 = *((char **)t1); + t1 = (t2 + 0); + *((unsigned char *)t1) = (unsigned char)2; + xsi_set_current_line(34, ng0); + t1 = (t0 + 7611); + *((int *)t1) = 22; + t2 = (t0 + 7615); + *((int *)t2) = 0; + t3 = 22; + t4 = 0; + +LAB2: if (t3 >= t4) + goto LAB3; + +LAB5: xsi_set_current_line(37, ng0); + t1 = (t0 + 2408U); + t2 = *((char **)t1); + t7 = *((unsigned char *)t2); + t1 = (t0 + 5296); + t5 = (t1 + 56U); + t6 = *((char **)t5); + t8 = (t6 + 56U); + t14 = *((char **)t8); + *((unsigned char *)t14) = t7; + xsi_driver_first_trans_fast(t1); + t1 = (t0 + 4992); + *((int *)t1) = 1; + +LAB1: return; +LAB3: xsi_set_current_line(35, ng0); + t5 = (t0 + 2408U); + t6 = *((char **)t5); + t7 = *((unsigned char *)t6); + t5 = (t0 + 1672U); + t8 = *((char **)t5); + t5 = (t0 + 7611); + t9 = *((int *)t5); + t10 = (t9 - 22); + t11 = (t10 * -1); + t12 = (1U * t11); + t13 = (0 + t12); + t14 = (t8 + t13); + t15 = *((unsigned char *)t14); + t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15); + t17 = (t0 + 2408U); + t18 = *((char **)t17); + t17 = (t18 + 0); + *((unsigned char *)t17) = t16; + +LAB4: t1 = (t0 + 7611); + t3 = *((int *)t1); + t2 = (t0 + 7615); + t4 = *((int *)t2); + if (t3 == t4) + goto LAB5; + +LAB6: t9 = (t3 + -1); + t3 = t9; + t5 = (t0 + 7611); + *((int *)t5) = t3; + goto LAB2; + +} + +static void work_a_0557987184_1272247069_p_4(char *t0) +{ + char *t1; + char *t2; + unsigned char t3; + char *t4; + unsigned char t5; + unsigned char t6; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + +LAB0: xsi_set_current_line(40, ng0); + +LAB3: t1 = (t0 + 1832U); + t2 = *((char **)t1); + t3 = *((unsigned char *)t2); + t1 = (t0 + 1992U); + t4 = *((char **)t1); + t5 = *((unsigned char *)t4); + t6 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t5); + t1 = (t0 + 5360); + t7 = (t1 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + *((unsigned char *)t10) = t6; + xsi_driver_first_trans_fast_port(t1); + +LAB2: t11 = (t0 + 5008); + *((int *)t11) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_0557987184_1272247069_p_5(char *t0) +{ + char *t1; + char *t2; + unsigned char t3; + char *t4; + unsigned char t5; + unsigned char t6; + unsigned char t7; + char *t8; + char *t9; + char *t10; + char *t11; + char *t12; + +LAB0: xsi_set_current_line(41, ng0); + +LAB3: t1 = (t0 + 1832U); + t2 = *((char **)t1); + t3 = *((unsigned char *)t2); + t1 = (t0 + 1992U); + t4 = *((char **)t1); + t5 = *((unsigned char *)t4); + t6 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t5); + t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t6); + t1 = (t0 + 5424); + t8 = (t1 + 56U); + t9 = *((char **)t8); + t10 = (t9 + 56U); + t11 = *((char **)t10); + *((unsigned char *)t11) = t7; + xsi_driver_first_trans_fast_port(t1); + +LAB2: t12 = (t0 + 5024); + *((int *)t12) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + + +extern void work_a_0557987184_1272247069_init() +{ + static char *pe[] = {(void *)work_a_0557987184_1272247069_p_0,(void *)work_a_0557987184_1272247069_p_1,(void *)work_a_0557987184_1272247069_p_2,(void *)work_a_0557987184_1272247069_p_3,(void *)work_a_0557987184_1272247069_p_4,(void *)work_a_0557987184_1272247069_p_5}; + xsi_register_didat("work_a_0557987184_1272247069", "isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.didat"); + xsi_register_executes(pe); +} diff --git a/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.didat b/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.didat new file mode 100644 index 0000000000000000000000000000000000000000..e2c3b7773c022c5e5aae39dee3101e4562731f4f GIT binary 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zN0Wf~AYaFhBuYAb9@N}XJ%bAy(Rs0geH^Z`+{jhLN!F!}mC7?|{q2-&kjW z=FNaE>K}J7<9i;o@jF6(r6`T>SHPYTyhqF<@wWv3N$?`{Q9gzX{p=MFWr$Pf$0Ox0 zVVDPeitXZI8`~ie4}TNa4t>MB?eqB^=j!g@*m{_F$s|`lLAw|7C!u-08W4U1s`Pi^ zgI)NZE_}KRf1(S2y9@uK3*P|GsZ;*jx^ULz#HSTm)zXr&ROW&QL$hio+022+dP<4) z6k_Ws#Me`ZuBQ-TT7HQCtfN|)sWg~5oZmgD=gr+acaG;K%n5xkpEKE^dc~|+2P*Z3 zRWqGq_8J7o^Wt2?s&mD<)i8^5wHh3e%&E$Z#qjiPj+(J#77o8~P|vc8WmzzXtHi9& z?K9))L^P6($70cVB%R8pQ!z6c0T_=bW8F*=nM^vBNn}&0NFo)D#1bjV26HUcDi1=^ z`zy72!)(+FGj(%+0h-m>T7#$CMd1PglZg~mkxpmgiAXXoC%Li$;Igp^u3zErP86|R z!`k7T<%y#X3a+5I=McXJAqeXG;Uc~jAqeW@AIZdZgdnJo-vRME5Q3mS`Xqh;AqcKa zxb_mSA_PHwJcAQI3~dzTcxEF05<(EYuR9G?Z%`>w=g|DOo1*7d2RFW1$JiG!&5Zxvk4|F$l? z+=V|SaXJ4tBrfNFMsPL%vyy%g@}+tBO>n%)@1a-hmumjIBrfMu5M1?hP|}z4T#&fz z2h!kz(~Z7p-=^~daoXo;4 +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd"; +extern char *IEEE_P_2592010699; + +unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char ); +unsigned char ieee_p_2592010699_sub_3496108612141461530_503743352(char *, unsigned char , unsigned char ); +unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char ); + + +static void work_a_1540508602_4151211736_p_0(char *t0) +{ + char *t1; + char *t2; + int t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + unsigned char t7; + char *t8; + char *t9; + char *t10; + char *t11; + char *t12; + char *t13; + +LAB0: xsi_set_current_line(28, ng0); + +LAB3: t1 = (t0 + 1032U); + t2 = *((char **)t1); + t3 = (31 - 31); + t4 = (t3 * -1); + t5 = (1U * t4); + t6 = (0 + t5); + t1 = (t2 + t6); + t7 = *((unsigned char *)t1); + t8 = (t0 + 5184); + t9 = (t8 + 56U); + t10 = *((char **)t9); + t11 = (t10 + 56U); + t12 = *((char **)t11); + *((unsigned char *)t12) = t7; + xsi_driver_first_trans_fast(t8); + +LAB2: t13 = (t0 + 5024); + *((int *)t13) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_1540508602_4151211736_p_1(char *t0) +{ + char *t1; + char *t2; + int t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + unsigned char t7; + char *t8; + char *t9; + char *t10; + char *t11; + char *t12; + char *t13; + +LAB0: xsi_set_current_line(29, ng0); + +LAB3: t1 = (t0 + 1192U); + t2 = *((char **)t1); + t3 = (31 - 31); + t4 = (t3 * -1); + t5 = (1U * t4); + t6 = (0 + t5); + t1 = (t2 + t6); + t7 = *((unsigned char *)t1); + t8 = (t0 + 5248); + t9 = (t8 + 56U); + t10 = *((char **)t9); + t11 = (t10 + 56U); + t12 = *((char **)t11); + *((unsigned char *)t12) = t7; + xsi_driver_first_trans_fast(t8); + +LAB2: t13 = (t0 + 5040); + *((int *)t13) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_1540508602_4151211736_p_2(char *t0) +{ + char *t1; + char *t2; + unsigned int t3; + unsigned int t4; + unsigned int t5; + char *t6; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + +LAB0: xsi_set_current_line(30, ng0); + +LAB3: t1 = (t0 + 1032U); + t2 = *((char **)t1); + t3 = (31 - 30); + t4 = (t3 * 1U); + t5 = (0 + t4); + t1 = (t2 + t5); + t6 = (t0 + 5312); + t7 = (t6 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t1, 31U); + xsi_driver_first_trans_fast(t6); + +LAB2: t11 = (t0 + 5056); + *((int *)t11) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_1540508602_4151211736_p_3(char *t0) +{ + char *t1; + char *t2; + unsigned int t3; + unsigned int t4; + unsigned int t5; + char *t6; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + +LAB0: xsi_set_current_line(31, ng0); + +LAB3: t1 = (t0 + 1192U); + t2 = *((char **)t1); + t3 = (31 - 30); + t4 = (t3 * 1U); + t5 = (0 + t4); + t1 = (t2 + t5); + t6 = (t0 + 5376); + t7 = (t6 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + memcpy(t10, t1, 31U); + xsi_driver_first_trans_fast(t6); + +LAB2: t11 = (t0 + 5072); + *((int *)t11) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_1540508602_4151211736_p_4(char *t0) +{ + char *t1; + char *t2; + unsigned char t3; + char *t4; + unsigned char t5; + unsigned char t6; + char *t7; + char *t8; + char *t9; + char *t10; + char *t11; + +LAB0: xsi_set_current_line(33, ng0); + +LAB3: t1 = (t0 + 1512U); + t2 = *((char **)t1); + t3 = *((unsigned char *)t2); + t1 = (t0 + 1672U); + t4 = *((char **)t1); + t5 = *((unsigned char *)t4); + t6 = ieee_p_2592010699_sub_3496108612141461530_503743352(IEEE_P_2592010699, t3, t5); + t1 = (t0 + 5440); + t7 = (t1 + 56U); + t8 = *((char **)t7); + t9 = (t8 + 56U); + t10 = *((char **)t9); + *((unsigned char *)t10) = t6; + xsi_driver_first_trans_fast(t1); + +LAB2: t11 = (t0 + 5088); + *((int *)t11) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_1540508602_4151211736_p_5(char *t0) +{ + char *t1; + char *t2; + unsigned char t3; + unsigned char t4; + char *t5; + unsigned char t6; + unsigned char t7; + char *t8; + char *t9; + char *t10; + char *t11; + char *t12; + +LAB0: xsi_set_current_line(38, ng0); + +LAB3: t1 = (t0 + 2312U); + t2 = *((char **)t1); + t3 = *((unsigned char *)t2); + t4 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t3); + t1 = (t0 + 2152U); + t5 = *((char **)t1); + t6 = *((unsigned char *)t5); + t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t4, t6); + t1 = (t0 + 5504); + t8 = (t1 + 56U); + t9 = *((char **)t8); + t10 = (t9 + 56U); + t11 = *((char **)t10); + *((unsigned char *)t11) = t7; + xsi_driver_first_trans_fast_port(t1); + +LAB2: t12 = (t0 + 5104); + *((int *)t12) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + + +extern void work_a_1540508602_4151211736_init() +{ + static char *pe[] = {(void *)work_a_1540508602_4151211736_p_0,(void *)work_a_1540508602_4151211736_p_1,(void *)work_a_1540508602_4151211736_p_2,(void *)work_a_1540508602_4151211736_p_3,(void *)work_a_1540508602_4151211736_p_4,(void *)work_a_1540508602_4151211736_p_5}; + xsi_register_didat("work_a_1540508602_4151211736", "isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1540508602_4151211736.didat"); + xsi_register_executes(pe); +} diff --git a/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1540508602_4151211736.didat b/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1540508602_4151211736.didat new file mode 100644 index 0000000000000000000000000000000000000000..3b3ece255445ad8a0fab16138161a308ae3f7d78 GIT binary patch literal 5160 zcmeHKO=whC6h8H@wi*@uX)UphBEeN=-presBnz2T0~K6Ibs?fWUNVo)Gk-cSv6E7; zEiMXOblXMgrW@(Lh+v_M(nUciU3XLJvWqUdC>WZ4-+T8=W^P{MTvW`$1K<7LJ-_#! zci)}lyMZ4cUn+;!1oHQ*97R3@?ranJx(h4j+21bG*e!Aw_zO7jnurhV*d?-pc>i^g zS>Vndk-@!~15My#;B(+E@GI~;KsjYNo8^!1!RNB&H@F}94NijV269m30&v;j)FIRW znppoMU^nty#d;rLeUE^%`$WzIKMjbS1XHL}*mLT&F8P%-Vr}4@KnqgVxiVYKXR<jfS_|BIWYq}si>$74 zM9b6sA$W!gBQ>z~y4Cd5%=*g!_pud(>-iqY`f{MNq--uS)Y0@l(EbI$GeqHj{s6ML zwLH`h8GzOa{qF&qhwpj-%B(*_nB~iVw|n)>^Cy5SAr+pL)15rBwjk*10R1U>c@DvN zI5Vf`V}64?6Y$wA&si9cm^`?i5ZElw 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literal 0 HcmV?d00001 diff --git a/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.c b/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.c new file mode 100644 index 0000000..dcd5fac --- /dev/null +++ b/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.c @@ -0,0 +1,31 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0xfbc00daa */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif + + + + +extern void work_a_1684417184_3395701438_init() +{ + xsi_register_didat("work_a_1684417184_3395701438", "isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.didat"); +} diff --git a/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.didat b/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.didat new file mode 100644 index 0000000000000000000000000000000000000000..b76d2a93fc157c6ff0fb194f32f3d11dfa01820e GIT binary patch literal 3668 zcmeH|J!lhQ7{?#K6|GoY1eHcy#3A>c4-r(-fW_j{f*{Iq-W^=1O=~V{Du{#Kbm-tB zWOUNSNkkkvIJgKM92^vv4lZsEf@1tXxqFj0*Ff53 zTqQ_r7e9&4g2k;wO^Kgz-`qwtxr1m4ya(UGk)5#JPP7WHpznc);3N13P9W}Sa2^C; z2{ZxA7t9Zm-LO3r+Y8(Ay+r+Jju5>DZ(^qR6EOkmUj=WGZyY=VPr%9^q7NVgo&y%v z36f*h%Xzo7J-QDbGuW1PE5@5?IXe3f5|Lw&-6iY;ew~;PBnOUxBkt7Bc4Ev&Ao}QT zNLsN(>u9yu8An98GIRsn2SU!Evri2EaLf50176p^AY9KU5beu>PD#<2DAUpOc6k07 zz!h!_uV)m>$gej}26Ie5Vf)WO#NqQTLmBN)2BZG+>t3&(;~d08yrz7vcT>i>AjRp; zG93L+JHU5}k%jMN5_x{u@4o}deH7ngZiUAS7|HtR8z5$T=Y;lU!iT>fvdHm-{#C+f zJ++OY7&+E@YCD$j;ct>Gay+3wp70U+jkL>H&^xdqElmF3g1K2=nY`&b%EVMznJAab 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b/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_2347761600_1146481140.c @@ -0,0 +1,180 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0xfbc00daa */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd"; +extern char *IEEE_P_2592010699; + +char *ieee_p_2592010699_sub_16439989833707593767_503743352(char *, char *, char *, char *, char *, char *); +unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char ); +unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char ); + + +static void work_a_2347761600_1146481140_p_0(char *t0) +{ + char t1[16]; + char *t2; + char *t3; + char *t4; + char *t5; + char *t6; + char *t7; + unsigned int t8; + unsigned int t9; + unsigned char t10; + char *t11; + char *t12; + char *t13; + char *t14; + char *t15; + char *t16; + +LAB0: xsi_set_current_line(15, ng0); + +LAB3: t2 = (t0 + 1032U); + t3 = *((char **)t2); + t2 = (t0 + 5352U); + t4 = (t0 + 1192U); + t5 = *((char **)t4); + t4 = (t0 + 5368U); + t6 = ieee_p_2592010699_sub_16439989833707593767_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4); + t7 = (t1 + 12U); + t8 = *((unsigned int *)t7); + t9 = (1U * t8); + t10 = (31U != t9); + if (t10 == 1) + goto LAB5; + +LAB6: t11 = (t0 + 3568); + t12 = (t11 + 56U); + t13 = *((char **)t12); + t14 = (t13 + 56U); + t15 = *((char **)t14); + memcpy(t15, t6, 31U); + xsi_driver_first_trans_fast(t11); + +LAB2: t16 = (t0 + 3472); + *((int *)t16) = 1; + +LAB1: return; +LAB4: goto LAB2; + +LAB5: xsi_size_not_matching(31U, t9, 0); + goto LAB6; + +} + +static void work_a_2347761600_1146481140_p_1(char *t0) +{ + char *t1; + char *t2; + int t3; + int t4; + char *t5; + char *t6; + unsigned char t7; + char *t8; + int t9; + int t10; + unsigned int t11; + unsigned int t12; + unsigned int t13; + char *t14; + unsigned char t15; + unsigned char t16; + char *t17; + char *t18; + +LAB0: xsi_set_current_line(20, ng0); + t1 = (t0 + 1928U); + t2 = *((char **)t1); + t1 = (t2 + 0); + *((unsigned char *)t1) = (unsigned char)2; + xsi_set_current_line(21, ng0); + t1 = (t0 + 5506); + *((int *)t1) = 30; + t2 = (t0 + 5510); + *((int *)t2) = 0; + t3 = 30; + t4 = 0; + +LAB2: if (t3 >= t4) + goto LAB3; + +LAB5: xsi_set_current_line(24, ng0); + t1 = (t0 + 1928U); + t2 = *((char **)t1); + t7 = *((unsigned char *)t2); + t15 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t7); + t1 = (t0 + 3632); + t5 = (t1 + 56U); + t6 = *((char **)t5); + t8 = (t6 + 56U); + t14 = *((char **)t8); + *((unsigned char *)t14) = t15; + xsi_driver_first_trans_fast_port(t1); + t1 = (t0 + 3488); + *((int *)t1) = 1; + +LAB1: return; +LAB3: xsi_set_current_line(22, ng0); + t5 = (t0 + 1928U); + t6 = *((char **)t5); + t7 = *((unsigned char *)t6); + t5 = (t0 + 1512U); + t8 = *((char **)t5); + t5 = (t0 + 5506); + t9 = *((int *)t5); + t10 = (t9 - 30); + t11 = (t10 * -1); + t12 = (1U * t11); + t13 = (0 + t12); + t14 = (t8 + t13); + t15 = *((unsigned char *)t14); + t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15); + t17 = (t0 + 1928U); + t18 = *((char **)t17); + t17 = (t18 + 0); + *((unsigned char *)t17) = t16; + +LAB4: t1 = (t0 + 5506); + t3 = *((int *)t1); + t2 = (t0 + 5510); + t4 = *((int *)t2); + if (t3 == t4) + goto LAB5; + +LAB6: t9 = (t3 + -1); + t3 = t9; + t5 = (t0 + 5506); + *((int *)t5) = t3; + goto LAB2; + +} + + +extern void work_a_2347761600_1146481140_init() +{ + static char *pe[] = {(void *)work_a_2347761600_1146481140_p_0,(void *)work_a_2347761600_1146481140_p_1}; + xsi_register_didat("work_a_2347761600_1146481140", "isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_2347761600_1146481140.didat"); + xsi_register_executes(pe); +} diff --git a/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_2347761600_1146481140.didat b/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_2347761600_1146481140.didat new file mode 100644 index 0000000000000000000000000000000000000000..bf33943bc8afe5a4f7eeafb1a3dd5c09a6688743 GIT binary patch literal 3488 zcmeHJJ8KkC6h3NvVlYY+L85{d7P60IcJru=vS1*Ekd(?enYplI-0ZqL8zU+Trm*u5 zq(~_i7NU(<2sZwJlnNFK79tjQit+nq=j={4Ys`R(5f6O#+a6vt7gj7P>?N*q>p(1dN00CGZC5-6?Vc zuz*S625=XkEJb@ZR-MPsi0O*rHR9qf5k(R6+YuIbV^83HgvD+VqKNw60*}FU9`$+9 z^T2WBodlM^-vv#fP0_xlUH7Hl6lSyrt_ie4(5i5*Hfps|E8_l6bA+zihqiXn+;%(H z^x?Qd=|dlITusg=k)4WhS|ei=%B`BQNn|+^=8G&ZbHuTP{4Vqi4Ur5%-h*Y>gj3LL_2$bq-j|>q5lPds~igR55d^Z!}T#>EuK&CD-X~9EO@9zj)r5W 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zh*+92Rl_zkR8ua^=sFxL~ZK0tLQmY(b9CA>$hyZ0|@LUHmD^(H`GAW{)R(6x_k!>*^j)BLqQv+y$8Z074M7 z$Im6k433O;b$qwo#zR-n4eEv_V^#f_`Hih>Eb`QxH}(wZ&AGd1MpsJYA02Dw btbzYJBNT*bi$3sTlBFHSnV(q?XL0`qH8Fj~ literal 0 HcmV?d00001 diff --git a/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_3914402253_2628201599.c b/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_3914402253_2628201599.c new file mode 100644 index 0000000..787d2f9 --- /dev/null +++ b/isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_3914402253_2628201599.c @@ -0,0 +1,221 @@ +/**********************************************************************/ +/* ____ ____ */ +/* / /\/ / */ +/* /___/ \ / */ +/* \ \ \/ */ +/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */ +/* / / All Right Reserved. */ +/* /---/ /\ */ +/* \ \ / \ */ +/* \___\/\___\ */ +/***********************************************************************/ + +/* This file is designed for use with ISim build 0xfbc00daa */ + +#define XSI_HIDE_SYMBOL_SPEC true +#include "xsi.h" +#include +#ifdef __GNUC__ +#include +#else +#include +#define alloca _alloca +#endif +static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd"; +extern char *IEEE_P_2592010699; + +unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char ); +unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char ); +unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char ); + + +static void work_a_3914402253_2628201599_p_0(char *t0) +{ + char *t1; + char *t2; + int t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + unsigned char t7; + char *t8; + char *t9; + char *t10; + char *t11; + char *t12; + char *t13; + +LAB0: xsi_set_current_line(32, ng0); + +LAB3: t1 = (t0 + 1032U); + t2 = *((char **)t1); + t3 = (31 - 31); + t4 = (t3 * -1); + t5 = (1U * t4); + t6 = (0 + t5); + t1 = (t2 + t6); + t7 = *((unsigned char *)t1); + t8 = (t0 + 4392); + t9 = (t8 + 56U); + t10 = *((char **)t9); + t11 = (t10 + 56U); + t12 = *((char **)t11); + *((unsigned char *)t12) = t7; + xsi_driver_first_trans_fast(t8); + +LAB2: t13 = (t0 + 4280); + *((int *)t13) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_3914402253_2628201599_p_1(char *t0) +{ + char *t1; + char *t2; + int t3; + unsigned int t4; + unsigned int t5; + unsigned int t6; + unsigned char t7; + char *t8; + char *t9; + char *t10; + char *t11; + char *t12; + char *t13; + +LAB0: xsi_set_current_line(33, ng0); + +LAB3: t1 = (t0 + 1192U); + t2 = *((char **)t1); + t3 = (31 - 31); + t4 = (t3 * -1); + t5 = (1U * t4); + t6 = (0 + t5); + t1 = (t2 + t6); + t7 = *((unsigned char *)t1); + t8 = (t0 + 4456); + t9 = (t8 + 56U); + t10 = *((char **)t9); + t11 = (t10 + 56U); + t12 = *((char **)t11); + *((unsigned char *)t12) = t7; + xsi_driver_first_trans_fast(t8); + +LAB2: t13 = (t0 + 4296); + *((int *)t13) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + +static void work_a_3914402253_2628201599_p_2(char *t0) +{ + char *t1; + char *t2; + unsigned char t3; + char *t4; + unsigned char t5; + unsigned char t6; + char *t7; + unsigned char t8; + char *t9; + unsigned char t10; + unsigned char t11; + char *t12; + unsigned char t13; + unsigned char t14; + char *t15; + unsigned char t16; + unsigned char t17; + unsigned char t18; + unsigned char t19; + char *t20; + unsigned char t21; + char *t22; + unsigned char t23; + unsigned char t24; + unsigned char t25; + char *t26; + unsigned char t27; + unsigned char t28; + char *t29; + unsigned char t30; + unsigned char t31; + unsigned char t32; + char *t33; + char *t34; + char *t35; + char *t36; + char *t37; + +LAB0: xsi_set_current_line(35, ng0); + +LAB3: t1 = (t0 + 1512U); + t2 = *((char **)t1); + t3 = *((unsigned char *)t2); + t1 = (t0 + 1992U); + t4 = *((char **)t1); + t5 = *((unsigned char *)t4); + t6 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t3, t5); + t1 = (t0 + 1672U); + t7 = *((char **)t1); + t8 = *((unsigned char *)t7); + t1 = (t0 + 1832U); + t9 = *((char **)t1); + t10 = *((unsigned char *)t9); + t11 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t10); + t1 = (t0 + 2152U); + t12 = *((char **)t1); + t13 = *((unsigned char *)t12); + t14 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t11, t13); + t1 = (t0 + 2312U); + t15 = *((char **)t1); + t16 = *((unsigned char *)t15); + t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16); + t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t14, t17); + t19 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t6, t18); + t1 = (t0 + 1672U); + t20 = *((char **)t1); + t21 = *((unsigned char *)t20); + t1 = (t0 + 1832U); + t22 = *((char **)t1); + t23 = *((unsigned char *)t22); + t24 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t23); + t25 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t21, t24); + t1 = (t0 + 2152U); + t26 = *((char **)t1); + t27 = *((unsigned char *)t26); + t28 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t25, t27); + t1 = (t0 + 2312U); + t29 = *((char **)t1); + t30 = *((unsigned char *)t29); + t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t28, t30); + t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t19, t31); + t1 = (t0 + 4520); + t33 = (t1 + 56U); + t34 = *((char **)t33); + t35 = (t34 + 56U); + t36 = *((char **)t35); + *((unsigned char *)t36) = t32; + xsi_driver_first_trans_fast_port(t1); + +LAB2: t37 = (t0 + 4312); + *((int *)t37) = 1; + +LAB1: return; +LAB4: goto LAB2; + +} + + +extern void work_a_3914402253_2628201599_init() +{ + static char *pe[] = {(void *)work_a_3914402253_2628201599_p_0,(void *)work_a_3914402253_2628201599_p_1,(void *)work_a_3914402253_2628201599_p_2}; + xsi_register_didat("work_a_3914402253_2628201599", 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[current_fileset -constrset] +add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]] +link_design +read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd" +if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} { + puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo" +} diff --git a/planAhead.ngc2edif.log b/planAhead.ngc2edif.log new file mode 100644 index 0000000..1e2bea2 --- /dev/null +++ b/planAhead.ngc2edif.log @@ -0,0 +1,12 @@ +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design SpecialCasesCheck.ngc ... +WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf, + ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file SpecialCasesCheck.edif ... +ngc2edif: Total memory usage is 103004 kilobytes + diff --git a/planAhead_pid7025.debug b/planAhead_pid7025.debug new file mode 100644 index 0000000..db27562 --- /dev/null +++ b/planAhead_pid7025.debug @@ -0,0 +1,92 @@ +#------------------------------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013 +# Current time: 8/24/19 2:52:26 PM +# Process ID: 7025 +# Platform: Unix +# +# This file is an indication that an internal application error occurred. +# This information is useful for debugging. Please open a case with Xilinx +# Technical Support with this file and a testcase attached. +#------------------------------------------------------------------------------- +8/24/19 2:52:26 PM +ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup() +HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR +HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR +HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR + + at ui.h.e.CF(SourceFile:217) + at ui.h.I.CF(SourceFile:702) + at ui.frmwork.HTclEventBroker.a(SourceFile:368) + at ui.frmwork.HTclEventBroker.bb(SourceFile:354) + at ui.project.a.een(SourceFile:759) + at ui.project.a.cleanup(SourceFile:608) + at ui.project.r.cleanup(SourceFile:631) + at ui.PlanAhead.aJj(SourceFile:335) + at ui.PlanAhead.a(SourceFile:1192) + at ui.frmwork.a.i.c(SourceFile:35) + at ui.frmwork.HTclEventBroker.a(SourceFile:233) + at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325) + at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method) + at ui.e.gY(SourceFile:195) + at ui.bl.run(SourceFile:882) + at ui.cd.run(SourceFile:1821) + at ui.views.F.aw.a(SourceFile:341) + at ui.cd.b(SourceFile:1809) + at ui.cd.a(SourceFile:1784) + at ui.PlanAhead.a(SourceFile:778) + at ui.aL.c(SourceFile:885) + at ui.aL.aHs(SourceFile:824) + at ui.bk.windowClosing(SourceFile:503) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349) + at java.awt.Window.processWindowEvent(Window.java:2051) + at javax.swing.JFrame.processWindowEvent(JFrame.java:296) + at java.awt.Window.processEvent(Window.java:2009) + at ui.aL.processEvent(SourceFile:1214) + at java.awt.Component.dispatchEventImpl(Component.java:4861) + at java.awt.Container.dispatchEventImpl(Container.java:2287) + at java.awt.Window.dispatchEventImpl(Window.java:2719) + at java.awt.Component.dispatchEvent(Component.java:4687) + at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729) + at java.awt.EventQueue.access$200(EventQueue.java:103) + at java.awt.EventQueue$3.run(EventQueue.java:688) + at java.awt.EventQueue$3.run(EventQueue.java:686) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87) + at java.awt.EventQueue$4.run(EventQueue.java:702) + at java.awt.EventQueue$4.run(EventQueue.java:700) + at java.security.AccessController.doPrivileged(Native Method) + at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76) + at java.awt.EventQueue.dispatchEvent(EventQueue.java:699) + at ui.frmwork.a.e.dispatchEvent(SourceFile:73) + at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242) + at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161) + at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146) + at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138) + at java.awt.EventDispatchThread.run(EventDispatchThread.java:91) + diff --git a/planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif b/planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif new file mode 100644 index 0000000..0d15b55 --- /dev/null +++ b/planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif @@ -0,0 +1,1762 @@ +(edif SpecialCasesCheck + (edifVersion 2 0 0) + (edifLevel 0) + (keywordMap (keywordLevel 0)) + (status + (written + (timestamp 2019 8 24 14 51 45) + (program "Xilinx ngc2edif" (version "P.20131013")) + (author "Xilinx. Inc ") + (comment "This EDIF netlist is to be used within supported synthesis tools") + (comment "for determining resource/timing estimates of the design component") + (comment "represented by this netlist.") + (comment "Command line: -mdp2sp -w -secure SpecialCasesCheck.ngc SpecialCasesCheck.edif "))) + (external UNISIMS + (edifLevel 0) + (technology (numberDefinition)) + (cell GND + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port G + (direction OUTPUT) + ) + ) + ) + ) + (cell VCC + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port P + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT4 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell MUXCY + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port CI + (direction INPUT) + ) + (port DI + (direction INPUT) + ) + (port S + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT6 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port I5 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT3 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell LUT5 + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I0 + (direction INPUT) + ) + (port I1 + (direction INPUT) + ) + (port I2 + (direction INPUT) + ) + (port I3 + (direction INPUT) + ) + (port I4 + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell IBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + (cell OBUF + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port I + (direction INPUT) + ) + (port O + (direction OUTPUT) + ) + ) + ) + ) + ) + + (library SpecialCasesCheck_lib + (edifLevel 0) + (technology (numberDefinition)) + (cell SpecialCasesCheck + (cellType GENERIC) + (view view_1 + (viewType NETLIST) + (interface + (port isNaN + (direction OUTPUT) + ) + (port isZero + (direction OUTPUT) + ) + (port (array (rename X "X<31:0>") 32) + (direction INPUT)) + (port (array (rename Y "Y<31:0>") 32) + (direction INPUT)) + (designator "xa6slx4-3-csg225") + (property TYPE (string "SpecialCasesCheck") (owner "Xilinx")) + (property BUS_INFO (string "32:INPUT:X<31:0>") (owner "Xilinx")) + (property BUS_INFO (string "32:INPUT:Y<31:0>") (owner "Xilinx")) + (property SHREG_MIN_SIZE (string "2") (owner "Xilinx")) + (property SHREG_EXTRACT_NGC (string "YES") (owner "Xilinx")) + (property NLW_UNIQUE_ID (integer 0) (owner "Xilinx")) + (property NLW_MACRO_TAG (integer 0) (owner "Xilinx")) + (property NLW_MACRO_ALIAS (string "SpecialCasesCheck_SpecialCasesCheck") (owner "Xilinx")) + ) + (contents + (instance XST_GND + (viewRef view_1 (cellRef GND (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance XST_VCC + (viewRef view_1 (cellRef VCC (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_lut_0__ "ZC/isZero_wg_lut<0>") + (viewRef view_1 (cellRef LUT4 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009") (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_cy_0__ "ZC/isZero_wg_cy<0>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_lut_1__ "ZC/isZero_wg_lut<1>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_cy_1__ "ZC/isZero_wg_cy<1>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_lut_2__ "ZC/isZero_wg_lut<2>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_cy_2__ "ZC/isZero_wg_cy<2>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_lut_3__ "ZC/isZero_wg_lut<3>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_cy_3__ "ZC/isZero_wg_cy<3>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_lut_4__ "ZC/isZero_wg_lut<4>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_cy_4__ "ZC/isZero_wg_cy<4>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_lut_5__ "ZC/isZero_wg_lut<5>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_cy_5__ "ZC/isZero_wg_cy<5>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_lut_6__ "ZC/isZero_wg_lut<6>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_cy_6__ "ZC/isZero_wg_cy<6>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_lut_7__ "ZC/isZero_wg_lut<7>") + (viewRef view_1 (cellRef LUT6 (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + (property INIT (string "9009000000009009") (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_cy_7__ "ZC/isZero_wg_cy<7>") + (viewRef view_1 (cellRef MUXCY (libraryRef UNISIMS))) + (property XSTLIB (boolean (true)) (owner "Xilinx")) + ) + (instance (rename ZC_isZero_wg_lut_8__ "ZC/isZero_wg_lut<8>") + (viewRef view_1 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isNaN_OBUF_renamed_75)) + ) + ) + (net isZero + (joined + (portRef isZero) + (portRef O (instanceRef isZero_OBUF_renamed_76)) + ) + ) + ) + ) + ) + ) + + (design SpecialCasesCheck + (cellRef SpecialCasesCheck + (libraryRef SpecialCasesCheck_lib) + ) + (property PART (string "xa6slx4-3-csg225") (owner "Xilinx")) + ) +) + diff --git a/planAhead_run_1/IEEE754Adder.data/constrs_1/fileset.xml b/planAhead_run_1/IEEE754Adder.data/constrs_1/fileset.xml new file mode 100644 index 0000000..7f16bae --- /dev/null +++ b/planAhead_run_1/IEEE754Adder.data/constrs_1/fileset.xml @@ -0,0 +1,16 @@ + + + + + + + + + + + + + + diff --git a/planAhead_run_1/IEEE754Adder.data/runs/impl_1.psg b/planAhead_run_1/IEEE754Adder.data/runs/impl_1.psg new file mode 100644 index 0000000..147f3a9 --- /dev/null +++ b/planAhead_run_1/IEEE754Adder.data/runs/impl_1.psg @@ -0,0 +1,20 @@ + + + + ISE Defaults, including packing registers in IOs off + + + + + + + + + + + + + + + + diff --git a/planAhead_run_1/IEEE754Adder.data/runs/runs.xml b/planAhead_run_1/IEEE754Adder.data/runs/runs.xml new file mode 100644 index 0000000..f573c93 --- /dev/null +++ b/planAhead_run_1/IEEE754Adder.data/runs/runs.xml @@ -0,0 +1,5 @@ + + + + + diff --git a/planAhead_run_1/IEEE754Adder.data/sim_1/fileset.xml b/planAhead_run_1/IEEE754Adder.data/sim_1/fileset.xml new file mode 100644 index 0000000..65babe3 --- /dev/null +++ b/planAhead_run_1/IEEE754Adder.data/sim_1/fileset.xml @@ -0,0 +1,10 @@ + + + + + + + diff --git a/planAhead_run_1/IEEE754Adder.data/sources_1/fileset.xml b/planAhead_run_1/IEEE754Adder.data/sources_1/fileset.xml new file mode 100644 index 0000000..468b3ce --- /dev/null +++ b/planAhead_run_1/IEEE754Adder.data/sources_1/fileset.xml @@ -0,0 +1,30 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/planAhead_run_1/IEEE754Adder.data/wt/java_command_handlers.wdf b/planAhead_run_1/IEEE754Adder.data/wt/java_command_handlers.wdf new file mode 100644 index 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+ + +
+
+ + + + + + + + + + + + + + + +
+ + diff --git a/planAhead_run_1/IEEE754Adder.ppr b/planAhead_run_1/IEEE754Adder.ppr new file mode 100644 index 0000000..f961cc1 --- /dev/null +++ b/planAhead_run_1/IEEE754Adder.ppr @@ -0,0 +1,28 @@ + + + + + + + + + + + + + diff --git a/planAhead_run_1/planAhead.jou b/planAhead_run_1/planAhead.jou new file mode 100644 index 0000000..915e2ff --- /dev/null +++ b/planAhead_run_1/planAhead.jou @@ -0,0 +1,10 @@ +#----------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013 +# Start of session at: Sat Aug 24 14:51:32 2019 +# Process ID: 7025 +# Log file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.log +# Journal file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.jou +#----------------------------------------------------------- +start_gui +source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl diff --git a/planAhead_run_1/planAhead.log b/planAhead_run_1/planAhead.log new file mode 100644 index 0000000..33e568b --- /dev/null +++ b/planAhead_run_1/planAhead.log @@ -0,0 +1,83 @@ +#----------------------------------------------------------- +# PlanAhead v14.7 (64-bit) +# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013 +# Start of session at: Sat Aug 24 14:51:32 2019 +# Process ID: 7025 +# Log file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.log +# Journal file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.jou +#----------------------------------------------------------- +INFO: [Common 17-78] Attempting to get a license: PlanAhead +INFO: [Common 17-290] Got license for PlanAhead +INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml +Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +start_gui +source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl +# create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3 +# set srcset [get_property srcset [current_run -impl]] +# set_property design_mode GateLvl $srcset +# set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ] +# add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} } +# set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset] +Adding file '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf' to fileset 'constrs_1' +# add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]] +# link_design +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +Design is defaulting to project part: xa6slx4csg225-3 +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design SpecialCasesCheck.ngc ... +WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf, + ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file SpecialCasesCheck.edif ... +ngc2edif: Total memory usage is 103004 kilobytes + +Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif] +Finished Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif] +Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockRegion.xml +Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockBuffers.xml +Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml... +Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/csg225/Package.xml +Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml +Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml +Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml +Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf] +Finished Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf] +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Phase 0 | Netlist Checksum: 684e9dfa +link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2835.180 ; gain = 156.531 +# read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd" +Release 14.7 - xdl P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings. +Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/. + "SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3 +Successfully converted design '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd' to '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xdl'. +INFO: [Designutils 20-669] Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd +INFO: [Designutils 20-658] Finished Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd +INFO: [Designutils 20-671] Placed 103 instances +read_xdl: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2835.180 ; gain = 0.000 +# if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} { +# puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo" +# } +exit +ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup() +HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR +HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR +HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR +HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR + (See /home/Luca/ISE/IEEE754Adder/planAhead_pid7025.debug) +ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors. +INFO: [Common 17-206] Exiting PlanAhead at Sat Aug 24 14:52:27 2019... +INFO: [Common 17-83] Releasing license: PlanAhead diff --git a/planAhead_run_1/planAhead_run.log b/planAhead_run_1/planAhead_run.log new file mode 100644 index 0000000..b66c313 --- /dev/null +++ b/planAhead_run_1/planAhead_run.log @@ -0,0 +1,74 @@ + +****** PlanAhead v14.7 (64-bit) + **** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013 + ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved. + +INFO: [Common 17-78] Attempting to get a license: PlanAhead +INFO: [Common 17-290] Got license for PlanAhead +INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml +Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml] +start_gui +source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl +# create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3 +# set srcset [get_property srcset [current_run -impl]] +# set_property design_mode GateLvl $srcset +# set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ] +# add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} } +# set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset] +Adding file '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf' to fileset 'constrs_1' +# add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]] +# link_design +Design is defaulting to srcset: sources_1 +Design is defaulting to constrset: constrs_1 +Design is defaulting to project part: xa6slx4csg225-3 +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +Release 14.7 - ngc2edif P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. +Reading design SpecialCasesCheck.ngc ... +WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf, + ignored. +Processing design ... + Preping design's networks ... + Preping design's macros ... + finished :Prep +Writing EDIF netlist file SpecialCasesCheck.edif ... +ngc2edif: Total memory usage is 103004 kilobytes + +Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif] +Finished Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif] +Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockRegion.xml +Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockBuffers.xml +Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml... +Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/csg225/Package.xml +Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml +Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml +Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml +Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf] +Finished Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf] +INFO: [Project 1-111] Unisim Transformation Summary: +No Unisim elements were transformed. + +Phase 0 | Netlist Checksum: 684e9dfa +link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2835.180 ; gain = 156.531 +# read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd" +Release 14.7 - xdl P.20131013 (lin64) +Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. + +WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings. +Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/. + "SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3 +Successfully converted design '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd' to '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xdl'. +INFO: [Designutils 20-669] Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd +INFO: [Designutils 20-658] Finished Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd +INFO: [Designutils 20-671] Placed 103 instances +read_xdl: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2835.180 ; gain = 0.000 +# if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} { +# puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo" +# } +exit +ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors. +INFO: [Common 17-206] Exiting PlanAhead at Sat Aug 24 14:52:27 2019... +INFO: [Common 17-83] Releasing license: PlanAhead