diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise
index 5c73487..a431073 100644
--- a/IEEE754Adder.xise
+++ b/IEEE754Adder.xise
@@ -43,7 +43,7 @@
     </file>
     <file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
     </file>
     <file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -53,7 +53,7 @@
     </file>
     <file xil_pn:name="PrepareForShift.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="Swap.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
@@ -81,11 +81,11 @@
     </file>
     <file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
     </file>
     <file xil_pn:name="AddSubTest.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
@@ -99,7 +99,15 @@
     </file>
     <file xil_pn:name="ShiftRight.vhd" xil_pn:type="FILE_VHDL">
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="207"/>
-      <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="SumDataAdapter.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="255"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
+    <file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="256"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
     </file>
   </files>
 
@@ -221,9 +229,9 @@
     <property xil_pn:name="ISim UUT Instance Name" xil_pn:value="UUT" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Ignore User Timing Constraints Par" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|ShiftRight48|ShiftRightArch" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top File" xil_pn:value="ShiftRight.vhd" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/ShiftRight48" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top" xil_pn:value="Architecture|PrepareForShift|PrepareForShiftArch" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top File" xil_pn:value="PrepareForShift.vhd" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Implementation Top Instance Path" xil_pn:value="/PrepareForShift" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Include 'uselib Directive in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include SIMPRIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -292,7 +300,7 @@
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-    <property xil_pn:name="Output File Name" xil_pn:value="ShiftRight48" xil_pn:valueState="default"/>
+    <property xil_pn:name="Output File Name" xil_pn:value="PrepareForShift" xil_pn:valueState="default"/>
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -307,10 +315,10 @@
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="ShiftRight48_map.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="ShiftRight48_timesim.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="ShiftRight48_synthesis.v" xil_pn:valueState="default"/>
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="ShiftRight48_translate.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="PrepareForShift_map.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="PrepareForShift_timesim.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="PrepareForShift_synthesis.v" xil_pn:valueState="default"/>
+    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="PrepareForShift_translate.v" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
diff --git a/Normalizer.vhd b/Normalizer.vhd
new file mode 100644
index 0000000..b817642
--- /dev/null
+++ b/Normalizer.vhd
@@ -0,0 +1,22 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity Normalizer is
+
+	port(
+		SIGN : in std_logic;
+		EXP : in std_logic_vector(7 downto 0);
+		MANT : in std_logic_vector(47 downto 0);
+		OVERFLOW : in std_logic;
+		IEEE_754_SUM : out std_logic_vector(31 downto 0)
+	);
+	
+end Normalizer;
+
+architecture NormalizerArch of Normalizer is
+
+begin
+
+
+end NormalizerArch;
+
diff --git a/ShiftRight.vhd b/ShiftRight.vhd
index 1e7f9e0..037c032 100644
--- a/ShiftRight.vhd
+++ b/ShiftRight.vhd
@@ -6,7 +6,7 @@ entity ShiftRight48 is
 	
 	port(
 		N : in std_logic_vector(47 downto 0);
-		PLACES : in std_logic_vector(5 downto 0);
+		PLACES : in std_logic_vector(8 downto 0);
 		RESULT : out std_logic_vector(47 downto 0)
 	);
 
@@ -20,53 +20,53 @@ begin
 	asdf: process (N, PLACES)
 	begin
 		case PLACES is
-			when "000000" => RESULT <= N( 47 downto 0 );
-			when "000001" => RESULT <= "0" & N( 47 downto 1 );
-			when "000010" => RESULT <= "00" & N( 47 downto 2 );
-			when "000011" => RESULT <= "000" & N( 47 downto 3 );
-			when "000100" => RESULT <= "0000" & N( 47 downto 4 );
-			when "000101" => RESULT <= "00000" & N( 47 downto 5 );
-			when "000110" => RESULT <= "000000" & N( 47 downto 6 );
-			when "000111" => RESULT <= "0000000" & N( 47 downto 7 );
-			when "001000" => RESULT <= "00000000" & N( 47 downto 8 );
-			when "001001" => RESULT <= "000000000" & N( 47 downto 9 );
-			when "001010" => RESULT <= "0000000000" & N( 47 downto 10 );
-			when "001011" => RESULT <= "00000000000" & N( 47 downto 11 );
-			when "001100" => RESULT <= "000000000000" & N( 47 downto 12 );
-			when "001101" => RESULT <= "0000000000000" & N( 47 downto 13 );
-			when "001110" => RESULT <= "00000000000000" & N( 47 downto 14 );
-			when "001111" => RESULT <= "000000000000000" & N( 47 downto 15 );
-			when "010000" => RESULT <= "0000000000000000" & N( 47 downto 16 );
-			when "010001" => RESULT <= "00000000000000000" & N( 47 downto 17 );
-			when "010010" => RESULT <= "000000000000000000" & N( 47 downto 18 );
-			when "010011" => RESULT <= "0000000000000000000" & N( 47 downto 19 );
-			when "010100" => RESULT <= "00000000000000000000" & N( 47 downto 20 );
-			when "010101" => RESULT <= "000000000000000000000" & N( 47 downto 21 );
-			when "010110" => RESULT <= "0000000000000000000000" & N( 47 downto 22 );
-			when "010111" => RESULT <= "00000000000000000000000" & N( 47 downto 23 );
-			when "011000" => RESULT <= "000000000000000000000000" & N( 47 downto 24 );
-			when "011001" => RESULT <= "0000000000000000000000000" & N( 47 downto 25 );
-			when "011010" => RESULT <= "00000000000000000000000000" & N( 47 downto 26 );
-			when "011011" => RESULT <= "000000000000000000000000000" & N( 47 downto 27 );
-			when "011100" => RESULT <= "0000000000000000000000000000" & N( 47 downto 28 );
-			when "011101" => RESULT <= "00000000000000000000000000000" & N( 47 downto 29 );
-			when "011110" => RESULT <= "000000000000000000000000000000" & N( 47 downto 30 );
-			when "011111" => RESULT <= "0000000000000000000000000000000" & N( 47 downto 31 );
-			when "100000" => RESULT <= "00000000000000000000000000000000" & N( 47 downto 32 );
-			when "100001" => RESULT <= "000000000000000000000000000000000" & N( 47 downto 33 );
-			when "100010" => RESULT <= "0000000000000000000000000000000000" & N( 47 downto 34 );
-			when "100011" => RESULT <= "00000000000000000000000000000000000" & N( 47 downto 35 );
-			when "100100" => RESULT <= "000000000000000000000000000000000000" & N( 47 downto 36 );
-			when "100101" => RESULT <= "0000000000000000000000000000000000000" & N( 47 downto 37 );
-			when "100110" => RESULT <= "00000000000000000000000000000000000000" & N( 47 downto 38 );
-			when "100111" => RESULT <= "000000000000000000000000000000000000000" & N( 47 downto 39 );
-			when "101000" => RESULT <= "0000000000000000000000000000000000000000" & N( 47 downto 40 );
-			when "101001" => RESULT <= "00000000000000000000000000000000000000000" & N( 47 downto 41 );
-			when "101010" => RESULT <= "000000000000000000000000000000000000000000" & N( 47 downto 42 );
-			when "101011" => RESULT <= "0000000000000000000000000000000000000000000" & N( 47 downto 43 );
-			when "101100" => RESULT <= "00000000000000000000000000000000000000000000" & N( 47 downto 44 );
-			when "101101" => RESULT <= "000000000000000000000000000000000000000000000" & N( 47 downto 45 );
-			when "101110" => RESULT <= "0000000000000000000000000000000000000000000000" & N( 47 downto 46 );
+			when "000000000" => RESULT <= N( 47 downto 0 );
+			when "000000001" => RESULT <= "0" & N( 47 downto 1 );
+			when "000000010" => RESULT <= "00" & N( 47 downto 2 );
+			when "000000011" => RESULT <= "000" & N( 47 downto 3 );
+			when "000000100" => RESULT <= "0000" & N( 47 downto 4 );
+			when "000000101" => RESULT <= "00000" & N( 47 downto 5 );
+			when "000000110" => RESULT <= "000000" & N( 47 downto 6 );
+			when "000000111" => RESULT <= "0000000" & N( 47 downto 7 );
+			when "000001000" => RESULT <= "00000000" & N( 47 downto 8 );
+			when "000001001" => RESULT <= "000000000" & N( 47 downto 9 );
+			when "000001010" => RESULT <= "0000000000" & N( 47 downto 10 );
+			when "000001011" => RESULT <= "00000000000" & N( 47 downto 11 );
+			when "000001100" => RESULT <= "000000000000" & N( 47 downto 12 );
+			when "000001101" => RESULT <= "0000000000000" & N( 47 downto 13 );
+			when "000001110" => RESULT <= "00000000000000" & N( 47 downto 14 );
+			when "000001111" => RESULT <= "000000000000000" & N( 47 downto 15 );
+			when "000010000" => RESULT <= "0000000000000000" & N( 47 downto 16 );
+			when "000010001" => RESULT <= "00000000000000000" & N( 47 downto 17 );
+			when "000010010" => RESULT <= "000000000000000000" & N( 47 downto 18 );
+			when "000010011" => RESULT <= "0000000000000000000" & N( 47 downto 19 );
+			when "000010100" => RESULT <= "00000000000000000000" & N( 47 downto 20 );
+			when "000010101" => RESULT <= "000000000000000000000" & N( 47 downto 21 );
+			when "000010110" => RESULT <= "0000000000000000000000" & N( 47 downto 22 );
+			when "000010111" => RESULT <= "00000000000000000000000" & N( 47 downto 23 );
+			when "000011000" => RESULT <= "000000000000000000000000" & N( 47 downto 24 );
+			when "000011001" => RESULT <= "0000000000000000000000000" & N( 47 downto 25 );
+			when "000011010" => RESULT <= "00000000000000000000000000" & N( 47 downto 26 );
+			when "000011011" => RESULT <= "000000000000000000000000000" & N( 47 downto 27 );
+			when "000011100" => RESULT <= "0000000000000000000000000000" & N( 47 downto 28 );
+			when "000011101" => RESULT <= "00000000000000000000000000000" & N( 47 downto 29 );
+			when "000011110" => RESULT <= "000000000000000000000000000000" & N( 47 downto 30 );
+			when "000011111" => RESULT <= "0000000000000000000000000000000" & N( 47 downto 31 );
+			when "000100000" => RESULT <= "00000000000000000000000000000000" & N( 47 downto 32 );
+			when "000100001" => RESULT <= "000000000000000000000000000000000" & N( 47 downto 33 );
+			when "000100010" => RESULT <= "0000000000000000000000000000000000" & N( 47 downto 34 );
+			when "000100011" => RESULT <= "00000000000000000000000000000000000" & N( 47 downto 35 );
+			when "000100100" => RESULT <= "000000000000000000000000000000000000" & N( 47 downto 36 );
+			when "000100101" => RESULT <= "0000000000000000000000000000000000000" & N( 47 downto 37 );
+			when "000100110" => RESULT <= "00000000000000000000000000000000000000" & N( 47 downto 38 );
+			when "000100111" => RESULT <= "000000000000000000000000000000000000000" & N( 47 downto 39 );
+			when "000101000" => RESULT <= "0000000000000000000000000000000000000000" & N( 47 downto 40 );
+			when "000101001" => RESULT <= "00000000000000000000000000000000000000000" & N( 47 downto 41 );
+			when "000101010" => RESULT <= "000000000000000000000000000000000000000000" & N( 47 downto 42 );
+			when "000101011" => RESULT <= "0000000000000000000000000000000000000000000" & N( 47 downto 43 );
+			when "000101100" => RESULT <= "00000000000000000000000000000000000000000000" & N( 47 downto 44 );
+			when "000101101" => RESULT <= "000000000000000000000000000000000000000000000" & N( 47 downto 45 );
+			when "000101110" => RESULT <= "0000000000000000000000000000000000000000000000" & N( 47 downto 46 );
 			when others   => RESULT <= "000000000000000000000000000000000000000000000000";
 		end case;
 	end process;
diff --git a/SumDataAdapter.vhd b/SumDataAdapter.vhd
new file mode 100644
index 0000000..57586f2
--- /dev/null
+++ b/SumDataAdapter.vhd
@@ -0,0 +1,55 @@
+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+entity SumDataAdapter is
+
+	port(
+		X_IN, Y_IN : in std_logic_vector(30 downto 0);
+		DIFF_EXP : in std_logic_vector(8 downto 0);
+		X_OUT, Y_OUT : out std_logic_vector(47 downto 0)
+	);
+	
+end SumDataAdapter;
+
+architecture SumDataAdapterArch of SumDataAdapter is
+
+	signal X_FST_BIT : std_logic;
+	signal Y_FST_BIT : std_logic;
+	
+	component ShiftRight48 is
+	
+		port(
+			N : in std_logic_vector(47 downto 0);
+			PLACES : in std_logic_vector(8 downto 0);
+			RESULT : out std_logic_vector(47 downto 0)
+		);
+
+	end component;
+	
+begin
+
+	X_Y_FST_BIT_PROCESS : process (X_IN, Y_IN)
+		
+		variable X_FST_TMP : std_logic := '0';
+		variable Y_FST_TMP : std_logic := '0';
+		
+	begin
+	
+		for i in 30 downto 23 loop
+			X_FST_TMP := X_FST_TMP or X_IN(i);
+			Y_FST_TMP := Y_FST_TMP or Y_IN(i);
+		end loop;
+		
+		X_FST_BIT <= X_FST_TMP;
+		Y_FST_BIT <= Y_FST_TMP;
+	
+	end process;
+	
+	--istanziare shifter
+	SHIFTER : ShiftRight48
+		port map (N -> Y_FST_BIT & Y_IN(22 downto 0) & "000000000000000000000000", PLACES -> DIFF_EXP, RESULT -> Y_OUT);
+
+	X_OUT <= X_FST_BIT & X_IN(22 downto 0) & "000000000000000000000000";
+	
+end SumDataAdapterArch;
+