lucacuzzocrea/IEEE754Adder
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Completato check casi speciali + test

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Luca Cuzzocrea
2019-08-24 14:39:01 +02:00
parent cd358fae35
commit c6ef95462a
143 changed files with 21122 additions and 224 deletions
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13
webtalk_pn.xml
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@@ -3,11 +3,11 @@
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pn" timeStamp="Sat Aug 17 17:19:19 2019">
<application name="pn" timeStamp="Sat Aug 24 12:14:25 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="4B48FA10A560F77F46DA66FD7F346092" type="project"/>
<property name="ProjectIteration" value="0" type="project"/>
<property name="ProjectFile" value="/home/ise/gianni/IEEE754Adder/IEEE754Adder.xise" type="project"/>
<property name="ProjectIteration" value="5" type="project"/>
<property name="ProjectFile" value="/home/Luca/ISE/IEEE754Adder/IEEE754Adder.xise" type="project"/>
<property name="ProjectCreationTimestamp" value="2019-08-17T16:51:15" type="project"/>
</section>
<section name="Project Statistics" visible="true">
@@ -17,6 +17,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_LastAppliedStrategy" value="Xilinx Default (unlocked)" type="design"/>
<property name="PROP_ManualCompileOrderImp" value="false" type="design"/>
<property name="PROP_PropSpecInProjFile" value="Store all values" type="design"/>
<property name="PROP_SelectedInstanceHierarchicalPath" value="/SpecialCasesTest/uut/NC" type="process"/>
<property name="PROP_Simulator" value="ISim (VHDL/Verilog)" type="design"/>
<property name="PROP_SynthTopFile" value="changed" type="process"/>
<property name="PROP_Top_Level_Module_Type" value="HDL" type="design"/>
@@ -25,15 +26,17 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_UserConstraintEditorPreference" value="Text Editor" type="process"/>
<property name="PROP_intProjectCreationTimestamp" value="2019-08-17T16:51:15" type="design"/>
<property name="PROP_intWbtProjectID" value="4B48FA10A560F77F46DA66FD7F346092" type="design"/>
<property name="PROP_intWbtProjectIteration" value="5" type="process"/>
<property name="PROP_intWorkingDirLocWRTProjDir" value="Same" type="design"/>
<property name="PROP_intWorkingDirUsed" value="No" type="design"/>
<property name="PROP_selectedSimRootSourceNode_behav" value="work.NaNCheck" type="process"/>
<property name="PROP_xilxBitgStart_IntDone" value="true" type="process"/>
<property name="PROP_xilxSynthAddBufg_spartan6" value="32" type="process"/>
<property name="PROP_xstUseClockEnable_spartan6" value="Yes" type="process"/>
<property name="PROP_xstUseSyncReset_spartan6" value="Yes" type="process"/>
<property name="PROP_xstUseSyncSet_spartan6" value="Yes" type="process"/>
<property name="PROPEXT_mapTimingMode_spartan6" value="Non Timing Driven" type="process"/>
<property name="PROP_AutoTop" value="true" type="design"/>
<property name="PROP_AutoTop" value="false" type="design"/>
<property name="PROP_DevFamily" value="Automotive Spartan6" type="design"/>
<property name="PROP_DevDevice" value="xa6slx4" type="design"/>
<property name="PROP_DevFamilyPMName" value="aspartan6" type="design"/>
@@ -41,7 +44,7 @@ This means code written to parse this file will need to be revisited each subseq
<property name="PROP_Synthesis_Tool" value="XST (VHDL/Verilog)" type="design"/>
<property name="PROP_DevSpeed" value="-3" type="design"/>
<property name="PROP_PreferredLanguage" value="VHDL" type="design"/>
<property name="FILE_VHDL" value="3" type="source"/>
<property name="FILE_VHDL" value="6" type="source"/>
</section>
</application>
</document>