Completato check casi speciali + test
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SpecialCasesCheck_map.mrp
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SpecialCasesCheck_map.mrp
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Release 14.7 Map P.20131013 (lin64)
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Xilinx Mapping Report File for Design 'SpecialCasesCheck'
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Design Information
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------------------
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Command Line : map -intstyle ise -p xa6slx4-csg225-3 -w -logic_opt off -ol
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high -t 1 -xt 0 -register_duplication off -r 4 -global_opt off -mt off -ir off
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-pr off -lc off -power off -o SpecialCasesCheck_map.ncd SpecialCasesCheck.ngd
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SpecialCasesCheck.pcf
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Target Device : xa6slx4
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Target Package : csg225
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Target Speed : -3
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Mapper Version : aspartan6 -- $Revision: 1.55 $
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Mapped Date : Sat Aug 24 12:14:20 2019
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Design Summary
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--------------
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Number of errors: 0
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Number of warnings: 0
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Slice Logic Utilization:
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Number of Slice Registers: 0 out of 4,800 0%
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Number of Slice LUTs: 26 out of 2,400 1%
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Number used as logic: 26 out of 2,400 1%
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Number using O6 output only: 25
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Number using O5 output only: 0
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Number using O5 and O6: 1
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Number used as ROM: 0
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Number used as Memory: 0 out of 1,200 0%
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Slice Logic Distribution:
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Number of occupied Slices: 10 out of 600 1%
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Number of MUXCYs used: 12 out of 1,200 1%
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Number of LUT Flip Flop pairs used: 26
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Number with an unused Flip Flop: 26 out of 26 100%
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Number with an unused LUT: 0 out of 26 0%
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Number of fully used LUT-FF pairs: 0 out of 26 0%
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Number of slice register sites lost
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to control set restrictions: 0 out of 4,800 0%
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A LUT Flip Flop pair for this architecture represents one LUT paired with
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one Flip Flop within a slice. A control set is a unique combination of
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clock, reset, set, and enable signals for a registered element.
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The Slice Logic Distribution report is not meaningful if the design is
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over-mapped for a non-slice resource or if Placement fails.
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IO Utilization:
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Number of bonded IOBs: 66 out of 132 50%
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Specific Feature Utilization:
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Number of RAMB16BWERs: 0 out of 12 0%
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Number of RAMB8BWERs: 0 out of 24 0%
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Number of BUFIO2/BUFIO2_2CLKs: 0 out of 32 0%
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Number of BUFIO2FB/BUFIO2FB_2CLKs: 0 out of 32 0%
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Number of BUFG/BUFGMUXs: 0 out of 16 0%
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Number of DCM/DCM_CLKGENs: 0 out of 4 0%
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Number of ILOGIC2/ISERDES2s: 0 out of 200 0%
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Number of IODELAY2/IODRP2/IODRP2_MCBs: 0 out of 200 0%
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Number of OLOGIC2/OSERDES2s: 0 out of 200 0%
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Number of BSCANs: 0 out of 4 0%
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Number of BUFHs: 0 out of 128 0%
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Number of BUFPLLs: 0 out of 8 0%
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Number of BUFPLL_MCBs: 0 out of 4 0%
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Number of DSP48A1s: 0 out of 8 0%
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Number of ICAPs: 0 out of 1 0%
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Number of PCILOGICSEs: 0 out of 2 0%
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Number of PLL_ADVs: 0 out of 2 0%
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Number of PMVs: 0 out of 1 0%
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Number of STARTUPs: 0 out of 1 0%
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Number of SUSPEND_SYNCs: 0 out of 1 0%
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Average Fanout of Non-Clock Nets: 1.78
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Peak Memory Usage: 734 MB
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Total REAL time to MAP completion: 5 secs
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Total CPU time to MAP completion: 5 secs
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Table of Contents
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-----------------
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Section 1 - Errors
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Section 2 - Warnings
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Section 3 - Informational
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Section 4 - Removed Logic Summary
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Section 5 - Removed Logic
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Section 6 - IOB Properties
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Section 7 - RPMs
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Section 8 - Guide Report
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Section 9 - Area Group and Partition Summary
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Section 10 - Timing Report
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Section 11 - Configuration String Information
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Section 12 - Control Set Information
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Section 13 - Utilization by Hierarchy
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Section 1 - Errors
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------------------
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Section 2 - Warnings
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--------------------
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Section 3 - Informational
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-------------------------
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INFO:LIT:244 - All of the single ended outputs in this design are using slew
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rate limited output drivers. The delay on speed critical single ended outputs
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can be dramatically reduced by designating them as fast outputs.
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INFO:Pack:1716 - Initializing temperature to 100.000 Celsius. (default - Range:
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-40.000 to 100.000 Celsius)
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INFO:Pack:1720 - Initializing voltage to 1.140 Volts. (default - Range: 1.140 to
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1.260 Volts)
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INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
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(.mrp).
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INFO:Pack:1650 - Map created a placed design.
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Section 4 - Removed Logic Summary
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---------------------------------
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2 block(s) optimized away
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Section 5 - Removed Logic
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-------------------------
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Optimized Block(s):
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TYPE BLOCK
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GND XST_GND
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VCC XST_VCC
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Section 6 - IOB Properties
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--------------------------
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+---------------------------------------------------------------------------------------------------------------------------------------------------------+
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| IOB Name | Type | Direction | IO Standard | Diff | Drive | Slew | Reg (s) | Resistor | IOB |
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| | | | | Term | Strength | Rate | | | Delay |
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+---------------------------------------------------------------------------------------------------------------------------------------------------------+
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| X<0> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<1> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<2> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<3> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<4> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<5> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<6> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<7> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<8> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<9> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<10> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<11> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<12> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<13> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<14> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<15> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<16> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<17> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<18> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<19> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<20> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<21> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<22> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<23> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<24> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<25> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<26> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<27> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<28> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<29> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<30> | IOB | INPUT | LVCMOS25 | | | | | | |
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| X<31> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<0> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<1> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<2> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<3> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<4> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<5> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<6> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<7> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<8> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<9> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<10> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<11> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<12> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<13> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<14> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<15> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<16> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<17> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<18> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<19> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<20> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<21> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<22> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<23> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<24> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<25> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<26> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<27> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<28> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<29> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<30> | IOB | INPUT | LVCMOS25 | | | | | | |
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| Y<31> | IOB | INPUT | LVCMOS25 | | | | | | |
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| isNaN | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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| isZero | IOB | OUTPUT | LVCMOS25 | | 12 | SLOW | | | |
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+---------------------------------------------------------------------------------------------------------------------------------------------------------+
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Section 7 - RPMs
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----------------
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Section 8 - Guide Report
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------------------------
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Guide not run on this design.
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Section 9 - Area Group and Partition Summary
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--------------------------------------------
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Partition Implementation Status
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-------------------------------
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No Partitions were found in this design.
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-------------------------------
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Area Group Information
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----------------------
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No area groups were found in this design.
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----------------------
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Section 10 - Timing Report
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--------------------------
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A logic-level (pre-route) timing report can be generated by using Xilinx static
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timing analysis tools, Timing Analyzer (GUI) or TRCE (command line), with the
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mapped NCD and PCF files. Please note that this timing report will be generated
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using estimated delay information. For accurate numbers, please generate a
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timing report with the post Place and Route NCD file.
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For more information about the Timing Analyzer, consult the Xilinx Timing
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Analyzer Reference Manual; for more information about TRCE, consult the Xilinx
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Command Line Tools User Guide "TRACE" chapter.
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Section 11 - Configuration String Details
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-----------------------------------------
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Use the "-detail" map option to print out Configuration Strings
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Section 12 - Control Set Information
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------------------------------------
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Use the "-detail" map option to print out Control Set Information.
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Section 13 - Utilization by Hierarchy
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-------------------------------------
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Use the "-detail" map option to print out the Utilization by Hierarchy section.
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