diff --git a/EqualCheck.vhd b/EqualCheck.vhd
index 15cd1ba..7e50fc8 100644
--- a/EqualCheck.vhd
+++ b/EqualCheck.vhd
@@ -1,28 +1,42 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity EqualCheck is
-	generic( BITCOUNT: integer := 8 );
-	port(
-		X, Y: in std_logic_vector( (BITCOUNT-1) downto 0 );
-		isEqual: out std_logic
-	);
-end EqualCheck;
-
-architecture EqualCheckArch of EqualCheck is
-	signal compVec: std_logic_vector( (BITCOUNT-1) downto 0 );
-begin
-	compVec <= X xor Y;
-	
-	res_compute: process (compVec)
-		variable res_tmp: std_logic;
-	begin
-		res_tmp := '0';
-		for i in compVec'range loop
-			res_tmp := res_tmp or compVec(i);
-		end loop;
-		isEqual <= not res_tmp;
-	end process;
-
-end EqualCheckArch;
-
+library IEEE;

+use IEEE.STD_LOGIC_1164.ALL;

+

+entity EqualCheck is
+

+	generic(
+		BITCOUNT: integer := 8
+	);
+	

+	port(

+		X, Y : in std_logic_vector((BITCOUNT-1) downto 0);

+		IS_EQUAL : out std_logic

+	);
+	

+end EqualCheck;

+
+architecture EqualCheckArch of EqualCheck is
+

+	signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
+

+begin
+

+	COMP_VEC <= X xor Y;

+	

+	RES_COMPUTE: process (COMP_VEC)
+	

+		variable RES_TMP : std_logic;
+		

+	begin
+	

+		RES_TMP := '0';
+		

+		for i in COMP_VEC'range loop

+			RES_TMP := RES_TMP or COMP_VEC(i);

+		end loop;
+		

+		IS_EQUAL <= not RES_TMP;
+		

+	end process;

+

+end EqualCheckArch;

+

diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise
index 674c31d..da138d4 100644
--- a/IEEE754Adder.xise
+++ b/IEEE754Adder.xise
@@ -1,906 +1,444 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no" ?>
-
 <project xmlns="http://www.xilinx.com/XMLSchema" xmlns:xil_pn="http://www.xilinx.com/XMLSchema">
 
-
-
   <header>
-
     <!-- ISE source project file created by Project Navigator.             -->
-
     <!--                                                                   -->
-
     <!-- This file contains project source information including a list of -->
-
     <!-- project source files, project and process properties.  This file, -->
-
     <!-- along with the project source files, is sufficient to open and    -->
-
     <!-- implement in ISE Project Navigator.                               -->
-
     <!--                                                                   -->
-
     <!-- Copyright (c) 1995-2013 Xilinx, Inc.  All rights reserved. -->
-
   </header>
 
-
-
   <version xil_pn:ise_version="14.7" xil_pn:schema_version="2"/>
 
-
-
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     <file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
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     </file>
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     <file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
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     </file>
-
     <file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
-
       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
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     </file>
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     <file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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       <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
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     </file>
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     <file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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       <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
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     </file>
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     <file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
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       <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
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     </file>
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     <file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
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+    <file xil_pn:name="OperationCheck.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="Implementation" xil_pn:seqID="0"/>
+    </file>
     <file xil_pn:name="TwoComplementTest.vhd" xil_pn:type="FILE_VHDL">
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-    <property xil_pn:name="Device Family" xil_pn:value="Automotive Spartan6" xil_pn:valueState="non-default"/>
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     <property xil_pn:name="Include UNISIM Models in Verilog File" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Include sdf_annotate task in Verilog File" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Incremental Compilation" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Insert Buffers to Prevent Pulse Swallowing" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Instantiation Template Target Language Xps" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-
     <property xil_pn:name="JTAG Pin TCK" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-
     <property xil_pn:name="JTAG Pin TDI" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-
     <property xil_pn:name="JTAG Pin TDO" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-
     <property xil_pn:name="JTAG Pin TMS" xil_pn:value="Pull Up" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Keep Hierarchy" xil_pn:value="No" xil_pn:valueState="default"/>
-
     <property xil_pn:name="LUT Combining Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-
     <property xil_pn:name="LUT Combining Xst" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Language" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Last Applied Goal" xil_pn:value="Balanced" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Last Applied Strategy" xil_pn:value="Xilinx Default (unlocked)" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Last Unlock Status" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Launch SDK after Export" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Library for Verilog Sources" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Load glbl" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Logical Shifter Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Manual Implementation Compile Order" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Map Slice Logic into Unused Block RAMs" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Mask Pins for Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="0x00" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Max Fanout" xil_pn:value="100000" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Maximum Compression" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Maximum Number of Lines in Report" xil_pn:value="1000" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Maximum Signal Name Length" xil_pn:value="20" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Move First Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Move Last Flip-Flop Stage" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="MultiBoot: Insert IPROG CMD in the Bitfile spartan6" xil_pn:value="Enable" xil_pn:valueState="default"/>
-
     <property xil_pn:name="MultiBoot: Next Configuration Mode spartan6" xil_pn:value="001" xil_pn:valueState="default"/>
-
     <property xil_pn:name="MultiBoot: Starting Address for Golden Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-
     <property xil_pn:name="MultiBoot: Starting Address for Next Configuration spartan6" xil_pn:value="0x00000000" xil_pn:valueState="default"/>
-
     <property xil_pn:name="MultiBoot: Use New Mode for Next Configuration spartan6" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="MultiBoot: User-Defined Register for Failsafe Scheme spartan6" xil_pn:value="0x0000" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Multiplier Style" xil_pn:value="LUT" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Mux Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Optimization Effort spartan6" xil_pn:value="Normal" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Optimization Goal" xil_pn:value="Speed" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Optimization Strategy (Cover Mode)" xil_pn:value="Area" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Optimize Instantiated Primitives" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Bitgen Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Bitgen Command Line Options spartan6" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Compiler Options" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Compiler Options Map" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Compiler Options Par" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Compiler Options Translate" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Compxlib Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Map Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other NETGEN Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Ngdbuild Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Place &amp; Route Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Simulator Commands Behavioral" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Simulator Commands Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Simulator Commands Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other Simulator Commands Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other XPWR Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Other XST Command Line Options" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Output Extended Identifiers" xil_pn:value="false" xil_pn:valueState="default"/>
-
-    <property xil_pn:name="Output File Name" xil_pn:value="TwoComplement" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Output File Name" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Overwrite Compiled Libraries" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Pack I/O Registers into IOBs" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Pack I/O Registers/Latches into IOBs" xil_pn:value="Off" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Package" xil_pn:value="csg225" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Perform Advanced Analysis" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Perform Advanced Analysis Post Trace" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Perform Timing-Driven Packing and Placement" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Place &amp; Route Effort Level (Overall)" xil_pn:value="High" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Place And Route Mode" xil_pn:value="Normal Place and Route" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Place MultiBoot Settings into Bitstream spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Placer Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Placer Effort Level Map" xil_pn:value="High" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Placer Extra Effort Map" xil_pn:value="None" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Port to be used" xil_pn:value="Auto - default" xil_pn:valueState="default"/>
-
-    <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="TwoComplement_map.vhd" xil_pn:valueState="default"/>
-
-    <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="TwoComplement_timesim.vhd" xil_pn:valueState="default"/>
-
-    <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="TwoComplement_synthesis.vhd" xil_pn:valueState="default"/>
-
-    <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="TwoComplement_translate.vhd" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Post Map Simulation Model Name" xil_pn:value="SpecialCasesCheck_map.vhd" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Post Place &amp; Route Simulation Model Name" xil_pn:value="SpecialCasesCheck_timesim.vhd" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Post Synthesis Simulation Model Name" xil_pn:value="SpecialCasesCheck_synthesis.vhd" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Post Translate Simulation Model Name" xil_pn:value="SpecialCasesCheck_translate.vhd" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Power Reduction Map" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Power Reduction Map spartan6" xil_pn:value="Off" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Power Reduction Par" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Power Reduction Xst" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Preferred Language" xil_pn:value="VHDL" xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="Priority Encoder Extraction" xil_pn:value="Yes" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Produce Verbose Report" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Project Description" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Project Generator" xil_pn:value="ProjNav" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Property Specification in Project File" xil_pn:value="Store all values" xil_pn:valueState="default"/>
-
     <property xil_pn:name="RAM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="RAM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="ROM Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="ROM Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Read Cores" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Reduce Control Sets" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Regenerate Core" xil_pn:value="Under Current Project Setting" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Register Balancing" xil_pn:value="No" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Register Duplication Map" xil_pn:value="Off" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Register Duplication Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Register Ordering spartan6" xil_pn:value="4" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Release Write Enable (Output Events)" xil_pn:value="Default (6)" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Rename Design Instance in Testbench File to" xil_pn:value="UUT" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Rename Top Level Architecture To" xil_pn:value="Structure" xil_pn:valueState="default"/>
-
-    <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="TwoComplement" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Rename Top Level Entity to" xil_pn:value="SpecialCasesCheck" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Rename Top Level Module To" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Report Fastest Path(s) in Each Constraint Post Trace" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Report Paths by Endpoint" xil_pn:value="3" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Report Paths by Endpoint Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Report Type" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Report Type Post Trace" xil_pn:value="Verbose Report" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Report Unconstrained Paths" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Report Unconstrained Paths Post Trace" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Reset On Configuration Pulse Width" xil_pn:value="100" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Resource Sharing" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Retain Hierarchy" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Retry Configuration if CRC Error Occurs spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Revision Select" xil_pn:value="00" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Revision Select Tristate" xil_pn:value="Disable" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Router Effort Level (Overrides Overall Level)" xil_pn:value="None" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Run Design Rules Checker (DRC)" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Run for Specified Time" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Run for Specified Time Map" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Run for Specified Time Par" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/TwoComplementTest" xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Selected Simulation Source Node" xil_pn:value="UUT" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Set SPI Configuration Bus Width spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Setup External Master Clock Division spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Shift Register Extraction" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Shift Register Minimum Size spartan6" xil_pn:value="2" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Show All Models" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Simulation Model Target" xil_pn:value="VHDL" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Simulation Run Time ISim" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Simulation Run Time Map" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Simulation Run Time Par" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Simulation Run Time Translate" xil_pn:value="1000 ns" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Simulator" xil_pn:value="ISim (VHDL/Verilog)" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.TwoComplementTest" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Speed Grade" xil_pn:value="-3" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Starting Placer Cost Table (1-100) Map" xil_pn:value="1" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Starting Placer Cost Table (1-100) Map spartan6" xil_pn:value="1" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Target UCF File Name" xil_pn:value="SpecialCasesCheck.ucf" xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Trim Unconnected Signals" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Project File Post-Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Simulation Command File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Simulation Command File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Simulation Command File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Simulation Command File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Waveform Configuration File Behav" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Waveform Configuration File Map" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Waveform Configuration File Par" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Custom Waveform Configuration File Translate" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use DSP Block spartan6" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6_runtime.xds" xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
-
     <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
-
     <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Value Range Check" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Verilog 2001 Xst" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Verilog Macros" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Wait for DCM and PLL Lock (Output Events) spartan6" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Wait for DLL Lock (Output Events)" xil_pn:value="Default (NoWait)" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Wakeup Clock spartan6" xil_pn:value="Startup Clock" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Watchdog Timer Value spartan6" xil_pn:value="0xFFFF" xil_pn:valueState="default"/>
-
     <property xil_pn:name="Working Directory" xil_pn:value="." xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="Write Timing Constraints" xil_pn:value="false" xil_pn:valueState="default"/>
-
     <property xil_pn:name="XOR Collapsing" xil_pn:value="true" xil_pn:valueState="default"/>
-
     <!--                                                                                  -->
-
     <!-- The following properties are for internal use only. These should not be modified.-->
-
     <!--                                                                                  -->
-
     <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|TwoComplementTest|behavior" xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
-
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
-
     <property xil_pn:name="PROP_PostMapSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="PROP_PostParSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
-
     <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
-
     <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-08-24T16:50:37" xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="444E2DA6F875B400D5DCC2E6514F4196" xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
-
     <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
-
   </properties>
 
-
-
   <bindings/>
 
-
-
   <libraries/>
 
-
-
   <autoManagedFiles>
-
     <!-- The following files are identified by `include statements in verilog -->
-
     <!-- source files and are automatically managed by Project Navigator.     -->
-
     <!--                                                                      -->
-
     <!-- Do not hand-edit this section, as it will be overwritten when the    -->
-
     <!-- project is analyzed based on files automatically identified as       -->
-
     <!-- include files.                                                       -->
-
   </autoManagedFiles>
 
-
-
 </project>
-
diff --git a/NaNCheck.vhd b/NaNCheck.vhd
index 0fb9aa3..2f7bd3d 100644
--- a/NaNCheck.vhd
+++ b/NaNCheck.vhd
@@ -15,7 +15,7 @@ architecture NaNCheckArch of NaNCheck is
 	component TypeCheck is
 	
 		port(
-			N : in std_logic_vector(31 downto 0);
+			N : in std_logic_vector(30 downto 0);
 			NAN, INF : out std_logic
 		);
 		
@@ -31,10 +31,10 @@ architecture NaNCheckArch of NaNCheck is
 begin
 
 	xCheck: TypeCheck
-		port map (N => X, NAN => X_NAN, INF => X_INF);
+		port map (N => X(30 downto 0), NAN => X_NAN, INF => X_INF);
 		
 	yCheck: TypeCheck
-		port map (N => Y, NAN => Y_NAN, INF => Y_INF);
+		port map (N => Y(30 downto 0), NAN => Y_NAN, INF => Y_INF);
 
 	X_SIGN <= X(31);
 	Y_SIGN <= Y(31);
diff --git a/TypeCheck.vhd b/TypeCheck.vhd
index a2fda1b..77b4d20 100644
--- a/TypeCheck.vhd
+++ b/TypeCheck.vhd
@@ -4,7 +4,7 @@ use IEEE.STD_LOGIC_1164.ALL;
 entity TypeCheck is
 
 	port(
-		N : in std_logic_vector(31 downto 0);
+		N : in std_logic_vector(30 downto 0);
 		NAN, INF : out std_logic
 	);
 	
diff --git a/equalCheck.vhd b/equalCheck.vhd
deleted file mode 100644
index eb1ec98..0000000
--- a/equalCheck.vhd
+++ /dev/null
@@ -1,44 +0,0 @@
-library IEEE;
-use IEEE.STD_LOGIC_1164.ALL;
-
-entity EqualCheck is
-
-	generic(
-		BITCOUNT: integer := 8
-	);
-	
-	port(
-		X, Y : in std_logic_vector((BITCOUNT-1) downto 0);
-		IS_EQUAL : out std_logic
-	);
-	
-end EqualCheck;
-
-architecture EqualCheckArch of EqualCheck is
-
-	signal COMP_VEC : std_logic_vector((BITCOUNT-1) downto 0);
-	
-
-
-begin
-
-	COMP_VEC <= X xor Y;
-	
-	RES_COMPUTE: process (COMP_VEC)
-	
-		variable RES_TMP : std_logic;
-		
-	begin
-	
-		RES_TMP := '0';
-		
-		for i in COMP_VEC'range loop
-			RES_TMP := RES_TMP or COMP_VEC(i);
-		end loop;
-		
-		IS_EQUAL <= not RES_TMP;
-		
-	end process;
-
-end EqualCheckArch;
-