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This commit is contained in:
Luca Cuzzocrea
2019-08-28 21:50:05 +02:00
parent f8b3061b00
commit a91e1252d0
80 changed files with 4236 additions and 50 deletions
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20
AddSub.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity AddSub is
generic( BITCOUNT: integer := 8 );
port(
X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
isSub: in std_logic := 0;
result: out std_logic_vector((BITCOUNT-1) downto 0)
);
end AddSub;
architecture CLAAddSubArch of AddSub is
begin
end CLAAddSubArch;

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Adder.vhd Normal file
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Adder is
generic( BITCOUNT: integer := 8 );
port(
X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
carry_in: in std_logic;
result: out std_logic_vector((BITCOUNT-1) downto 0);
carry_out: out std_logic
);
end Adder;
architecture CarryLookAheadArch of Adder is
signal generation: std_logic_vector((BITCOUNT-1) downto 0);
signal propagation: std_logic_vector((BITCOUNT-1) downto 0);
signal carry: std_logic_vector((BITCOUNT-1) downto 0);
signal sum_no_carry: std_logic_vector((BITCOUNT-1) downto 0);
begin
generation <= X and Y;
propagation <= X or Y;
sum_no_carry <= X xor Y;
carry_look_ahead: process (generation, propagation, carry, carry_in)
begin
carry(0) <= carry_in;
for i in (BITCOUNT-1) downto 1 loop
carry(i) <= generation(i) or (propagation(i) and carry(i-1));
end loop;
end process;
result <= sum_no_carry xor carry;
carry_out <= sum_no_carry(BITCOUNT-1) xor carry(BITCOUNT-1);
end CarryLookAheadArch;

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AdderTest.vhd Normal file
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--------------------------------------------------------------------------------
-- Company:
-- Engineer:
--
-- Create Date: 17:01:26 08/24/2019
-- Design Name:
-- Module Name: /home/Luca/ISE/IEEE754Adder/AdderTest.vhd
-- Project Name: IEEE754Adder
-- Target Device:
-- Tool versions:
-- Description:
--
-- VHDL Test Bench Created by ISE for module: Adder
--
-- Dependencies:
--
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes:
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test. Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
ENTITY AdderTest IS
END AdderTest;
ARCHITECTURE behavior OF AdderTest IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Adder
PORT(
X : IN std_logic_vector(7 downto 0);
Y : IN std_logic_vector(7 downto 0);
carry_in : IN std_logic;
result : OUT std_logic_vector(7 downto 0);
carry_out : OUT std_logic
);
END COMPONENT;
--Inputs
signal X : std_logic_vector(7 downto 0) := (others => '0');
signal Y : std_logic_vector(7 downto 0) := (others => '0');
signal carry_in : std_logic := '0';
--Outputs
signal result : std_logic_vector(7 downto 0);
signal carry_out : std_logic;
-- No clocks detected in port list. Replace clock below with
-- appropriate port name
signal clock: std_logic;
constant clock_period : time := 10 ns;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Adder PORT MAP (
X => X,
Y => Y,
carry_in => carry_in,
result => result,
carry_out => carry_out
);
-- Clock process definitions
clock_process :process
begin
clock <= '0';
wait for clock_period/2;
clock <= '1';
wait for clock_period/2;
end process;
x <= "00010101";
y <= "00001110";
END;

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54
IEEE754Adder.xise
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@@ -16,31 +16,48 @@
<files> <files>
<file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="SpecialCasesCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="5"/> <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
</file> </file>
<file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="TypeCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="1"/> <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
</file> </file>
<file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="NaNCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="4"/> <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
</file> </file>
<file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="ZeroCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="3"/> <association xil_pn:name="Implementation" xil_pn:seqID="3"/>
</file> </file>
<file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="EqualCheck.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="2"/> <association xil_pn:name="Implementation" xil_pn:seqID="2"/>
</file> </file>
<file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL"> <file xil_pn:name="SpecialCasesTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/> <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/> <association xil_pn:name="PostMapSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/> <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="96"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/> <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
</file> </file>
<file xil_pn:name="SpecialCasesCheck.ucf" xil_pn:type="FILE_UCF">
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
<association xil_pn:name="Implementation" xil_pn:seqID="0"/>
</file>
<file xil_pn:name="AdderTest.vhd" xil_pn:type="FILE_VHDL">
<association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
<association xil_pn:name="PostMapSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostRouteSimulation" xil_pn:seqID="143"/>
<association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="143"/>
</file>
</files> </files>
<properties> <properties>
@@ -109,7 +126,7 @@
<property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Debugging of Serial Mode BitStream" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable External Master Clock spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Hardware Co-Simulation" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="true" xil_pn:valueState="non-default"/> <property xil_pn:name="Enable Internal Done Pipe" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Message Filtering" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Pin Wake-Up Suspend Mode spartan6" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/> <property xil_pn:name="Enable Multi-Threading" xil_pn:value="Off" xil_pn:valueState="default"/>
@@ -206,7 +223,7 @@
<property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/> <property xil_pn:name="Mux Style" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/> <property xil_pn:name="Netlist Hierarchy" xil_pn:value="As Optimized" xil_pn:valueState="default"/>
<property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/> <property xil_pn:name="Netlist Translation Type" xil_pn:value="Timestamp" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Clock Buffers" xil_pn:value="32" xil_pn:valueState="non-default"/> <property xil_pn:name="Number of Clock Buffers" xil_pn:value="16" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Number of Paths in Error/Verbose Report" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/> <property xil_pn:name="Number of Paths in Error/Verbose Report Post Trace" xil_pn:value="3" xil_pn:valueState="default"/>
<property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/> <property xil_pn:name="Optimization Effort" xil_pn:value="Normal" xil_pn:valueState="default"/>
@@ -328,7 +345,8 @@
<property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/> <property xil_pn:name="Starting Placer Cost Table (1-100) Par" xil_pn:value="1" xil_pn:valueState="default"/>
<property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/> <property xil_pn:name="Synthesis Tool" xil_pn:value="XST (VHDL/Verilog)" xil_pn:valueState="default"/>
<property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/> <property xil_pn:name="Target Simulator" xil_pn:value="Please Specify" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Non Timing Driven" xil_pn:valueState="non-default"/> <property xil_pn:name="Target UCF File Name" xil_pn:value="SpecialCasesCheck.ucf" xil_pn:valueState="non-default"/>
<property xil_pn:name="Timing Mode Map" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/> <property xil_pn:name="Timing Mode Par" xil_pn:value="Performance Evaluation" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Module Name in Output Netlist" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/> <property xil_pn:name="Top-Level Source Type" xil_pn:value="HDL" xil_pn:valueState="default"/>
@@ -336,7 +354,7 @@
<property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/> <property xil_pn:name="Tristate On Configuration Pulse Width" xil_pn:value="0" xil_pn:valueState="default"/>
<property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/> <property xil_pn:name="Unused IOB Pins" xil_pn:value="Pull Down" xil_pn:valueState="default"/>
<property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use 64-bit PlanAhead on 64-bit Systems" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use Clock Enable" xil_pn:value="Yes" xil_pn:valueState="non-default"/> <property xil_pn:name="Use Clock Enable" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Project File Behavioral" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Project File Post-Map" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Custom Project File Post-Route" xil_pn:value="false" xil_pn:valueState="default"/>
@@ -353,10 +371,10 @@
<property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use LOC Constraints" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/> <property xil_pn:name="Use RLOC Constraints" xil_pn:value="Yes" xil_pn:valueState="default"/>
<property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/> <property xil_pn:name="Use Smart Guide" xil_pn:value="false" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Reset" xil_pn:value="Yes" xil_pn:valueState="non-default"/> <property xil_pn:name="Use Synchronous Reset" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synchronous Set" xil_pn:value="Yes" xil_pn:valueState="non-default"/> <property xil_pn:name="Use Synchronous Set" xil_pn:value="Auto" xil_pn:valueState="default"/>
<property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/> <property xil_pn:name="Use Synthesis Constraints File" xil_pn:value="true" xil_pn:valueState="default"/>
<property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan3/data/spartan3_runtime.xds" xil_pn:valueState="non-default"/> <property xil_pn:name="User Browsed Strategy Files" xil_pn:value="/opt/Xilinx/14.7/ISE_DS/ISE/spartan6/data/spartan6_runtime.xds" xil_pn:valueState="non-default"/>
<property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/> <property xil_pn:name="UserID Code (8 Digit Hexadecimal)" xil_pn:value="0xFFFFFFFF" xil_pn:valueState="default"/>
<property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/> <property xil_pn:name="VCCAUX Voltage Level spartan6" xil_pn:value="2.5V" xil_pn:valueState="default"/>
<property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/> <property xil_pn:name="VHDL Source Analysis Standard" xil_pn:value="VHDL-93" xil_pn:valueState="default"/>
@@ -373,7 +391,7 @@
<!-- --> <!-- -->
<!-- The following properties are for internal use only. These should not be modified.--> <!-- The following properties are for internal use only. These should not be modified.-->
<!-- --> <!-- -->
<property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|SpecialCasesTest|behavior" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|AdderTest|behavior" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/> <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="aspartan6" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/> <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
@@ -382,13 +400,15 @@
<property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostSynthSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PostXlateSimTop" xil_pn:value="" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/> <property xil_pn:name="PROP_PreSynthesis" xil_pn:value="PreSynthesis" xil_pn:valueState="default"/>
<property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-08-17T16:51:15" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intProjectCreationTimestamp" xil_pn:value="2019-08-24T16:50:37" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="4B48FA10A560F77F46DA66FD7F346092" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWbtProjectID" xil_pn:value="444E2DA6F875B400D5DCC2E6514F4196" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirLocWRTProjDir" xil_pn:value="Same" xil_pn:valueState="non-default"/>
<property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/> <property xil_pn:name="PROP_intWorkingDirUsed" xil_pn:value="No" xil_pn:valueState="non-default"/>
</properties> </properties>
<bindings/> <bindings>
<binding xil_pn:location="/Adder" xil_pn:name="SpecialCasesCheck.ucf"/>
</bindings>
<libraries/> <libraries/>

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SpecialCasesCheck.ucf Normal file
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SpecialCasesCheck.vhd
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@@ -16,7 +16,7 @@ architecture SpecialCasesCheckArch of SpecialCasesCheck is
isNaN: out std_logic isNaN: out std_logic
); );
end component; end component;
component ZeroCheck is component ZeroCheck is
port( port(
X, Y: in std_logic_vector(31 downto 0); X, Y: in std_logic_vector(31 downto 0);

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SpecialCasesCheck.xdl Normal file
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fuse.log
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@@ -1,30 +1,22 @@
Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_beh.prj work.SpecialCasesTest Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj work.AdderTest
ISim P.20131013 (signature 0xfbc00daa) ISim P.20131013 (signature 0xfbc00daa)
Number of CPUs detected in this system: 4 Number of CPUs detected in this system: 4
Turning on mult-threading, number of parallel sub-compilation jobs: 8 Turning on mult-threading, number of parallel sub-compilation jobs: 8
Determining compilation order of HDL files Determining compilation order of HDL files
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd" into library work Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd" into library work Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AdderTest.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.vhd" into library work
Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest.vhd" into library work
Starting static elaboration Starting static elaboration
Completed static elaboration Completed static elaboration
Fuse Memory Usage: 94420 KB Fuse Memory Usage: 94252 KB
Fuse CPU Usage: 980 ms Fuse CPU Usage: 950 ms
Compiling package standard Compiling package standard
Compiling package std_logic_1164 Compiling package std_logic_1164
Compiling architecture typecheckarch of entity TypeCheck [typecheck_default] Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
Compiling architecture nancheckarch of entity NaNCheck [nancheck_default] Compiling architecture behavior of entity addertest
Compiling architecture equalcheckarch of entity EqualCheck [\EqualCheck(31)\]
Compiling architecture zerocheckarch of entity ZeroCheck [zerocheck_default]
Compiling architecture specialcasescheckarch of entity SpecialCasesCheck [specialcasescheck_default]
Compiling architecture behavior of entity specialcasestest
Time Resolution for simulation is 1ps. Time Resolution for simulation is 1ps.
Waiting for 1 sub-compilation(s) to finish... Waiting for 1 sub-compilation(s) to finish...
Compiled 13 VHDL Units Compiled 5 VHDL Units
Built simulation executable /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe Built simulation executable /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe
Fuse Memory Usage: 658120 KB Fuse Memory Usage: 657936 KB
Fuse CPU Usage: 1000 ms Fuse CPU Usage: 980 ms
GCC CPU Usage: 280 ms GCC CPU Usage: 140 ms

2
fuseRelaunch.cmd
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@@ -1 +1 @@
-intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/SpecialCasesTest_beh.prj" "work.SpecialCasesTest" -intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/AdderTest_beh.prj" "work.AdderTest"

2
isim.log
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@@ -1,5 +1,5 @@
ISim log file ISim log file
Running: /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/Luca/ISE/IEEE754Adder/SpecialCasesTest_isim_beh.wdb Running: /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.exe -intstyle ise -gui -tclbatch isim.cmd -wdb /home/Luca/ISE/IEEE754Adder/AdderTest_isim_beh.wdb
ISim P.20131013 (signature 0xfbc00daa) ISim P.20131013 (signature 0xfbc00daa)
WARNING: A WEBPACK license was found. WARNING: A WEBPACK license was found.
WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license. WARNING: Please use Xilinx License Configuration Manager to check out a full ISim license.

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isim/AdderTest_isim_beh.exe.sim/AdderTest_isim_beh.exe Executable file
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isim/AdderTest_isim_beh.exe.sim/ISimEngine-DesignHierarchy.dbg Normal file
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isim/AdderTest_isim_beh.exe.sim/isimcrash.log Normal file
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isim/AdderTest_isim_beh.exe.sim/isimkernel.log Normal file
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Command line:
AdderTest_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 37101
Sat Aug 24 17:55:24 2019
Elaboration Time: 0.02 sec
Current Memory Usage: 195.351 Meg
Total Signals : 15
Total Nets : 59
Total Signal Drivers : 9
Total Blocks : 3
Total Primitive Blocks : 2
Total Processes : 9
Total Traceable Variables : 10
Total Scalar Nets and Variables : 421
Total Line Count : 14
Total Simulation Time: 0.03 sec
Current Memory Usage: 272.949 Meg
Sat Aug 24 18:01:51 2019

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isim/AdderTest_isim_beh.exe.sim/netId.dat Normal file
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isim/AdderTest_isim_beh.exe.sim/tmp_save/_1 Normal file
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40
isim/AdderTest_isim_beh.exe.sim/work/AdderTest_isim_beh.exe_main.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_3841309559_2737618828_init();
work_a_4008929629_2372691052_init();
xsi_register_tops("work_a_4008929629_2372691052");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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isim/AdderTest_isim_beh.exe.sim/work/AdderTest_isim_beh.exe_main.lin64.o Normal file
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462
isim/AdderTest_isim_beh.exe.sim/work/a_3841309559_2737618828.c Normal file
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@@ -0,0 +1,462 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/Adder.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439767405979520975_503743352(char *, char *, char *, char *, char *, char *);
char *ieee_p_2592010699_sub_16439989832805790689_503743352(char *, char *, char *, char *, char *, char *);
char *ieee_p_2592010699_sub_16439989833707593767_503743352(char *, char *, char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768497506413324_503743352(char *, unsigned char , unsigned char );
static void work_a_3841309559_2737618828_p_0(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(21, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 7680U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 7696U);
t6 = ieee_p_2592010699_sub_16439989832805790689_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (8U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 5304);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 8U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 5144);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t9, 0);
goto LAB6;
}
static void work_a_3841309559_2737618828_p_1(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(22, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 7680U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 7696U);
t6 = ieee_p_2592010699_sub_16439767405979520975_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (8U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 5368);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 8U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 5160);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t9, 0);
goto LAB6;
}
static void work_a_3841309559_2737618828_p_2(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(23, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 7680U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 7696U);
t6 = ieee_p_2592010699_sub_16439989833707593767_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (8U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 5432);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 8U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 5176);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t9, 0);
goto LAB6;
}
static void work_a_3841309559_2737618828_p_3(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
char *t5;
char *t6;
char *t7;
int t8;
int t9;
int t10;
int t11;
int t12;
unsigned int t13;
unsigned int t14;
unsigned int t15;
char *t16;
int t17;
int t18;
unsigned int t19;
unsigned int t20;
unsigned int t21;
char *t22;
unsigned char t23;
char *t24;
char *t25;
int t26;
int t27;
int t28;
unsigned int t29;
unsigned int t30;
unsigned int t31;
char *t32;
unsigned char t33;
unsigned char t34;
unsigned char t35;
char *t36;
int t37;
int t38;
unsigned int t39;
unsigned int t40;
unsigned int t41;
char *t42;
char *t43;
char *t44;
char *t45;
char *t46;
LAB0: xsi_set_current_line(27, ng0);
t1 = (t0 + 1352U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 5496);
t4 = (t1 + 56U);
t5 = *((char **)t4);
t6 = (t5 + 56U);
t7 = *((char **)t6);
*((unsigned char *)t7) = t3;
xsi_driver_first_trans_delta(t1, 7U, 1, 0LL);
xsi_set_current_line(28, ng0);
t8 = (8 - 1);
t1 = (t0 + 7853);
*((int *)t1) = t8;
t2 = (t0 + 7857);
*((int *)t2) = 1;
t9 = t8;
t10 = 1;
LAB2: if (t9 >= t10)
goto LAB3;
LAB5: t1 = (t0 + 5192);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(29, ng0);
t4 = (t0 + 1832U);
t5 = *((char **)t4);
t4 = (t0 + 7853);
t11 = *((int *)t4);
t12 = (t11 - 7);
t13 = (t12 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t4));
t14 = (1U * t13);
t15 = (0 + t14);
t6 = (t5 + t15);
t3 = *((unsigned char *)t6);
t7 = (t0 + 1992U);
t16 = *((char **)t7);
t7 = (t0 + 7853);
t17 = *((int *)t7);
t18 = (t17 - 7);
t19 = (t18 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, *((int *)t7));
t20 = (1U * t19);
t21 = (0 + t20);
t22 = (t16 + t21);
t23 = *((unsigned char *)t22);
t24 = (t0 + 2152U);
t25 = *((char **)t24);
t24 = (t0 + 7853);
t26 = *((int *)t24);
t27 = (t26 - 1);
t28 = (t27 - 7);
t29 = (t28 * -1);
xsi_vhdl_check_range_of_index(7, 0, -1, t27);
t30 = (1U * t29);
t31 = (0 + t30);
t32 = (t25 + t31);
t33 = *((unsigned char *)t32);
t34 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t23, t33);
t35 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t3, t34);
t36 = (t0 + 7853);
t37 = *((int *)t36);
t38 = (t37 - 7);
t39 = (t38 * -1);
t40 = (1 * t39);
t41 = (0U + t40);
t42 = (t0 + 5496);
t43 = (t42 + 56U);
t44 = *((char **)t43);
t45 = (t44 + 56U);
t46 = *((char **)t45);
*((unsigned char *)t46) = t35;
xsi_driver_first_trans_delta(t42, t41, 1, 0LL);
LAB4: t1 = (t0 + 7853);
t9 = *((int *)t1);
t2 = (t0 + 7857);
t10 = *((int *)t2);
if (t9 == t10)
goto LAB5;
LAB6: t8 = (t9 + -1);
t9 = t8;
t4 = (t0 + 7853);
*((int *)t4) = t9;
goto LAB2;
}
static void work_a_3841309559_2737618828_p_4(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(33, ng0);
LAB3: t2 = (t0 + 2312U);
t3 = *((char **)t2);
t2 = (t0 + 7776U);
t4 = (t0 + 2152U);
t5 = *((char **)t4);
t4 = (t0 + 7760U);
t6 = ieee_p_2592010699_sub_16439989833707593767_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (8U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 5560);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 8U);
xsi_driver_first_trans_fast_port(t11);
LAB2: t16 = (t0 + 5208);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(8U, t9, 0);
goto LAB6;
}
static void work_a_3841309559_2737618828_p_5(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
unsigned int t5;
unsigned int t6;
unsigned int t7;
unsigned char t8;
char *t9;
char *t10;
int t11;
int t12;
unsigned int t13;
unsigned int t14;
unsigned int t15;
unsigned char t16;
unsigned char t17;
char *t18;
char *t19;
char *t20;
char *t21;
char *t22;
char *t23;
LAB0: xsi_set_current_line(34, ng0);
LAB3: t1 = (t0 + 2312U);
t2 = *((char **)t1);
t3 = (8 - 1);
t4 = (t3 - 7);
t5 = (t4 * -1);
t6 = (1U * t5);
t7 = (0 + t6);
t1 = (t2 + t7);
t8 = *((unsigned char *)t1);
t9 = (t0 + 2152U);
t10 = *((char **)t9);
t11 = (8 - 1);
t12 = (t11 - 7);
t13 = (t12 * -1);
t14 = (1U * t13);
t15 = (0 + t14);
t9 = (t10 + t15);
t16 = *((unsigned char *)t9);
t17 = ieee_p_2592010699_sub_3488768497506413324_503743352(IEEE_P_2592010699, t8, t16);
t18 = (t0 + 5624);
t19 = (t18 + 56U);
t20 = *((char **)t19);
t21 = (t20 + 56U);
t22 = *((char **)t21);
*((unsigned char *)t22) = t17;
xsi_driver_first_trans_fast_port(t18);
LAB2: t23 = (t0 + 5224);
*((int *)t23) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_3841309559_2737618828_init()
{
static char *pe[] = {(void *)work_a_3841309559_2737618828_p_0,(void *)work_a_3841309559_2737618828_p_1,(void *)work_a_3841309559_2737618828_p_2,(void *)work_a_3841309559_2737618828_p_3,(void *)work_a_3841309559_2737618828_p_4,(void *)work_a_3841309559_2737618828_p_5};
xsi_register_didat("work_a_3841309559_2737618828", "isim/AdderTest_isim_beh.exe.sim/work/a_3841309559_2737618828.didat");
xsi_register_executes(pe);
}

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isim/AdderTest_isim_beh.exe.sim/work/a_3841309559_2737618828.lin64.o Normal file
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isim/AdderTest_isim_beh.exe.sim/work/a_4008929629_2372691052.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/AdderTest.vhd";
static void work_a_4008929629_2372691052_p_0(char *t0)
{
char *t1;
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
int64 t7;
int64 t8;
LAB0: t1 = (t0 + 3104U);
t2 = *((char **)t1);
if (t2 == 0)
goto LAB2;
LAB3: goto *t2;
LAB2: xsi_set_current_line(81, ng0);
t2 = (t0 + 3984);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)2;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(82, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB6: *((char **)t1) = &&LAB7;
LAB1: return;
LAB4: xsi_set_current_line(83, ng0);
t2 = (t0 + 3984);
t3 = (t2 + 56U);
t4 = *((char **)t3);
t5 = (t4 + 56U);
t6 = *((char **)t5);
*((unsigned char *)t6) = (unsigned char)3;
xsi_driver_first_trans_fast(t2);
xsi_set_current_line(84, ng0);
t2 = (t0 + 2128U);
t3 = *((char **)t2);
t7 = *((int64 *)t3);
t8 = (t7 / 2);
t2 = (t0 + 2912);
xsi_process_wait(t2, t8);
LAB10: *((char **)t1) = &&LAB11;
goto LAB1;
LAB5: goto LAB4;
LAB7: goto LAB5;
LAB8: goto LAB2;
LAB9: goto LAB8;
LAB11: goto LAB9;
}
static void work_a_4008929629_2372691052_p_1(char *t0)
{
char *t1;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(87, ng0);
LAB3: t1 = (t0 + 6136);
t3 = (t0 + 4048);
t4 = (t3 + 56U);
t5 = *((char **)t4);
t6 = (t5 + 56U);
t7 = *((char **)t6);
memcpy(t7, t1, 8U);
xsi_driver_first_trans_fast(t3);
LAB2:
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_4008929629_2372691052_p_2(char *t0)
{
char *t1;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
LAB0: xsi_set_current_line(88, ng0);
LAB3: t1 = (t0 + 6144);
t3 = (t0 + 4112);
t4 = (t3 + 56U);
t5 = *((char **)t4);
t6 = (t5 + 56U);
t7 = *((char **)t6);
memcpy(t7, t1, 8U);
xsi_driver_first_trans_fast(t3);
LAB2:
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_4008929629_2372691052_init()
{
static char *pe[] = {(void *)work_a_4008929629_2372691052_p_0,(void *)work_a_4008929629_2372691052_p_1,(void *)work_a_4008929629_2372691052_p_2};
xsi_register_didat("work_a_4008929629_2372691052", "isim/AdderTest_isim_beh.exe.sim/work/a_4008929629_2372691052.didat");
xsi_register_executes(pe);
}

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Command line:
SpecialCasesCheck_isim_beh.exe
-simmode gui
-simrunnum 0
-socket 46093
Sat Aug 24 14:53:42 2019
Elaboration Time: 0.02 sec
Current Memory Usage: 195.351 Meg
Total Signals : 40
Total Nets : 235
Total Signal Drivers : 23
Total Blocks : 7
Total Primitive Blocks : 4
Total Processes : 23
Total Traceable Variables : 9
Total Scalar Nets and Variables : 596
Total Line Count : 38
Total Simulation Time: 0.02 sec
Current Memory Usage: 272.949 Meg
Sat Aug 24 14:53:52 2019

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isim/SpecialCasesCheck_isim_beh.exe.sim/work/SpecialCasesCheck_isim_beh.exe_main.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
#include "xsi.h"
struct XSI_INFO xsi_info;
char *IEEE_P_2592010699;
char *STD_STANDARD;
int main(int argc, char **argv)
{
xsi_init_design(argc, argv);
xsi_register_info(&xsi_info);
xsi_register_min_prec_unit(-12);
ieee_p_2592010699_init();
work_a_0557987184_1272247069_init();
work_a_3914402253_2628201599_init();
work_a_2347761600_1146481140_init();
work_a_1540508602_4151211736_init();
work_a_1684417184_3395701438_init();
xsi_register_tops("work_a_1684417184_3395701438");
IEEE_P_2592010699 = xsi_get_engine_memory("ieee_p_2592010699");
xsi_register_ieee_std_logic_1164(IEEE_P_2592010699);
STD_STANDARD = xsi_get_engine_memory("std_standard");
return xsi_run_simulation(argc, argv);
}

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isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/TypeCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_0557987184_1272247069_p_0(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(17, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5104);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 8U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4944);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_1(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(18, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 22);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5168);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 23U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 4960);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_2(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(23, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)3;
xsi_set_current_line(24, ng0);
t1 = (t0 + 7603);
*((int *)t1) = 7;
t2 = (t0 + 7607);
*((int *)t2) = 0;
t3 = 7;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(27, ng0);
t1 = (t0 + 2288U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5232);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4976);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(25, ng0);
t5 = (t0 + 2288U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1512U);
t8 = *((char **)t5);
t5 = (t0 + 7603);
t9 = *((int *)t5);
t10 = (t9 - 7);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2288U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7603);
t3 = *((int *)t1);
t2 = (t0 + 7607);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7603);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_3(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(33, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(34, ng0);
t1 = (t0 + 7611);
*((int *)t1) = 22;
t2 = (t0 + 7615);
*((int *)t2) = 0;
t3 = 22;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(37, ng0);
t1 = (t0 + 2408U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t1 = (t0 + 5296);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t7;
xsi_driver_first_trans_fast(t1);
t1 = (t0 + 4992);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(35, ng0);
t5 = (t0 + 2408U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1672U);
t8 = *((char **)t5);
t5 = (t0 + 7611);
t9 = *((int *)t5);
t10 = (t9 - 22);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 2408U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 7611);
t3 = *((int *)t1);
t2 = (t0 + 7615);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 7611);
*((int *)t5) = t3;
goto LAB2;
}
static void work_a_0557987184_1272247069_p_4(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(40, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 5360);
t7 = (t1 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
*((unsigned char *)t10) = t6;
xsi_driver_first_trans_fast_port(t1);
LAB2: t11 = (t0 + 5008);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_0557987184_1272247069_p_5(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
LAB0: xsi_set_current_line(41, ng0);
LAB3: t1 = (t0 + 1832U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t5);
t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t3, t6);
t1 = (t0 + 5424);
t8 = (t1 + 56U);
t9 = *((char **)t8);
t10 = (t9 + 56U);
t11 = *((char **)t10);
*((unsigned char *)t11) = t7;
xsi_driver_first_trans_fast_port(t1);
LAB2: t12 = (t0 + 5024);
*((int *)t12) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_0557987184_1272247069_init()
{
static char *pe[] = {(void *)work_a_0557987184_1272247069_p_0,(void *)work_a_0557987184_1272247069_p_1,(void *)work_a_0557987184_1272247069_p_2,(void *)work_a_0557987184_1272247069_p_3,(void *)work_a_0557987184_1272247069_p_4,(void *)work_a_0557987184_1272247069_p_5};
xsi_register_didat("work_a_0557987184_1272247069", "isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_0557987184_1272247069.didat");
xsi_register_executes(pe);
}

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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/ZeroCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3496108612141461530_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_1540508602_4151211736_p_0(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(28, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 5184);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 5024);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_1(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(29, ng0);
LAB3: t1 = (t0 + 1192U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 5248);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 5040);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_2(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(30, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5312);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 31U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 5056);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_3(char *t0)
{
char *t1;
char *t2;
unsigned int t3;
unsigned int t4;
unsigned int t5;
char *t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(31, ng0);
LAB3: t1 = (t0 + 1192U);
t2 = *((char **)t1);
t3 = (31 - 30);
t4 = (t3 * 1U);
t5 = (0 + t4);
t1 = (t2 + t5);
t6 = (t0 + 5376);
t7 = (t6 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
memcpy(t10, t1, 31U);
xsi_driver_first_trans_fast(t6);
LAB2: t11 = (t0 + 5072);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_4(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
char *t8;
char *t9;
char *t10;
char *t11;
LAB0: xsi_set_current_line(33, ng0);
LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1672U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3496108612141461530_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 5440);
t7 = (t1 + 56U);
t8 = *((char **)t7);
t9 = (t8 + 56U);
t10 = *((char **)t9);
*((unsigned char *)t10) = t6;
xsi_driver_first_trans_fast(t1);
LAB2: t11 = (t0 + 5088);
*((int *)t11) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_1540508602_4151211736_p_5(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
unsigned char t4;
char *t5;
unsigned char t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
LAB0: xsi_set_current_line(38, ng0);
LAB3: t1 = (t0 + 2312U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t4 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t3);
t1 = (t0 + 2152U);
t5 = *((char **)t1);
t6 = *((unsigned char *)t5);
t7 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t4, t6);
t1 = (t0 + 5504);
t8 = (t1 + 56U);
t9 = *((char **)t8);
t10 = (t9 + 56U);
t11 = *((char **)t10);
*((unsigned char *)t11) = t7;
xsi_driver_first_trans_fast_port(t1);
LAB2: t12 = (t0 + 5104);
*((int *)t12) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_1540508602_4151211736_init()
{
static char *pe[] = {(void *)work_a_1540508602_4151211736_p_0,(void *)work_a_1540508602_4151211736_p_1,(void *)work_a_1540508602_4151211736_p_2,(void *)work_a_1540508602_4151211736_p_3,(void *)work_a_1540508602_4151211736_p_4,(void *)work_a_1540508602_4151211736_p_5};
xsi_register_didat("work_a_1540508602_4151211736", "isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1540508602_4151211736.didat");
xsi_register_executes(pe);
}

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isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.c Normal file
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/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
extern void work_a_1684417184_3395701438_init()
{
xsi_register_didat("work_a_1684417184_3395701438", "isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_1684417184_3395701438.didat");
}

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@@ -0,0 +1,180 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/EqualCheck.vhd";
extern char *IEEE_P_2592010699;
char *ieee_p_2592010699_sub_16439989833707593767_503743352(char *, char *, char *, char *, char *, char *);
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_2347761600_1146481140_p_0(char *t0)
{
char t1[16];
char *t2;
char *t3;
char *t4;
char *t5;
char *t6;
char *t7;
unsigned int t8;
unsigned int t9;
unsigned char t10;
char *t11;
char *t12;
char *t13;
char *t14;
char *t15;
char *t16;
LAB0: xsi_set_current_line(15, ng0);
LAB3: t2 = (t0 + 1032U);
t3 = *((char **)t2);
t2 = (t0 + 5352U);
t4 = (t0 + 1192U);
t5 = *((char **)t4);
t4 = (t0 + 5368U);
t6 = ieee_p_2592010699_sub_16439989833707593767_503743352(IEEE_P_2592010699, t1, t3, t2, t5, t4);
t7 = (t1 + 12U);
t8 = *((unsigned int *)t7);
t9 = (1U * t8);
t10 = (31U != t9);
if (t10 == 1)
goto LAB5;
LAB6: t11 = (t0 + 3568);
t12 = (t11 + 56U);
t13 = *((char **)t12);
t14 = (t13 + 56U);
t15 = *((char **)t14);
memcpy(t15, t6, 31U);
xsi_driver_first_trans_fast(t11);
LAB2: t16 = (t0 + 3472);
*((int *)t16) = 1;
LAB1: return;
LAB4: goto LAB2;
LAB5: xsi_size_not_matching(31U, t9, 0);
goto LAB6;
}
static void work_a_2347761600_1146481140_p_1(char *t0)
{
char *t1;
char *t2;
int t3;
int t4;
char *t5;
char *t6;
unsigned char t7;
char *t8;
int t9;
int t10;
unsigned int t11;
unsigned int t12;
unsigned int t13;
char *t14;
unsigned char t15;
unsigned char t16;
char *t17;
char *t18;
LAB0: xsi_set_current_line(20, ng0);
t1 = (t0 + 1928U);
t2 = *((char **)t1);
t1 = (t2 + 0);
*((unsigned char *)t1) = (unsigned char)2;
xsi_set_current_line(21, ng0);
t1 = (t0 + 5506);
*((int *)t1) = 30;
t2 = (t0 + 5510);
*((int *)t2) = 0;
t3 = 30;
t4 = 0;
LAB2: if (t3 >= t4)
goto LAB3;
LAB5: xsi_set_current_line(24, ng0);
t1 = (t0 + 1928U);
t2 = *((char **)t1);
t7 = *((unsigned char *)t2);
t15 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t7);
t1 = (t0 + 3632);
t5 = (t1 + 56U);
t6 = *((char **)t5);
t8 = (t6 + 56U);
t14 = *((char **)t8);
*((unsigned char *)t14) = t15;
xsi_driver_first_trans_fast_port(t1);
t1 = (t0 + 3488);
*((int *)t1) = 1;
LAB1: return;
LAB3: xsi_set_current_line(22, ng0);
t5 = (t0 + 1928U);
t6 = *((char **)t5);
t7 = *((unsigned char *)t6);
t5 = (t0 + 1512U);
t8 = *((char **)t5);
t5 = (t0 + 5506);
t9 = *((int *)t5);
t10 = (t9 - 30);
t11 = (t10 * -1);
t12 = (1U * t11);
t13 = (0 + t12);
t14 = (t8 + t13);
t15 = *((unsigned char *)t14);
t16 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t7, t15);
t17 = (t0 + 1928U);
t18 = *((char **)t17);
t17 = (t18 + 0);
*((unsigned char *)t17) = t16;
LAB4: t1 = (t0 + 5506);
t3 = *((int *)t1);
t2 = (t0 + 5510);
t4 = *((int *)t2);
if (t3 == t4)
goto LAB5;
LAB6: t9 = (t3 + -1);
t3 = t9;
t5 = (t0 + 5506);
*((int *)t5) = t3;
goto LAB2;
}
extern void work_a_2347761600_1146481140_init()
{
static char *pe[] = {(void *)work_a_2347761600_1146481140_p_0,(void *)work_a_2347761600_1146481140_p_1};
xsi_register_didat("work_a_2347761600_1146481140", "isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_2347761600_1146481140.didat");
xsi_register_executes(pe);
}

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isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_3914402253_2628201599.c Normal file
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@@ -0,0 +1,221 @@
/**********************************************************************/
/* ____ ____ */
/* / /\/ / */
/* /___/ \ / */
/* \ \ \/ */
/* \ \ Copyright (c) 2003-2009 Xilinx, Inc. */
/* / / All Right Reserved. */
/* /---/ /\ */
/* \ \ / \ */
/* \___\/\___\ */
/***********************************************************************/
/* This file is designed for use with ISim build 0xfbc00daa */
#define XSI_HIDE_SYMBOL_SPEC true
#include "xsi.h"
#include <memory.h>
#ifdef __GNUC__
#include <stdlib.h>
#else
#include <malloc.h>
#define alloca _alloca
#endif
static const char *ng0 = "/home/Luca/ISE/IEEE754Adder/NaNCheck.vhd";
extern char *IEEE_P_2592010699;
unsigned char ieee_p_2592010699_sub_3488546069778340532_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_3488768496604610246_503743352(char *, unsigned char , unsigned char );
unsigned char ieee_p_2592010699_sub_374109322130769762_503743352(char *, unsigned char );
static void work_a_3914402253_2628201599_p_0(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(32, ng0);
LAB3: t1 = (t0 + 1032U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 4392);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 4280);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_3914402253_2628201599_p_1(char *t0)
{
char *t1;
char *t2;
int t3;
unsigned int t4;
unsigned int t5;
unsigned int t6;
unsigned char t7;
char *t8;
char *t9;
char *t10;
char *t11;
char *t12;
char *t13;
LAB0: xsi_set_current_line(33, ng0);
LAB3: t1 = (t0 + 1192U);
t2 = *((char **)t1);
t3 = (31 - 31);
t4 = (t3 * -1);
t5 = (1U * t4);
t6 = (0 + t5);
t1 = (t2 + t6);
t7 = *((unsigned char *)t1);
t8 = (t0 + 4456);
t9 = (t8 + 56U);
t10 = *((char **)t9);
t11 = (t10 + 56U);
t12 = *((char **)t11);
*((unsigned char *)t12) = t7;
xsi_driver_first_trans_fast(t8);
LAB2: t13 = (t0 + 4296);
*((int *)t13) = 1;
LAB1: return;
LAB4: goto LAB2;
}
static void work_a_3914402253_2628201599_p_2(char *t0)
{
char *t1;
char *t2;
unsigned char t3;
char *t4;
unsigned char t5;
unsigned char t6;
char *t7;
unsigned char t8;
char *t9;
unsigned char t10;
unsigned char t11;
char *t12;
unsigned char t13;
unsigned char t14;
char *t15;
unsigned char t16;
unsigned char t17;
unsigned char t18;
unsigned char t19;
char *t20;
unsigned char t21;
char *t22;
unsigned char t23;
unsigned char t24;
unsigned char t25;
char *t26;
unsigned char t27;
unsigned char t28;
char *t29;
unsigned char t30;
unsigned char t31;
unsigned char t32;
char *t33;
char *t34;
char *t35;
char *t36;
char *t37;
LAB0: xsi_set_current_line(35, ng0);
LAB3: t1 = (t0 + 1512U);
t2 = *((char **)t1);
t3 = *((unsigned char *)t2);
t1 = (t0 + 1992U);
t4 = *((char **)t1);
t5 = *((unsigned char *)t4);
t6 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t3, t5);
t1 = (t0 + 1672U);
t7 = *((char **)t1);
t8 = *((unsigned char *)t7);
t1 = (t0 + 1832U);
t9 = *((char **)t1);
t10 = *((unsigned char *)t9);
t11 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t8, t10);
t1 = (t0 + 2152U);
t12 = *((char **)t1);
t13 = *((unsigned char *)t12);
t14 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t11, t13);
t1 = (t0 + 2312U);
t15 = *((char **)t1);
t16 = *((unsigned char *)t15);
t17 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t16);
t18 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t14, t17);
t19 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t6, t18);
t1 = (t0 + 1672U);
t20 = *((char **)t1);
t21 = *((unsigned char *)t20);
t1 = (t0 + 1832U);
t22 = *((char **)t1);
t23 = *((unsigned char *)t22);
t24 = ieee_p_2592010699_sub_374109322130769762_503743352(IEEE_P_2592010699, t23);
t25 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t21, t24);
t1 = (t0 + 2152U);
t26 = *((char **)t1);
t27 = *((unsigned char *)t26);
t28 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t25, t27);
t1 = (t0 + 2312U);
t29 = *((char **)t1);
t30 = *((unsigned char *)t29);
t31 = ieee_p_2592010699_sub_3488768496604610246_503743352(IEEE_P_2592010699, t28, t30);
t32 = ieee_p_2592010699_sub_3488546069778340532_503743352(IEEE_P_2592010699, t19, t31);
t1 = (t0 + 4520);
t33 = (t1 + 56U);
t34 = *((char **)t33);
t35 = (t34 + 56U);
t36 = *((char **)t35);
*((unsigned char *)t36) = t32;
xsi_driver_first_trans_fast_port(t1);
LAB2: t37 = (t0 + 4312);
*((int *)t37) = 1;
LAB1: return;
LAB4: goto LAB2;
}
extern void work_a_3914402253_2628201599_init()
{
static char *pe[] = {(void *)work_a_3914402253_2628201599_p_0,(void *)work_a_3914402253_2628201599_p_1,(void *)work_a_3914402253_2628201599_p_2};
xsi_register_didat("work_a_3914402253_2628201599", "isim/SpecialCasesCheck_isim_beh.exe.sim/work/a_3914402253_2628201599.didat");
xsi_register_executes(pe);
}

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isim/SpecialCasesTest_isim_beh.exe.sim/isimkernel.log
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@@ -2,9 +2,9 @@ Command line:
SpecialCasesTest_isim_beh.exe SpecialCasesTest_isim_beh.exe
-simmode gui -simmode gui
-simrunnum 0 -simrunnum 0
-socket 47173 -socket 52126
Sat Aug 24 12:20:10 2019 Sat Aug 24 14:59:56 2019
Elaboration Time: 0.01 sec Elaboration Time: 0.01 sec
@@ -21,9 +21,9 @@ Sat Aug 24 12:20:10 2019
Total Scalar Nets and Variables : 601 Total Scalar Nets and Variables : 601
Total Line Count : 143 Total Line Count : 143
Total Simulation Time: 0.04 sec Total Simulation Time: 0.03 sec
Current Memory Usage: 272.957 Meg Current Memory Usage: 272.957 Meg
Sat Aug 24 14:38:35 2019 Sat Aug 24 15:00:02 2019

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isim/isim_usage_statistics.html
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<xtag-section name="ISimStatistics"> <xtag-section name="ISimStatistics">
<TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR> <TR ALIGN=CENTER BGCOLOR='#99CCFF'><TD COLSPAN=1><B>ISim Statistics</B></TD></TR>
<TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Xilinx HDL Libraries Used</xtag-isim-property-name>=<xtag-isim-property-value>ieee</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>1000 ms, 658120 KB</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Fuse Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>980 ms, 657936 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>48</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Signals</xtag-isim-property-name>=<xtag-isim-property-value>15</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>239</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Nets</xtag-isim-property-name>=<xtag-isim-property-value>59</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>8</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Blocks</xtag-isim-property-name>=<xtag-isim-property-value>3</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>26</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Processes</xtag-isim-property-name>=<xtag-isim-property-value>9</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Total Simulation Time</xtag-isim-property-name>=<xtag-isim-property-value>1 us</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.04 sec, 271904 KB</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Simulation Resource Usage</xtag-isim-property-name>=<xtag-isim-property-value>0.03 sec, 271896 KB</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Simulation Mode</xtag-isim-property-name>=<xtag-isim-property-value>gui</xtag-isim-property-value></TD></TR>
<TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR> <TR><TD><xtag-isim-property-name>Hardware CoSim</xtag-isim-property-name>=<xtag-isim-property-value>0</xtag-isim-property-value></TD></TR>
</xtag-section> </xtag-section>

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# PlanAhead Launch Script for Post PAR Floorplanning, created by Project Navigator
create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3
set srcset [get_property srcset [current_run -impl]]
set_property design_mode GateLvl $srcset
set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ]
add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} }
set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset]
add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]]
link_design
read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd"
if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} {
puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo"
}

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Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design SpecialCasesCheck.ngc ...
WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf,
ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SpecialCasesCheck.edif ...
ngc2edif: Total memory usage is 103004 kilobytes

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#-------------------------------------------------------------------------------
# PlanAhead v14.7 (64-bit)
# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
# Current time: 8/24/19 2:52:26 PM
# Process ID: 7025
# Platform: Unix
#
# This file is an indication that an internal application error occurred.
# This information is useful for debugging. Please open a case with Xilinx
# Technical Support with this file and a testcase attached.
#-------------------------------------------------------------------------------
8/24/19 2:52:26 PM
ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR
HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR
HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR
HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR
at ui.h.e.CF(SourceFile:217)
at ui.h.I.CF(SourceFile:702)
at ui.frmwork.HTclEventBroker.a(SourceFile:368)
at ui.frmwork.HTclEventBroker.bb(SourceFile:354)
at ui.project.a.een(SourceFile:759)
at ui.project.a.cleanup(SourceFile:608)
at ui.project.r.cleanup(SourceFile:631)
at ui.PlanAhead.aJj(SourceFile:335)
at ui.PlanAhead.a(SourceFile:1192)
at ui.frmwork.a.i.c(SourceFile:35)
at ui.frmwork.HTclEventBroker.a(SourceFile:233)
at ui.frmwork.HTclEventBroker.fireTclEvent(SourceFile:325)
at ui.frmwork.tcltasksi.task_manager_eval_in_tcl_or_bad_alloc(Native Method)
at ui.e.gY(SourceFile:195)
at ui.bl.run(SourceFile:882)
at ui.cd.run(SourceFile:1821)
at ui.views.F.aw.a(SourceFile:341)
at ui.cd.b(SourceFile:1809)
at ui.cd.a(SourceFile:1784)
at ui.PlanAhead.a(SourceFile:778)
at ui.aL.c(SourceFile:885)
at ui.aL.aHs(SourceFile:824)
at ui.bk.windowClosing(SourceFile:503)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:350)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.AWTEventMulticaster.windowClosing(AWTEventMulticaster.java:349)
at java.awt.Window.processWindowEvent(Window.java:2051)
at javax.swing.JFrame.processWindowEvent(JFrame.java:296)
at java.awt.Window.processEvent(Window.java:2009)
at ui.aL.processEvent(SourceFile:1214)
at java.awt.Component.dispatchEventImpl(Component.java:4861)
at java.awt.Container.dispatchEventImpl(Container.java:2287)
at java.awt.Window.dispatchEventImpl(Window.java:2719)
at java.awt.Component.dispatchEvent(Component.java:4687)
at java.awt.EventQueue.dispatchEventImpl(EventQueue.java:729)
at java.awt.EventQueue.access$200(EventQueue.java:103)
at java.awt.EventQueue$3.run(EventQueue.java:688)
at java.awt.EventQueue$3.run(EventQueue.java:686)
at java.security.AccessController.doPrivileged(Native Method)
at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:87)
at java.awt.EventQueue$4.run(EventQueue.java:702)
at java.awt.EventQueue$4.run(EventQueue.java:700)
at java.security.AccessController.doPrivileged(Native Method)
at java.security.ProtectionDomain$1.doIntersectionPrivilege(ProtectionDomain.java:76)
at java.awt.EventQueue.dispatchEvent(EventQueue.java:699)
at ui.frmwork.a.e.dispatchEvent(SourceFile:73)
at java.awt.EventDispatchThread.pumpOneEventForFilters(EventDispatchThread.java:242)
at java.awt.EventDispatchThread.pumpEventsForFilter(EventDispatchThread.java:161)
at java.awt.EventDispatchThread.pumpEventsForHierarchy(EventDispatchThread.java:150)
at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:146)
at java.awt.EventDispatchThread.pumpEvents(EventDispatchThread.java:138)
at java.awt.EventDispatchThread.run(EventDispatchThread.java:91)

1762
planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif vendored Normal file
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File diff suppressed because it is too large Load Diff

16
planAhead_run_1/IEEE754Adder.data/constrs_1/fileset.xml Normal file
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@@ -0,0 +1,16 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="constrs_1" Type="Constrs" RelSrcDir="$PSRCDIR/constrs_1">
<Filter Type="Constrs"/>
<File Path="$PPRDIR/../SpecialCasesCheck.ucf">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="TargetConstrsFile" Val="$PPRDIR/../SpecialCasesCheck.ucf"/>
<Option Name="ConstrsType" Val="UCF"/>
</Config>
</FileSet>
</DARoots>

20
planAhead_run_1/IEEE754Adder.data/runs/impl_1.psg Normal file
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@@ -0,0 +1,20 @@
<?xml version="1.0"?>
<Strategy Version="1" Minor="2">
<StratHandle Name="ISE Defaults" Flow="ISE14">
<Desc>ISE Defaults, including packing registers in IOs off</Desc>
</StratHandle>
<Step Id="ngdbuild">
</Step>
<Step Id="map">
<Option Id="FFPackEnum">3</Option>
</Step>
<Step Id="par">
</Step>
<Step Id="trce">
</Step>
<Step Id="xdl">
</Step>
<Step Id="bitgen">
</Step>
</Strategy>

5
planAhead_run_1/IEEE754Adder.data/runs/runs.xml Normal file
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@@ -0,0 +1,5 @@
<?xml version="1.0"?>
<Runs Version="1" Minor="8">
<Run Id="impl_1" Type="Ft2:EntireDesign" SrcSet="sources_1" Part="xa6slx4csg225-3" ConstrsSet="constrs_1" Description="ISE Defaults, including packing registers in IOs off" State="current"/>
</Runs>

10
planAhead_run_1/IEEE754Adder.data/sim_1/fileset.xml Normal file
View File

@@ -0,0 +1,10 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sim_1" Type="SimulationSrcs" RelSrcDir="$PSRCDIR/sim_1">
<Config>
<Option Name="DesignMode" Val="RTL"/>
<Option Name="TopAutoSet" Val="TRUE"/>
<Option Name="SrcSet" Val="sources_1"/>
</Config>
</FileSet>
</DARoots>

30
planAhead_run_1/IEEE754Adder.data/sources_1/fileset.xml Normal file
View File

@@ -0,0 +1,30 @@
<?xml version="1.0" encoding="UTF-8"?>
<DARoots Version="1" Minor="26">
<FileSet Name="sources_1" Type="DesignSrcs" RelSrcDir="$PSRCDIR/sources_1">
<Filter Type="EDIFSrcs"/>
<File Path="$PPRDIR/../SpecialCasesCheck.ngc">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../equalCheck.ngc">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<File Path="$PPRDIR/../TypeCheck.ngc">
<FileInfo>
<Attr Name="UsedInSynthesis" Val="1"/>
<Attr Name="UsedInImplementation" Val="1"/>
</FileInfo>
</File>
<Config>
<Option Name="DesignMode" Val="GateLvl"/>
<Option Name="GateLvlMode" Val="EDIF"/>
<Option Name="TopFile" Val="$PPRDIR/../SpecialCasesCheck.ngc"/>
<Option Name="TopAutoSet" Val="TRUE"/>
</Config>
</FileSet>
</DARoots>

3
planAhead_run_1/IEEE754Adder.data/wt/java_command_handlers.wdf Normal file
View File

@@ -0,0 +1,3 @@
version:1
70726f6a656374:706c616e5f61686561645f75736167655c6a6176615f636f6d6d616e645f68616e646c657273:7a6f6f6d696e:35:00:00
eof:3762079013

4
planAhead_run_1/IEEE754Adder.data/wt/project.wpc Normal file
View File

@@ -0,0 +1,4 @@
version:1
6d6f64655f636f756e7465727c4755494d6f6465:1
6d6f64655f636f756e7465727c4953454d6f6465:1
eof:

29
planAhead_run_1/IEEE754Adder.data/wt/webtalk_pa.xml Normal file
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@@ -0,0 +1,29 @@
<?xml version="1.0" encoding="UTF-8" ?>
<document>
<!--The data in this file is primarily intended for consumption by Xilinx tools.
The structure and the elements are likely to change over the next few releases.
This means code written to parse this file will need to be revisited each subsequent release.-->
<application name="pa" timeStamp="Sat Aug 24 14:52:23 2019">
<section name="Project Information" visible="false">
<property name="ProjectID" value="e7a017e01966464abdfa199c35ad33a2" type="ProjectID"/>
<property name="ProjectIteration" value="1" type="ProjectIteration"/>
</section>
<section name="PlanAhead Usage" visible="true">
<item name="Project Data">
<property name="SrcSetCount" value="1" type="SrcSetCount"/>
<property name="ConstraintSetCount" value="1" type="ConstraintSetCount"/>
<property name="DesignMode" value="GateLvl" type="DesignMode"/>
<property name="ImplStrategy" value="ISE Defaults" type="ImplStrategy"/>
</item>
<item name="Java Command Handlers">
<property name="ZoomIn" value="5" type="JavaHandler"/>
</item>
<item name="Other">
<property name="GuiMode" value="0" type="GuiMode"/>
<property name="BatchMode" value="0" type="BatchMode"/>
<property name="TclMode" value="0" type="TclMode"/>
<property name="ISEMode" value="1" type="ISEMode"/>
</item>
</section>
</application>
</document>

28
planAhead_run_1/IEEE754Adder.ppr Normal file
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@@ -0,0 +1,28 @@
<?xml version="1.0"?>
<!--Product Version: PlanAhead v14.7 (64-bit)-->
<Project Version="4" Minor="36">
<FileSet Dir="sources_1" File="fileset.xml"/>
<FileSet Dir="constrs_1" File="fileset.xml"/>
<FileSet Dir="sim_1" File="fileset.xml"/>
<RunSet Dir="runs" File="runs.xml"/>
<DefaultLaunch Dir="$PRUNDIR"/>
<DefaultPromote Dir="$PROMOTEDIR"/>
<Config>
<Option Name="Id" Val="45689c7b25ae425b84c8ab3f166c9430"/>
<Option Name="Part" Val="xa6slx4csg225-3"/>
<Option Name="CompiledLibDir" Val="$PCACHEDIR/compile_simlib"/>
<Option Name="TargetLanguage" Val="Verilog"/>
<Option Name="TargetSimulator" Val="ISim"/>
<Option Name="Board" Val=""/>
<Option Name="SourceMgmtMode" Val="All"/>
<Option Name="ActiveSimSet" Val="sim_1"/>
<Option Name="CxlOverwriteLibs" Val="1"/>
<Option Name="CxlFuncsim" Val="1"/>
<Option Name="CxlTimesim" Val="1"/>
<Option Name="CxlCore" Val="1"/>
<Option Name="CxlEdk" Val="0"/>
<Option Name="CxlExcludeCores" Val="1"/>
<Option Name="CxlExcludeSubLibs" Val="0"/>
</Config>
</Project>

10
planAhead_run_1/planAhead.jou Normal file
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@@ -0,0 +1,10 @@
#-----------------------------------------------------------
# PlanAhead v14.7 (64-bit)
# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
# Start of session at: Sat Aug 24 14:51:32 2019
# Process ID: 7025
# Log file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.log
# Journal file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
start_gui
source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl

83
planAhead_run_1/planAhead.log Normal file
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@@ -0,0 +1,83 @@
#-----------------------------------------------------------
# PlanAhead v14.7 (64-bit)
# Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
# Start of session at: Sat Aug 24 14:51:32 2019
# Process ID: 7025
# Log file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.log
# Journal file: /home/Luca/ISE/IEEE754Adder/planAhead_run_1/planAhead.jou
#-----------------------------------------------------------
INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl
# create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3
# set srcset [get_property srcset [current_run -impl]]
# set_property design_mode GateLvl $srcset
# set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} }
# set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset]
Adding file '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf' to fileset 'constrs_1'
# add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]]
# link_design
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xa6slx4csg225-3
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design SpecialCasesCheck.ngc ...
WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf,
ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SpecialCasesCheck.edif ...
ngc2edif: Total memory usage is 103004 kilobytes
Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
Finished Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockRegion.xml
Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockBuffers.xml
Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/csg225/Package.xml
Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
Finished Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Phase 0 | Netlist Checksum: 684e9dfa
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2835.180 ; gain = 156.531
# read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd"
Release 14.7 - xdl P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3
Successfully converted design '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd' to '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xdl'.
INFO: [Designutils 20-669] Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
INFO: [Designutils 20-658] Finished Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
INFO: [Designutils 20-671] Placed 103 instances
read_xdl: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2835.180 ; gain = 0.000
# if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} {
# puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo"
# }
exit
ERROR: [#UNDEF] *** Exception: ui.h.b: Found deleted key in HTclEventBroker. Verify if the classes listed here call cleanup()
HTclEvent: DEBUG_CORE_CONFIG_CHANGE Classes: ui.views.aR
HTclEvent: SIGNAL_BUS_MODIFY Classes: ui.views.aR
HTclEvent: SIGNAL_MODIFY Classes: ui.views.aR
HTclEvent: DEBUG_PORT_CONFIG_CHANGE Classes: ui.views.aR
(See /home/Luca/ISE/IEEE754Adder/planAhead_pid7025.debug)
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
INFO: [Common 17-206] Exiting PlanAhead at Sat Aug 24 14:52:27 2019...
INFO: [Common 17-83] Releasing license: PlanAhead

74
planAhead_run_1/planAhead_run.log Normal file
View File

@@ -0,0 +1,74 @@
****** PlanAhead v14.7 (64-bit)
**** Build 321239 by xbuild on Fri Sep 27 19:24:36 MDT 2013
** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.
INFO: [Common 17-78] Attempting to get a license: PlanAhead
INFO: [Common 17-290] Got license for PlanAhead
INFO: [Device 21-36] Loading parts and site information from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/arch.xml
Parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
Finished parsing RTL primitives file [/opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/rtl/prims/rtl_prims.xml]
start_gui
source /home/Luca/ISE/IEEE754Adder/pa.fromNcd.tcl
# create_project -name IEEE754Adder -dir "/home/Luca/ISE/IEEE754Adder/planAhead_run_1" -part xa6slx4csg225-3
# set srcset [get_property srcset [current_run -impl]]
# set_property design_mode GateLvl $srcset
# set_property edif_top_file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ngc" [ get_property srcset [ current_run ] ]
# add_files -norecurse { {/home/Luca/ISE/IEEE754Adder} }
# set_property target_constrs_file "SpecialCasesCheck.ucf" [current_fileset -constrset]
Adding file '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf' to fileset 'constrs_1'
# add_files [list {SpecialCasesCheck.ucf}] -fileset [get_property constrset [current_run]]
# link_design
Design is defaulting to srcset: sources_1
Design is defaulting to constrset: constrs_1
Design is defaulting to project part: xa6slx4csg225-3
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Release 14.7 - ngc2edif P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
Reading design SpecialCasesCheck.ngc ...
WARNING:NetListWriters:298 - No output is written to SpecialCasesCheck.xncf,
ignored.
Processing design ...
Preping design's networks ...
Preping design's macros ...
finished :Prep
Writing EDIF netlist file SpecialCasesCheck.edif ...
ngc2edif: Total memory usage is 103004 kilobytes
Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
Finished Parsing EDIF File [./planAhead_run_1/IEEE754Adder.data/cache/SpecialCasesCheck_ngc_ec4f3bca.edif]
Loading clock regions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockRegion.xml
Loading clock buffers from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/ClockBuffers.xml
Loading package pin functions from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/PinFunctions.xml...
Loading package from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/aspartan6/xa6slx4/csg225/Package.xml
Loading io standards from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/IOStandards.xml
Loading device configuration modes from /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/parts/xilinx/spartan6/ConfigModes.xml
Loading list of drcs for the architecture : /opt/Xilinx/14.7/ISE_DS/PlanAhead/data/./parts/xilinx/spartan6/drc.xml
Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
Finished Parsing UCF File [/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ucf]
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
Phase 0 | Netlist Checksum: 684e9dfa
link_design: Time (s): cpu = 00:00:11 ; elapsed = 00:00:07 . Memory (MB): peak = 2835.180 ; gain = 156.531
# read_xdl -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd"
Release 14.7 - xdl P.20131013 (lin64)
Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved.
WARNING:XDL:213 - The resulting xdl output will not have LUT equation strings or RAM INIT strings.
Loading device for application Rf_Device from file '6slx4.nph' in environment /opt/Xilinx/14.7/ISE_DS/ISE/.
"SpecialCasesCheck" is an NCD, version 3.2, device xa6slx4, package csg225, speed -3
Successfully converted design '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd' to '/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.xdl'.
INFO: [Designutils 20-669] Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
INFO: [Designutils 20-658] Finished Parsing Placement File : /home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.ncd
INFO: [Designutils 20-671] Placed 103 instances
read_xdl: Time (s): cpu = 00:00:09 ; elapsed = 00:00:06 . Memory (MB): peak = 2835.180 ; gain = 0.000
# if {[catch {read_twx -name results_1 -file "/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx"} eInfo]} {
# puts "WARNING: there was a problem importing \"/home/Luca/ISE/IEEE754Adder/SpecialCasesCheck.twx\": $eInfo"
# }
exit
ERROR: [Common 17-39] 'stop_gui' failed due to earlier errors.
INFO: [Common 17-206] Exiting PlanAhead at Sat Aug 24 14:52:27 2019...
INFO: [Common 17-83] Releasing license: PlanAhead