Sommatore 1

AddSub.vhd

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+library IEEE;
+use IEEE.STD_LOGIC_1164.ALL;
+
+
+entity AddSub is
+	generic( BITCOUNT: integer := 8 );
+	port(
+		X, Y: in std_logic_vector((BITCOUNT-1) downto 0);
+		isSub: in std_logic := 0;
+		result: out std_logic_vector((BITCOUNT-1) downto 0)
+	);
+end AddSub;
+
+architecture CLAAddSubArch of AddSub is
+
+begin
+
+
+end CLAAddSubArch;
+