diff --git a/IEEE754Adder.xise b/IEEE754Adder.xise
index ee9e06d..f45da8d 100644
--- a/IEEE754Adder.xise
+++ b/IEEE754Adder.xise
@@ -42,7 +42,7 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="96"/>
     </file>
     <file xil_pn:name="Comparator.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="5"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="10"/>
     </file>
     <file xil_pn:name="ComparatorTest.vhd" xil_pn:type="FILE_VHDL">
@@ -80,11 +80,11 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="227"/>
     </file>
     <file xil_pn:name="Adder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="4"/>
     </file>
     <file xil_pn:name="AddSub.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="6"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="11"/>
     </file>
     <file xil_pn:name="AddSubTest.vhd" xil_pn:type="FILE_VHDL">
@@ -106,7 +106,7 @@
       <association xil_pn:name="Implementation" xil_pn:seqID="14"/>
     </file>
     <file xil_pn:name="Normalizer.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="7"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="19"/>
     </file>
     <file xil_pn:name="SumDataAdapterTest.vhd" xil_pn:type="FILE_VHDL">
@@ -140,57 +140,63 @@
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="279"/>
     </file>
     <file xil_pn:name="ZeroCounter.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="3"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="5"/>
     </file>
     <file xil_pn:name="ZeroCounterTest.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="255"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="255"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="255"/>
     </file>
     <file xil_pn:name="ShiftLeft.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="4"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="8"/>
     </file>
     <file xil_pn:name="UTILS.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="1"/>
     </file>
     <file xil_pn:name="OutputSelector.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="1"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="17"/>
     </file>
     <file xil_pn:name="OutputSelectorTest.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="2"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="PostMapSimulation" xil_pn:seqID="305"/>
       <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="305"/>
       <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="305"/>
     </file>
     <file xil_pn:name="PipelineStageOne.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="318"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="23"/>
     </file>
     <file xil_pn:name="PipelineStageTwo.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="329"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="21"/>
     </file>
     <file xil_pn:name="PipelineStageThree.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="350"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="22"/>
     </file>
     <file xil_pn:name="IEEE754Adder.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="362"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="26"/>
     </file>
     <file xil_pn:name="FlipFlopD.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="363"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="25"/>
     </file>
     <file xil_pn:name="FlipFlopDVector.vhd" xil_pn:type="FILE_VHDL">
-      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="375"/>
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="0"/>
       <association xil_pn:name="Implementation" xil_pn:seqID="24"/>
     </file>
+    <file xil_pn:name="NormalizerTest.vhd" xil_pn:type="FILE_VHDL">
+      <association xil_pn:name="BehavioralSimulation" xil_pn:seqID="8"/>
+      <association xil_pn:name="PostMapSimulation" xil_pn:seqID="336"/>
+      <association xil_pn:name="PostRouteSimulation" xil_pn:seqID="336"/>
+      <association xil_pn:name="PostTranslateSimulation" xil_pn:seqID="336"/>
+    </file>
   </files>
 
   <properties>
@@ -449,8 +455,8 @@
     <property xil_pn:name="Run for Specified Time Translate" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Safe Implementation" xil_pn:value="No" xil_pn:valueState="default"/>
     <property xil_pn:name="Security" xil_pn:value="Enable Readback and Reconfiguration" xil_pn:valueState="default"/>
-    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/ZeroCounterTest" xil_pn:valueState="non-default"/>
-    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.ZeroCounterTest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Module Instance Name" xil_pn:value="/NormalizerTest" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="Selected Simulation Root Source Node Behavioral" xil_pn:value="work.NormalizerTest" xil_pn:valueState="non-default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Map" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Route" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="Selected Simulation Root Source Node Post-Translate" xil_pn:value="" xil_pn:valueState="default"/>
@@ -469,7 +475,7 @@
     <property xil_pn:name="Slice Packing" xil_pn:value="true" xil_pn:valueState="default"/>
     <property xil_pn:name="Slice Utilization Ratio" xil_pn:value="100" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify 'define Macro Name and Value" xil_pn:value="" xil_pn:valueState="default"/>
-    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.ZeroCounterTest" xil_pn:valueState="default"/>
+    <property xil_pn:name="Specify Top Level Instance Names Behavioral" xil_pn:value="work.NormalizerTest" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Map" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Route" xil_pn:value="Default" xil_pn:valueState="default"/>
     <property xil_pn:name="Specify Top Level Instance Names Post-Translate" xil_pn:value="Default" xil_pn:valueState="default"/>
@@ -525,7 +531,7 @@
     <!--                                                                                  -->
     <!-- The following properties are for internal use only. These should not be modified.-->
     <!--                                                                                  -->
-    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|OutputSelectorTest|behavior" xil_pn:valueState="non-default"/>
+    <property xil_pn:name="PROP_BehavioralSimTop" xil_pn:value="Architecture|NormalizerTest|behavior" xil_pn:valueState="non-default"/>
     <property xil_pn:name="PROP_DesignName" xil_pn:value="" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_DevFamilyPMName" xil_pn:value="spartan6" xil_pn:valueState="default"/>
     <property xil_pn:name="PROP_FPGAConfiguration" xil_pn:value="FPGAConfiguration" xil_pn:valueState="default"/>
diff --git a/Normalizer.vhd b/Normalizer.vhd
index cadd6c7..8d43721 100644
--- a/Normalizer.vhd
+++ b/Normalizer.vhd
@@ -94,9 +94,9 @@ begin
 			EXP_ADD_RIGHT <= "00000001";
 			EXP_ADD_ISSUB <= '0';
 		elsif (IS_FINAL_EXP_MINIMUM = '1') then
-			EXP_ADD_LEFT <= "01111111"; --127
-			EXP_ADD_RIGHT <= EXP;
-			EXP_ADD_ISSUB <= '1';
+			EXP_ADD_LEFT <= "00000000";
+			EXP_ADD_RIGHT <= "00000000";
+			EXP_ADD_ISSUB <= '0';
 		else
 			EXP_ADD_LEFT <= EXP;
 			EXP_ADD_RIGHT <= ZERO_COUNT;
@@ -108,10 +108,10 @@ begin
 		generic map ( BITCOUNT => 8 )
 		port map ( X => EXP_ADD_LEFT, Y => EXP_ADD_RIGHT, IS_SUB => EXP_ADD_ISSUB, RESULT => EXP_ADDSUB_RES, OVERFLOW => EXP_ADDSUB_OF );
 
-	shift_process: process (IS_FINAL_EXP_MINIMUM, EXP_ADDSUB_RES, ZERO_COUNT)
+	shift_process: process (IS_FINAL_EXP_MINIMUM, EXP, ZERO_COUNT)
 	begin
 		if (IS_FINAL_EXP_MINIMUM = '1') then
-			LEFT_SHIFT_AMOUNT <= '0' & EXP_ADDSUB_RES;
+			LEFT_SHIFT_AMOUNT <= '0' & EXP;
 		else
 			LEFT_SHIFT_AMOUNT <= '0' & ZERO_COUNT;
 		end if;
@@ -123,30 +123,31 @@ begin
 		port map ( N => MANT, PLACES => LEFT_SHIFT_AMOUNT, RESULT => LEFT_SHIFTED_MANT_TMP );
 	LEFT_SHIFTED_MANT <= LEFT_SHIFTED_MANT_TMP(47 downto 25);
 	
-	final_process: process (SUM_OVERFLOW, IS_FINAL_EXP_MINIMUM, EXP_ADDSUB_RES, EXP_ADDSUB_OF, RIGHT_SHIFTED_MANT, LEFT_SHIFTED_MANT)
+	final_process: process (SUM_OVERFLOW, IS_FINAL_EXP_MINIMUM, EXP_ADDSUB_RES, EXP_ADDSUB_OF, RIGHT_SHIFTED_MANT, LEFT_SHIFTED_MANT, EXP)
 		variable IS_INF : std_logic;
+		variable IS_INF_ORIGINAL_EXP : std_logic;
+		variable IS_INF_FINAL_EXP : std_logic;
 	begin
-		if (SUM_OVERFLOW = '1') then
-			IS_INF := '1';
-			for i in EXP_ADDSUB_RES'range loop
-				IS_INF := IS_INF and EXP_ADDSUB_RES(i);
-			end loop;
-			IS_INF := IS_INF or EXP_ADDSUB_OF;
-			
-			if (IS_INF = '1') then
-				FINAL_EXP <= "11111111";
-				FINAL_MANT <= "00000000000000000000000";
-			else
+		IS_INF_ORIGINAL_EXP  := '1';
+		for i in EXP'range loop
+			IS_INF_ORIGINAL_EXP := IS_INF_ORIGINAL_EXP and EXP(i);
+		end loop;
+		IS_INF_FINAL_EXP := '1';
+		for i in EXP_ADDSUB_RES'range loop
+			IS_INF_FINAL_EXP := IS_INF_FINAL_EXP and EXP_ADDSUB_RES(i);
+		end loop;
+		IS_INF := IS_INF_ORIGINAL_EXP or IS_INF_FINAL_EXP or EXP_ADDSUB_OF;
+		
+		if (IS_INF = '1') then
+			FINAL_EXP <= "11111111";
+			FINAL_MANT <= "00000000000000000000000";
+		else
+			if (SUM_OVERFLOW = '1') then
 				FINAL_EXP <= EXP_ADDSUB_RES;
 				FINAL_MANT <= RIGHT_SHIFTED_MANT;
-			end if;
-		else
-			if (IS_FINAL_EXP_MINIMUM = '1') then
-				FINAL_EXP <= "00000000";
-				FINAL_MANT <= LEFT_SHIFTED_MANT;
 			else
 				FINAL_EXP <= EXP_ADDSUB_RES;
-				FINAL_MANT <= LEFT_SHIFTED_MANT;
+				FINAL_MANT <= LEFT_SHIFTED_MANT;			
 			end if;
 		end if;
 	end process;
diff --git a/NormalizerTest.vhd b/NormalizerTest.vhd
new file mode 100644
index 0000000..6d1ed2a
--- /dev/null
+++ b/NormalizerTest.vhd
@@ -0,0 +1,111 @@
+LIBRARY ieee;
+USE ieee.std_logic_1164.ALL;
+
+ 
+ENTITY NormalizerTest IS
+END NormalizerTest;
+ 
+ARCHITECTURE behavior OF NormalizerTest IS 
+ 
+    -- Component Declaration for the Unit Under Test (UUT)
+ 
+    COMPONENT Normalizer
+    PORT(
+         SIGN : IN  std_logic;
+         EXP : IN  std_logic_vector(7 downto 0);
+         MANT : IN  std_logic_vector(47 downto 0);
+         SUM_OVERFLOW : IN  std_logic;
+         IEEE_754_SUM : OUT  std_logic_vector(31 downto 0)
+        );
+    END COMPONENT;
+    
+
+   --Inputs
+   signal SIGN : std_logic := '0';
+   signal EXP : std_logic_vector(7 downto 0) := (others => '0');
+   signal MANT : std_logic_vector(47 downto 0) := (others => '0');
+   signal SUM_OVERFLOW : std_logic := '0';
+
+ 	--Outputs
+   signal IEEE_754_SUM : std_logic_vector(31 downto 0);
+ 
+   constant clock_period : time := 10 ns;
+	signal clock : std_logic;
+ 
+BEGIN
+ 
+	-- Instantiate the Unit Under Test (UUT)
+   uut: Normalizer PORT MAP (
+          SIGN => SIGN,
+          EXP => EXP,
+          MANT => MANT,
+          SUM_OVERFLOW => SUM_OVERFLOW,
+          IEEE_754_SUM => IEEE_754_SUM
+        );
+
+   -- Clock process definitions
+   clock_process :process
+   begin
+		clock <= '0';
+		wait for clock_period/2;
+		clock <= '1';
+		wait for clock_period/2;
+   end process;
+ 
+
+   -- Stimulus process
+   stim_proc: process
+   begin
+		SIGN <= '1';
+		EXP <= "10010100";
+		MANT <= "100101010001001001000001111101010000001000110001";
+		SUM_OVERFLOW <= '1';
+      wait for clock_period;
+		SIGN <= '1';
+		EXP <= "10010100";
+		MANT <= "000000000000000000000000000000000000000000000000";
+		SUM_OVERFLOW <= '0';
+      wait for clock_period;
+		SIGN <= '1';
+		EXP <= "00000010";
+		MANT <= "000000010001001001000001111101010000001000110001";
+		SUM_OVERFLOW <= '0';
+      wait for clock_period;
+		SIGN <= '1';
+		EXP <= "11111110";
+		MANT <= "111111111111111111111111111111111111111111111111";
+		SUM_OVERFLOW <= '0';
+      wait for clock_period;
+		SIGN <= '1';
+		EXP <= "11111110";
+		MANT <= "111111111111111111111111111111111111111111111111";
+		SUM_OVERFLOW <= '0';
+      wait for clock_period;
+		SIGN <= '1';
+		EXP <= "11111111";
+		MANT <= "100101010001001001000001111101010000001000110001";
+		SUM_OVERFLOW <= '0';
+      wait for clock_period;
+		SIGN <= '1';
+		EXP <= "11111111";
+		MANT <= "100101010001001001000001111101010000001000110001";
+		SUM_OVERFLOW <= '1';
+      wait for clock_period;
+		SIGN <= '1';
+		EXP <= "11111111";
+		MANT <= "000000000000001001000001111101010000001000110001";
+		SUM_OVERFLOW <= '0';
+      wait for clock_period;
+		SIGN <= '1';
+		EXP <= "00000001";
+		MANT <= "010101010001001001000001111101010000001000110001";
+		SUM_OVERFLOW <= '0';
+      wait for clock_period;
+		SIGN <= '1';
+		EXP <= "00000000";
+		MANT <= "100101010001001001000001111101010000001000110001";
+		SUM_OVERFLOW <= '0';
+      wait for clock_period;
+   end process;
+
+END;
diff --git a/NormalizerTest_isim_beh.exe b/NormalizerTest_isim_beh.exe
new file mode 100755
index 0000000..3209988
Binary files /dev/null and b/NormalizerTest_isim_beh.exe differ
diff --git a/NormalizerTest_isim_beh.wdb b/NormalizerTest_isim_beh.wdb
new file mode 100644
index 0000000..8e3ff7f
Binary files /dev/null and b/NormalizerTest_isim_beh.wdb differ
diff --git a/NormalizerTest_isim_beh2.wdb b/NormalizerTest_isim_beh2.wdb
new file mode 100644
index 0000000..2697d18
Binary files /dev/null and b/NormalizerTest_isim_beh2.wdb differ
diff --git a/Normalizer_isim_beh.exe b/Normalizer_isim_beh.exe
new file mode 100755
index 0000000..3209988
Binary files /dev/null and b/Normalizer_isim_beh.exe differ
diff --git a/fuse.log b/fuse.log
index 6e4d842..eeb1191 100644
--- a/fuse.log
+++ b/fuse.log
@@ -1,21 +1,36 @@
-Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/ise/gianni/IEEE754Adder/OutputSelectorTest_isim_beh.exe -prj /home/ise/gianni/IEEE754Adder/OutputSelectorTest_beh.prj work.OutputSelectorTest 
-ISim P.20160913 (signature 0xfbc00daa)
-Number of CPUs detected in this system: 1
-Turning on mult-threading, number of parallel sub-compilation jobs: 0 
+Running: /opt/Xilinx/14.7/ISE_DS/ISE/bin/lin64/unwrapped/fuse -intstyle ise -incremental -lib secureip -o /home/Luca/ISE/IEEE754Adder/NormalizerTest_isim_beh.exe -prj /home/Luca/ISE/IEEE754Adder/NormalizerTest_beh.prj work.NormalizerTest 
+ISim P.20131013 (signature 0xfbc00daa)
+Number of CPUs detected in this system: 4
+Turning on mult-threading, number of parallel sub-compilation jobs: 8 
 Determining compilation order of HDL files
-Parsing VHDL file "/home/ise/gianni/IEEE754Adder/OutputSelector.vhd" into library work
-Parsing VHDL file "/home/ise/gianni/IEEE754Adder/OutputSelectorTest.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/UTILS.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Adder.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ZeroCounter.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/ShiftLeft.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Comparator.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/AddSub.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/Normalizer.vhd" into library work
+Parsing VHDL file "/home/Luca/ISE/IEEE754Adder/NormalizerTest.vhd" into library work
 Starting static elaboration
 Completed static elaboration
-Fuse Memory Usage: 95300 KB
-Fuse CPU Usage: 2310 ms
+Fuse Memory Usage: 96516 KB
+Fuse CPU Usage: 1020 ms
 Compiling package standard
 Compiling package std_logic_1164
-Compiling architecture outputselectorarch of entity OutputSelector [outputselector_default]
-Compiling architecture behavior of entity outputselectortest
+Compiling package numeric_std
+Compiling package math_real
+Compiling package utils
+Compiling architecture zerocounterarch of entity ZeroCounter [\ZeroCounter(48,8)\]
+Compiling architecture comparatorarch of entity Comparator [\Comparator(8)\]
+Compiling architecture carrylookaheadarch of entity Adder [\Adder(8)\]
+Compiling architecture addsubarch of entity AddSub [\AddSub(8)\]
+Compiling architecture shiftleftarch of entity ShiftLeft48 [shiftleft48_default]
+Compiling architecture normalizerarch of entity Normalizer [normalizer_default]
+Compiling architecture behavior of entity normalizertest
 Time Resolution for simulation is 1ps.
-Compiled 5 VHDL Units
-Built simulation executable /home/ise/gianni/IEEE754Adder/OutputSelectorTest_isim_beh.exe
-Fuse Memory Usage: 103948 KB
-Fuse CPU Usage: 2410 ms
-GCC CPU Usage: 550 ms
+Waiting for 1 sub-compilation(s) to finish...
+Compiled 18 VHDL Units
+Built simulation executable /home/Luca/ISE/IEEE754Adder/NormalizerTest_isim_beh.exe
+Fuse Memory Usage: 670604 KB
+Fuse CPU Usage: 1130 ms
+GCC CPU Usage: 480 ms
diff --git a/fuseRelaunch.cmd b/fuseRelaunch.cmd
index 27fca25..4f1cf30 100644
--- a/fuseRelaunch.cmd
+++ b/fuseRelaunch.cmd
@@ -1 +1 @@
--intstyle "ise" -incremental -lib "secureip" -o "/home/ise/gianni/IEEE754Adder/OutputSelectorTest_isim_beh.exe" -prj "/home/ise/gianni/IEEE754Adder/OutputSelectorTest_beh.prj" "work.OutputSelectorTest" 
+-intstyle "ise" -incremental -lib "secureip" -o "/home/Luca/ISE/IEEE754Adder/NormalizerTest_isim_beh.exe" -prj "/home/Luca/ISE/IEEE754Adder/NormalizerTest_beh.prj" "work.NormalizerTest"