Comopletato sommatore-sottrattore con test

AdderTest.vhd

@@ -1,37 +1,6 @@
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--- Company: 
--- Engineer:
---
--- Create Date:   17:01:26 08/24/2019
--- Design Name:   
--- Module Name:   /home/Luca/ISE/IEEE754Adder/AdderTest.vhd
--- Project Name:  IEEE754Adder
--- Target Device:  
--- Tool versions:  
--- Description:   
--- 
--- VHDL Test Bench Created by ISE for module: Adder
--- 
--- Dependencies:
--- 
--- Revision:
--- Revision 0.01 - File Created
--- Additional Comments:
---
--- Notes: 
--- This testbench has been automatically generated using types std_logic and
--- std_logic_vector for the ports of the unit under test.  Xilinx recommends
--- that these types always be used for the top-level I/O of a design in order
--- to guarantee that the testbench will bind correctly to the post-implementation 
--- simulation model.
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 LIBRARY ieee;
 USE ieee.std_logic_1164.ALL;
  
--- Uncomment the following library declaration if using
--- arithmetic functions with Signed or Unsigned values
---USE ieee.numeric_std.ALL;
- 
 ENTITY AdderTest IS
 END AdderTest;